JPH01147638A - Instruction execution detector - Google Patents

Abstract

PURPOSE:To easily decide whether a microprocessor has executed a prescribed instruction or not by replacing forcibly the instruction code of an address to be executed and decided with another specific instruction code. CONSTITUTION:A comparison address generating circuit 4 detects a bus cycle where the instruction code of a designated address is prefetched by a microprocessor 1 and fetches forcibly the instruction code to be unconditionally branched to a known address into said bus cycle in place of the instruction code to be originally fetched. Then an address coincidence detecting circuit checks whether a branch address is delivered onto an address bus or not. When the address coincidence is detected, the original instruction code is fetched and at the same time a signal showing that a designated instruction code is carried out by the processor 1 is transmitted through a gate 11.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an in-circuit emulator for a microprocessor that performs instruction prefetching for determining whether a prefetched instruction has been moved to execution processing or ignored. Regarding the device.

[Prior Art] Modern microprocessors, especially those with 16 bits or more, often perform instruction prefetching to improve processing speed. Such microprocessors generally have a built-in buffer memory called an instruction queue. , an instruction at an address up to several bytes ahead of the instruction actually being executed within the microprocessor is fetched.

However, not all instructions captured in the instruction queue will be executed, and if a JUMP instruction etc. is executed,
Clears the instruction queue and processes new instructions. Therefore, in-circuit emulators for such microprocessors often include a circuit that determines in real time whether an instruction at a certain address has been actually executed or discarded from the instruction queue. are doing.

Generally, this judgment circuit learns the internal state of the instruction queue either directly by the queue status output by the microprocessor, or indirectly by preparing a memory in which the total number of instruction cycles is registered and referring to it. This is achieved by

[Problems that the invention attempts to solve]However, some of the problems that the invention attempts to solve include
There are also microprocessors such as 86 that do not output queue status to the outside, and conventional methods cannot be applied to such microprocessors, so it is possible to determine the execution of instructions in real time without affecting the processing operations of the microprocessor. is difficult to do.

An object of the present invention has been made in view of the above-mentioned points.The present invention has been made in view of the above-mentioned points, and is capable of determining the address of a microprocessor that is unable to determine whether to execute an instruction by monitoring signals from outside the microprocessor. An object of the present invention is to provide an instruction execution detection device that can easily determine instruction execution by forcibly replacing an instruction code with another specific instruction code.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides an in-circuit emulator equipped with a target microprocessor that performs one-instruction refetch, based on the status signal of the microprocessor. a status decoder that generates a signal indicating the instruction code fetch bus cycle, and an address match that compares the address on the address bus of the microprocessor with the given comparison address and outputs a match signal when they match. a detection circuit; and a signal indicating an instruction injection cycle and a period for monitoring whether an instruction fetch of the same address occurs after instruction injection based on the output of the status decoder and the output of the address coincidence detection circuit. a gate signal generation circuit that generates a signal indicating the signal shown in FIG. a comparison address generation circuit that generates an address to which an instruction is to be injected only while the instruction injection cycle is active; and an instruction swap signal that indicates an instruction swap period from the output of the address match detection circuit and the output of the gate signal generation circuit. means for generating a branch instruction code on the data bus during the instruction injection cycle; buffer means for inhibiting fetching of the original instruction code output on the data bus during the instruction injection cycle; an instruction injection means, a gate means for outputting a signal indicating that an instruction at an address whose execution is to be determined has been executed based on an output of the address coincidence detection circuit and a signal indicating a monitoring period from the gate signal generation circuit; It is characterized by having the following.

[Operation] In the present invention, a bus cycle in which an instruction code at a specified address is prefetched by the microprocessor is detected, and an instruction code that unconditionally branches to a known address is inserted into that bus cycle instead of the instruction code that should be fetched. After that, an address match detection circuit detects whether the branch destination address is output on the address bus during a certain number of instruction fetches, and if a branch occurs, the branch instruction is fetched again. The original instruction code is fetched from the address injected, and it is possible to detect whether the instruction code at the prefetched specified address has been processed by the instruction execution unit in the microprocessor by the output signal of the gate means.

[Example] Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a main part configuration diagram showing an embodiment of an instruction execution detection device according to the present invention. In FIG. be. 2 is a match detection circuit that detects address matching, 3 is a gate signal generation circuit, 4 is a comparison address generation circuit, 5 is a 3-state buffer, 6 is an instruction injection board, and 7 is a branch (J U
M P ) instruction memory, 8 is address counter, 9
is a status decoder, and 10.11 is a gate.

The match detection circuit 2 compares the address on the address bus (ADH3BUS) 12 of the microprocessor with the address given from the comparison address generation circuit 4, and outputs a match signal ADRHIT when the two match.

The gate signal generation circuit 3 receives the output of the status decoder 9, that is, the CHCLK signal indicating the instruction code fetch bus cycle, and the output ADR of the coincidence detection circuit 2.
Ding W indicating the instruction injection cycle based on HI'T'
MON I indicating the period of monitoring whether an instruction fetch of the same address occurs after signal and instruction injection at Y under T.
Generate TCYC signals respectively.

The comparison address generation circuit 4 generates a comparison address to be given to the match detection circuit 2. This comparison address is normally an address to which an execution determination is attempted, but especially during the period when the 5WAPCYC is active, the comparison address is an address to which an instruction is to be injected.

The three-state buffer 5 is connected to the data bus (DATA BUS) 13 of the microprocessor, and has a function of inhibiting the fetching of the original instruction code by the output 5WAP of the gate 10.

The address counter 8 receives the output of the gate signal generation circuit 3 and the output F of the status decoder 9.
E 'f' is received, and the address is updated in synchronization with the T address while the Y is active in the WA address.

The JUMP instruction memory 7 is pre-written with a relative JtJMP instruction code with a displacement such that the address given from the address counter 8 returns to the same address. 6, the output S of gate 10
It is output onto the data bus DATA BUS of the microprocessor at the timing of the W AP signal.

The gate 11 is connected to the output Ayr τT of the coincidence detection circuit 2 and the output MON of the gate signal generation circuit 3.
EXECU performs logical AND with ITC and indicates that the instruction at the address for which execution was to be determined was actually executed.
Outputs TED signal.

The operation in such a configuration will be explained next.

First, I will explain the principle of the moving ear of the present invention.
To simplify the explanation, it is assumed that the instruction queue in the microprocessor is 4 bytes and the JUMP instruction to be injected is 1 byte. Generally, when it is necessary to judge whether to execute an instruction, for example, address N in the flowchart of FIG.
This is a point like this. In other words, the instruction E at address N is fetched into the instruction queue by the microprocessor's prefetch processing before the execution of the immediately preceding conditional branch instruction, but depending on the execution result of the instruction, the instruction queue may be cleared without being executed. This is because there are cases where

Therefore, in the present invention, an instruction (relative jump instruction: JMP, N
) is forced to be fetched.

As the program processing progresses and the conditional branch instruction is transferred to the execution unit as shown in Figure 3 (B), if a branch occurs, the instruction queue is cleared and the branch address N+3 is cleared as shown in Figure 3 (D). Instruction H is newly taken into the instruction queue.

On the other hand, if no instruction branch occurs, the instruction queue is cleared and the branch destination address N
instruction E is newly imported.

Therefore, after the relative jump instruction injection, the address N is re-injected during the bus cycle period corresponding to the capacity of the instruction queue.
If a fetch cycle occurs, the instruction E at address N
can be determined to be an instruction that will definitely be executed. At this time, a loss time corresponding to the time required to execute the injected JMP and H instructions occurs, but if the processing time of the entire 10 grams is considered, it is negligible if the impulse is 1 or so.

This is basically the same even if the JUMP instruction to be injected is 2 bytes or more. However, if a branch due to a previously fetched branch instruction occurs during the instruction injection period, it is necessary to stop instruction injection. Therefore, a circuit that monitors the instruction injection address is required. “Now, the operation of FIG. 1 will be explained below with reference to the time chart of FIG. 4. In this embodiment, it is assumed that two bus cycles are required to inject a relative JUMP instruction. When the address is N, the comparison address generation circuit 4 outputs IN as the comparison address, and the match detection circuit 2 outputs the bus cycle in which the microprocessor 1 outputs the address N on the address bus for prefetching. ADR Ding Ding TT is shown in Figure 4 (D)
It becomes active as shown in . Gate signal generation circuit 3
generates from this signal a 5WAPCYC signal ((e) in the figure) for the bus cycle required for injecting the relative JUMP instruction, and supplies it to the gate 10.

In the instruction fetch bus cycle that occurs while this signal is active, the A
The SWw lower ℃ signal obtained by the logical product on the R3HI lower signal causes J on the DATA BUS13 as shown in the same figure.
Relative JUMP instructions indicated by MPO and JMPl are output.

When the injection of the relative JUMP command ends, the gate signal generation circuit 3 again generates the MO gate signal that defines the period for monitoring the appearance of address N on the ADDRES BUS.

Only when the ADH3HIT signal output from the address match detection circuit becomes active while the MON I gate signal is active, the EXECUTED signal, which indicates that the instruction at address N is confirmed to be executed in the microprocessor, becomes active. becomes.

Here, it is necessary to consider the case where the execution unit in the microprocessor executes a branch instruction during the 5WAPCYC active period. In this case, 5WAPCYC must be canceled immediately to stop the instruction injection. Therefore, during the 5WAPCYC period, the address given to the address-number output circuit 2 is changed to the address N + 1 of the JMPl instruction.
Assuming that, when a branch occurs and an instruction fetch at an address other than N+1 occurs, the gate signal generation circuit 3 detects that the ADR3HIT signal is negative and is up to t, and cancels SW A P CY C. . In FIG. 4, the situation at this time is shown by broken lines.

As described above, it can be determined from the microprocessor's bus signal that the prefetched instruction code at the specified address has been processed by the instruction execution unit within the microprocessor.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can also be modified as follows.

■In the case of a microprocessor in which injection of a relative JUMP instruction is completed in one bus cycle, the address counter and JUMP instruction memory shown in FIG. 1 are unnecessary, and the relative JtJMP instruction code can be directly given to the instruction injection board 6. , In addition, in the embodiment, the number of addresses for which execution determination is to be made is one point, but when execution determination is made at multiple points in the address space, 1 bit xnli is used.
Connect the RAM 51 of the configuration to the address bus, and set it to “1” (
Or when the address that was writing "0°°" is accessed by the microprocessor, the address -
There is a way to make several numbers.

In this case, the configuration is as shown in FIG.

5W indicating a match of instruction injection address in 5WAPCYC
AD indicating a match between the APHIT signal and the effective determination address
It is necessary to be able to separate the H3HI'T' signal.

■ In addition to relative JtJMP instructions to the same address, the instructions to be injected are absolute JtJMP instructions to a fixed address as shown in Figure 6.
A UMP command may also be used. At that time, a J'UMP instruction is executed to return to the address where the instruction was injected at the JUMP destination. Address matching is detected by monitoring the appearance of the JUMP destination address.

[Effects of the Invention] As described above, according to the present invention, even if a microprocessor cannot determine whether to execute an instruction at a specified address by simply monitoring the status signal from outside the microprocessor, the known By injecting an instruction to branch to the specified address, execution can be determined based on whether or not the microprocessor accesses the branch destination address. Therefore, when the in-circuit emulator executes the instruction at the specified address, there is a very small amount of invalidity. By simply adding processing time, it is possible to perform various types of debugging using program addresses as event conditions in almost real time.

For example, in high-level language debugging, each line N O,
Alternatively, if you trace using the address corresponding to the function module name as a sample condition, real-time line N
O, tracing, etc. becomes possible.

[Brief explanation of the drawing]

FIG. 1 is a main part configuration diagram showing an embodiment of an instruction execution detection device according to the present invention, FIG. 2 is a diagram showing an example of the flow of an execution program, and FIG. 3 is a diagram for explaining the operating principle of the present invention. , FIG. 4 is a time chart of the operation in the configuration of FIG. 1, FIG. 5 is a block diagram of main parts of another embodiment of the present invention, and FIG. 6 is for explaining another embodiment of the present invention. FIG. 1...Target microprocessor, 2...Address-several output circuit, 3...Gate signal generation circuit, 4
... Comparison address generation circuit, 5 ... 3-state buffer, 6 ... Instruction injection port, 7 ... JUMP instruction memory, 8 ... Address counter, 9 ... Status decoder, 10 .11...gate, 12...
-Address bus, 13...data bus.

Claims (1)

[Scope of Claims] An in-circuit emulator equipped with a target microprocessor that performs instruction prefetch, comprising: a status decoder that generates a signal indicating a bus cycle for instruction code fetch based on a status signal of the microprocessor; an address match detection circuit that compares an address on the address bus of the microprocessor with a given comparison address and outputs a match signal when they match; and an output of the status decoder and an output of the address match detection circuit. a gate signal generation circuit that generates a signal indicating an instruction injection cycle and a signal indicating a period for monitoring whether or not an instruction fetch of the same address occurs after instruction injection; and an address given to the address coincidence detection circuit. Normally, it generates an address at which an execution decision is to be made, but based on the output of the gate signal generation circuit, it generates an address at which an instruction is to be injected only while the instruction injection cycle is active. an address generation circuit; means for generating an instruction swap signal indicating an instruction swap period from an output of the address match detection circuit and an output of the gate signal generation circuit; buffer means for inhibiting the fetching of the original instruction code; instruction injection means for outputting the branch instruction code onto the data bus during the instruction injection cycle; an output of the address match detection circuit; and the gate signal generation circuit. and a gate means for outputting a signal indicating that an instruction at an address whose execution is to be determined has been executed, and an instruction code at a specified address is prefetched by a microprocessor. Detects a cycle, forces an instruction code that causes an unconditional branch to a known address to be fetched during that bus cycle instead of the instruction code that should have been fetched, and then updates the branch destination address for a certain number of instruction fetches. An address match detection circuit detects whether or not the instruction code is output on the address bus, and when a branch occurs, the original instruction code is fetched again from the address where the branch instruction is injected, and the output signal of the gate means is An instruction execution detection device characterized in that it is capable of detecting whether an instruction code at a specified address prefetched by an instruction code has been processed by an instruction execution unit in a microprocessor.