JPH0378254A - P-type mos transistor - Google Patents
P-type mos transistorInfo
- Publication number
- JPH0378254A JPH0378254A JP1215271A JP21527189A JPH0378254A JP H0378254 A JPH0378254 A JP H0378254A JP 1215271 A JP1215271 A JP 1215271A JP 21527189 A JP21527189 A JP 21527189A JP H0378254 A JPH0378254 A JP H0378254A
- Authority
- JP
- Japan
- Prior art keywords
- type
- drain
- diode
- substrate
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 230000004888 barrier function Effects 0.000 claims abstract description 7
- 238000009792 diffusion process Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 230000003071 parasitic effect Effects 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000001939 inductive effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1087—Substrate region of field-effect devices of field-effect transistors with insulated gate characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はＭＯ５型半導体集積回路に用いるＰ型ＭＯＳ
トランジスタの構造に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a P-type MOS used in an MO5-type semiconductor integrated circuit.
This relates to the structure of transistors.
第３図は従来のＰ型ＭＯ３）ランジスタの断面図を示す
。図において、（１）はＮ型シリコン基板、（２）・（
３）はＰ＋拡散層、（４）はＮ＋拡散層、（５）はゲー
ト電極、（６）はソース電極、（７）はドレイン電極、
（８）はＳｉＯ！膜である。FIG. 3 shows a cross-sectional view of a conventional P-type MO3) transistor. In the figure, (1) is an N-type silicon substrate, (2)
3) is a P+ diffusion layer, (4) is an N+ diffusion layer, (5) is a gate electrode, (6) is a source electrode, (7) is a drain electrode,
(8) is SiO! It is a membrane.
第４図は第３図のＰ型ＭＯＳトランジスタの等何回路を
示したもので、図中、（５）はゲート電極、（６）はソ
ース電極、（７）はドレイン電極、（９）は寄生ダイオ
ードである。Figure 4 shows the circuit of the P-type MOS transistor in Figure 3, where (5) is the gate electrode, (6) is the source electrode, (7) is the drain electrode, and (9) is the It is a parasitic diode.
次に動作について説明する。Next, the operation will be explained.
ＭＯ３型集積回路において、出力に接続されたＬ負荷（
モータ等）をスイッチングする時、又は負荷から回シ込
むノイズにより、出力のＰ型ＭＯＳトランジスタのドレ
イン（７）の電位が、ソース（６）の電位（通常は電源
電圧ＶＤＤ ）より一定期間だけ高くなる場合がある。In MO3 type integrated circuit, L load (
When switching a motor, etc.) or due to noise injected from the load, the potential of the drain (7) of the output P-type MOS transistor is higher than the potential of the source (6) (usually the power supply voltage VDD) for a certain period of time. It may happen.
寄生ダイオード（９）のインピーダンスが十分低ければ
、このようなノイズは寄生ダイオード（９）のｖＦ（約
０．６Ｖ）程度に抑えることができるが、実際には寄生
ダイオード（９）の直列抵抗により、完全には吸収でき
ずにＶｙ を上回るレベルでクランプされる。If the impedance of the parasitic diode (9) is sufficiently low, such noise can be suppressed to about vF (approximately 0.6 V) of the parasitic diode (9), but in reality, it is caused by the series resistance of the parasitic diode (9). , it cannot be completely absorbed and is clamped at a level above Vy.
従来のＰ型ＭＯ５ｌ−ランジスタは以上のように構成さ
れていたので、特に集積回路が０ＭＯ５構成の時には、
このようなノイズがトリガとなって、ラッチアップが発
生するという問題点があった。Since the conventional P-type MO5l-transistor was configured as described above, especially when the integrated circuit has a 0MO5 configuration,
There is a problem in that such noise becomes a trigger and latch-up occurs.
この発明は上記のような問題点を解決するためＫなされ
たもので、ＣＭＯ８型Ｏ８回路のラッチアップ耐量の向
上を図ることを目的とする。This invention was made to solve the above-mentioned problems, and its object is to improve the latch-up resistance of a CMO8 type O8 circuit.
この発明に係るＰ型ＭＯＳトランジスタは、ドレインを
構成するＰ＋拡散層とこれに接するＮ型シリコン基板に
共通コンタクトを設けた後、アルミ配線を形成すること
によシ、ドレイン−Ｎ型シリコン基板間にシッットキー
バリアダイオードを形成したものである。In the P-type MOS transistor according to the present invention, a common contact is provided between the P+ diffusion layer constituting the drain and the N-type silicon substrate in contact with the same, and then an aluminum wiring is formed between the drain and the N-type silicon substrate. A Schittky barrier diode is formed in this structure.
この発明におけるＰ型ＭＯ３）ランリスクは、ドレイン
電位がソース電位よ）高くなると、シッットキーパイア
ダイオードがオンし、これによシトレイン−ソース間の
電位差はシッットキーバリアダイオードのＶＦ程度（約
０．２〜０．３Ｖ）にクランプされる。The P-type MO3) run risk in this invention is that when the drain potential becomes higher than the source potential, the Schittkeeper diode turns on, and the potential difference between the Schittkie barrier diode and the source becomes approximately VF (approximately 0.2-0.3V).
以下、この発明の一実施例を図について説明する０
８１図はこの発明の一実施例に係るＰ型ＭＯＳトランジ
スタの断面図、第２図は第１図の等価回路図である。An embodiment of the present invention will be described below with reference to the drawings. FIG. 81 is a sectional view of a P-type MOS transistor according to an embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of FIG. 1.
歯巾、（１）はＮ型シリコン基板、（２）はドレインを
形成するＰ＋拡散層、（３１はソースを形成するＰ＋拡
散層、（４）はＮ型シリコン基板Ｆｉｌのオーミックコ
ンタクトを取るためのＮ＋拡散層、（５）はゲート電極
、（６）はソース電極、（７）はドレイン電極、（８）
はＳｉｎ！膜、（３）は寄生ダイオード、叫はショット
キバリアダイオード、（１すはドレイン拡散層（２）と
Ｎ型シリコン基板＋に＋の共通コンタクトホールである
。Tooth width, (1) is the N-type silicon substrate, (2) is the P+ diffusion layer that forms the drain, (31 is the P+ diffusion layer that forms the source, (4) is for making ohmic contact with the N-type silicon substrate Fil. N+ diffusion layer, (5) is the gate electrode, (6) is the source electrode, (7) is the drain electrode, (8)
Is Sin! 1 is a common contact hole between the drain diffusion layer (2) and the N-type silicon substrate.
次に動作について説明する。Next, the operation will be explained.
ＭＯ５型集積回路のＰ型ＭＯ３）ランリスクによりモー
タ等のし負荷を駆動すると、Ｌ負荷につながるドレイン
電極（７）にソース電極（６）（通常は電源電圧ＶＤＤ
Ｋ接続される）の電位以上のノイズが発生するが、シ
ぢットキーパリアダイオード１ｌｏｌがオンすることに
よシ、ショットキーパリアダイオード叫のＶＦ （約０
．２Ｖ程度）程度にまで吸収できる。このノイズレベル
はショットキバリアダイオード（圃のサイズを適切に設
定し、直列抵抗を下げることにより、ＣＭＯ５回路の寄
生サイリスクのトリガレベル以下に抑えることができる
。When a load such as a motor is driven by the P-type MO3) run risk of an MO5 type integrated circuit, the drain electrode (7) connected to the L load is connected to the source electrode (6) (usually the power supply voltage VDD).
However, by turning on the Schottky parrier diode 1lol, the VF of the Schottky parrier diode (approximately 0
．． It can absorb up to about 2V). This noise level can be suppressed to below the trigger level of the parasitic noise risk of the CMO5 circuit by appropriately setting the size of the Schottky barrier diode (field) and lowering the series resistance.
以上のようにこの発明によれば、Ｐ型ＭＯＳトランジス
タのＮ型シリコン基板とドレイン間にショットキバリア
ダイオードを構成したので、モータ等のし負荷の駆動を
目的とするＣＭＯ５型Ｏ５回路において、ラッチアップ
耐量の向上、動作安定化を図ることができる。As described above, according to the present invention, since a Schottky barrier diode is configured between the N-type silicon substrate and the drain of a P-type MOS transistor, latch-up can be avoided in a CMO5-type O5 circuit intended for driving a load such as a motor. It is possible to improve durability and stabilize operation.
第１図は、この発明の一実施例によるＰ型ＭＯＳトラン
ジスタの断面図、第２図は第１図の等価回路図、第３図
は従来のＰ型ＭＯ３）ランリスクの断面図、第４図は第
３図の等価回路図である。
（１）はＮ型シリコン基板、（２）はドレインを形成す
るＰ＋拡散層、（１１）は共通コンタクトホールを示す
。
なお、図中、同一符号は同一 又は相当部分を示す。FIG. 1 is a sectional view of a P-type MOS transistor according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of FIG. 1, FIG. 3 is a sectional view of a conventional P-type MO3) run risk, and FIG. The figure is an equivalent circuit diagram of FIG. 3. (1) shows an N-type silicon substrate, (2) shows a P+ diffusion layer forming a drain, and (11) shows a common contact hole. In addition, the same symbols in the figures indicate the same or equivalent parts.
Claims (2)
ドを設けたことを特徴とするＰ型ＭＯＳトランジスタ。(1) A P-type MOS transistor characterized in that a Schottky barrier diode is provided between the substrate and the drain.
めに、ドレインＰ＾＋拡散層とこれに接するＮ型シリコ
ン基板に共通コンタクトを設けたことを特徴とする請求
項１記載のＰ型ＭＯＳトランジスタ。(2) The P-type MOS transistor according to claim 1, wherein a common contact is provided between the drain P^+ diffusion layer and the N-type silicon substrate in contact with the drain P^+ diffusion layer to form the Schottky barrier diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215271A JPH0378254A (en) | 1989-08-21 | 1989-08-21 | P-type mos transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1215271A JPH0378254A (en) | 1989-08-21 | 1989-08-21 | P-type mos transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0378254A true JPH0378254A (en) | 1991-04-03 |
Family
ID=16669547
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1215271A Pending JPH0378254A (en) | 1989-08-21 | 1989-08-21 | P-type mos transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0378254A (en) |
-
1989
- 1989-08-21 JP JP1215271A patent/JPH0378254A/en active Pending
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