JPH0377670B2 - - Google Patents
Info
- Publication number
- JPH0377670B2 JPH0377670B2 JP57211568A JP21156882A JPH0377670B2 JP H0377670 B2 JPH0377670 B2 JP H0377670B2 JP 57211568 A JP57211568 A JP 57211568A JP 21156882 A JP21156882 A JP 21156882A JP H0377670 B2 JPH0377670 B2 JP H0377670B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- tft
- film
- gate insulating
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 56
- 239000004065 semiconductor Substances 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 8
- 239000010409 thin film Substances 0.000 claims description 6
- 150000001875 compounds Chemical class 0.000 claims description 5
- 229910004261 CaF 2 Inorganic materials 0.000 claims description 2
- 239000010407 anodic oxide Substances 0.000 claims description 2
- SBIBMFFZSBJNJF-UHFFFAOYSA-N selenium;zinc Chemical compound [Se]=[Zn] SBIBMFFZSBJNJF-UHFFFAOYSA-N 0.000 claims description 2
- 230000001681 protective effect Effects 0.000 description 13
- 230000000694 effects Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000002048 anodisation reaction Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- YBNMDCCMCLUHBL-UHFFFAOYSA-N (2,5-dioxopyrrolidin-1-yl) 4-pyren-1-ylbutanoate Chemical compound C=1C=C(C2=C34)C=CC3=CC=CC4=CC=C2C=1CCCC(=O)ON1C(=O)CCC1=O YBNMDCCMCLUHBL-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000007733 ion plating Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910001635 magnesium fluoride Inorganic materials 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000013081 microcrystal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
- WYXIGTJNYDDFFH-UHFFFAOYSA-Q triazanium;borate Chemical compound [NH4+].[NH4+].[NH4+].[O-]B([O-])[O-] WYXIGTJNYDDFFH-UHFFFAOYSA-Q 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〈技術分野〉
本発明は絶縁基板上に形成された薄膜トランジ
スタ（以下TFTと称す）に関し、特に絶縁ゲー
ト型電界効果トランジスタのゲート絶縁膜又は保
護絶縁膜に新規な技術を駆使することにより、ス
ローステートに於ける不安定性を軽減して長期間
安定な動作を行なうTFTに関するものである。[Detailed Description of the Invention] <Technical Field> The present invention relates to a thin film transistor (hereinafter referred to as TFT) formed on an insulating substrate, and in particular to a new technology for the gate insulating film or protective insulating film of an insulated gate field effect transistor. This relates to TFTs that can be used to reduce instability in slow states and operate stably for long periods of time.
〈従来技術〉
第１図に示すTFTの要部断面構成図を参照し
ながら従来のTFTの構造及びその製造方法につ
いて説明する。従来のTFTは絶縁基板１上にゲ
ート電極２とゲート絶縁膜３を重畳し、更に半導
体膜４を積層した上にソース電極５及びドレイン
電極６を形成し、保護膜７で被覆することにより
構成される。各電極層及びその他の薄膜層は周知
の薄膜形成技術即ち真空蒸着法，スパツタリング
法，イオンプレーテイング法，CVD法，プラズ
マCVD法等が利用される。絶縁基板１としては、
ガラス板，石英，セラミツク板，サフアイア基板
等が用いられ、ゲート電極２としては金属や
In2O3，SnO2等の透明導電材料、ゲート絶縁膜３
としては金属酸化物，窒化物等の絶縁材料、半導
体膜４としてはCdS，CdSe，PbS，PbSe，InSb
等の化合物あるいはTe，Si等が用いられる。ま
た、ソース電極５及びドレイン電極６は金属が一
般的に用いられるが、半導体膜４とオーミツクコ
ンタクトを成すものが望ましい。保護絶縁膜７は
Al2O3，SiO2，Si3N4等の絶縁材料で形成される。<Prior Art> The structure of a conventional TFT and its manufacturing method will be described with reference to the cross-sectional configuration diagram of main parts of a TFT shown in FIG. A conventional TFT is constructed by superimposing a gate electrode 2 and a gate insulating film 3 on an insulating substrate 1, further laminating a semiconductor film 4, forming a source electrode 5 and a drain electrode 6, and covering it with a protective film 7. be done. For each electrode layer and other thin film layers, well-known thin film forming techniques such as vacuum evaporation, sputtering, ion plating, CVD, plasma CVD, etc. are used. As the insulating substrate 1,
Glass plates, quartz, ceramic plates, sapphire substrates, etc. are used, and the gate electrode 2 is made of metal or
Transparent conductive materials such as In 2 O 3 and SnO 2 , gate insulating film 3
As for the insulating material such as metal oxide or nitride, as for the semiconductor film 4, CdS, CdSe, PbS, PbSe, InSb.
Compounds such as Te, Si, etc. are used. Although metal is generally used for the source electrode 5 and the drain electrode 6, it is desirable that they form ohmic contact with the semiconductor film 4. The protective insulating film 7 is
It is made of insulating materials such as Al 2 O 3 , SiO 2 , Si 3 N 4 , etc.
上記構造を有するTFTを動作させると、半導
体表面に蓄積されたキヤリアがゆつくりとスロー
ステートにトラツプされ、その結果ドレイン電流
がゆるやかに減少するといつた現象が生じる。こ
の現象は、TFTをマトリツクス液晶表示装置等
の表示駆動に利用した場合の信頼性を低下させる
という問題を発生させる。このようなスローステ
ートにキヤリアがトラツプされる現象について
は、その主たる機構はゲート絶縁膜中の局在準位
にキヤリアがトンネルすることにより補獲される
ことに起因するものであると説明されており、例
えば、H.Sewell，andJ.C.Anderson：Solid−
State Electronics，18，641（1975）に詳述され
ている。このような局在準位としては、アモルフ
アス物質の移動度ギヤツプ中の局在準位あるいは
微結晶の粒界が考えられ、実際に影響を与える部
分は室温近辺ではゲート絶縁膜３の半導体膜４と
の界面より約100Å〜数百Å程度の深さ迄の領域
である。 When a TFT having the above structure is operated, carriers accumulated on the semiconductor surface are slowly trapped in a slow state, resulting in a phenomenon in which the drain current gradually decreases. This phenomenon causes a problem of reduced reliability when the TFT is used for display driving of a matrix liquid crystal display device or the like. The main mechanism behind this phenomenon of carriers being trapped in a slow state is that they are captured by tunneling into localized levels in the gate insulating film. For example, H. Sewell, and J.C. Anderson: Solid−
State Electronics, 18 , 641 (1975). Such localized levels can be considered to be localized levels in the mobility gap of an amorphous material or grain boundaries of microcrystals, and the part that actually has an effect is the semiconductor film 4 of the gate insulating film 3 near room temperature. This region extends to a depth of approximately 100 Å to several hundreds of Å from the interface with the substrate.
〈発明の目的〉
本発明は上述の問題点に鑑み、TFTの構造に
新規な技術を駆使することによりTFTの動作特
性の信頼度を向上せしめたものであり、特にゲー
ト絶縁膜を複数層で構成することにより局在準位
をゲート絶縁膜の半導体膜との界面近傍で減少さ
せた信頼性の高いTFTを提供することを目的と
するものである。<Purpose of the Invention> In view of the above-mentioned problems, the present invention improves the reliability of the operating characteristics of TFTs by making full use of new technology for the structure of TFTs. The purpose of this invention is to provide a highly reliable TFT in which the localized level is reduced near the interface between the gate insulating film and the semiconductor film.
一般に、電気陰性度の差の大きい化合物はイオ
ン性が大きく、イオン結晶性の絶縁体となり易い
傾向がある。従つてこのような物質を用いてゲー
ト絶縁膜を形成すれば、容易に長距離秩序度の高
い局在準位の少ない絶縁膜を得ることができると
考えられる。しかしながら、ゲート絶縁膜を全て
上述の如きイオン性の強い物質で形成すれば、ピ
ンホールが発生し易く、また耐圧が充分に確保さ
れないといつた新たな問題が生じ、実用化が困難
となる。一方、スローステートにキヤリアが補獲
される現象はキヤリアのトンネル効果によるもの
であり、ゲート絶縁膜の半導体膜との界面より数
百Å程度を上述したイオン性の強い物質で形成す
れば、実質的にスローステートの影響は充分に防
ぐことができると考えられる。尚、ゲート絶縁膜
以外に半導体膜及びソース・ドレイン電極を被覆
する保護絶縁膜をイオン性の強い物質で形成して
もその効果を得ることは可能であつた。 Generally, compounds with a large difference in electronegativity have large ionic properties and tend to become ionic crystalline insulators. Therefore, it is considered that if a gate insulating film is formed using such a substance, an insulating film with a high degree of long-range order and few localized levels can be easily obtained. However, if the gate insulating film is entirely formed of a highly ionic material as described above, new problems arise such as pinholes are likely to occur and a sufficient withstand voltage cannot be ensured, making it difficult to put it into practical use. On the other hand, the phenomenon of carrier capture in the slow state is due to the tunnel effect of carriers, and if the area of the gate insulating film from the interface with the semiconductor film is made of the above-mentioned highly ionic material, it can be effectively suppressed. It is considered that the effects of slow states can be sufficiently prevented. Incidentally, it was possible to obtain the same effect even if the protective insulating film covering the semiconductor film and the source/drain electrodes was formed of a strongly ionic substance in addition to the gate insulating film.
本発明は以上の考察に基いて、ゲート絶縁膜あ
るいは保護絶縁膜を複数層で構成し、スローステ
ートの影響を防止することを企図するものであ
る。また、陽極酸化膜の如き極めて薄い膜であり
ながらピンホールが無く絶縁耐圧の高い膜をゲー
ト絶縁膜として利用すれば、より一層の顕著な効
果を期待することができる。 Based on the above considerations, the present invention aims to prevent the influence of slow states by configuring the gate insulating film or the protective insulating film with multiple layers. Moreover, if a film such as an anodic oxide film, which is extremely thin but has no pinholes and has a high dielectric strength, is used as the gate insulating film, even more remarkable effects can be expected.
〈実施例〉
第２図は本発明の一実施例を示すTFTの要部
断面構成図である。このTFTは以下の如き製造
工程により製作される。即ち、ガラス等の絶縁基
板１の上にゲート電極材料として約5000ÅのTa
を蒸着し、CF4を用いてドライエツチングを行な
い、パターン化する。次に、このTaを陽極酸化
し、約1300Åの厚さのTa2O5から成る第１の絶縁
層３１を形成する。陽極酸化は３％ホウ酸アンモ
ニウム水溶液を用い、化成電圧は80（Ｖ）に設定
する。陽極酸化により得られた第１の絶縁層３１
上にはイオン性の強い第２の絶縁層３２として約
300Åの厚さのMgF2を蒸着する。第１の絶縁層
３１と第２の絶縁層３２で２層構造のゲート絶縁
膜を構成し、この上に半導体膜４として約70Åの
Teを蒸着した後、パターン化する。半導体膜４
上にはソース電極５及びドレイン電極６となる金
属膜として約2000ÅのNiを蒸着した後、パター
ン化する。更にTETの保護絶縁膜７として約
3000Åの厚さのAl2O3，Si3N4，MgF2等を真空蒸
着法，スパツタリング法あるいはCVD法等で堆
積する。以上により第２図に示すTFTが作製さ
れる。<Embodiment> FIG. 2 is a cross-sectional configuration diagram of essential parts of a TFT showing an embodiment of the present invention. This TFT is manufactured by the following manufacturing process. That is, about 5000 Å of Ta is deposited on an insulating substrate 1 made of glass or the like as a gate electrode material.
is deposited and dry etched using CF 4 to form a pattern. Next, this Ta is anodized to form a first insulating layer 31 made of Ta 2 O 5 with a thickness of about 1300 Å. For anodization, a 3% ammonium borate aqueous solution is used, and the anodization voltage is set to 80 (V). First insulating layer 31 obtained by anodic oxidation
On top is a second insulating layer 32 with strong ionic properties.
Deposit MgF2 to a thickness of 300 Å. The first insulating layer 31 and the second insulating layer 32 form a two-layer gate insulating film, and on top of this is a semiconductor film 4 with a thickness of approximately 70 Å.
After Te is deposited, it is patterned. Semiconductor film 4
Ni is deposited to a thickness of about 2000 Å on top as a metal film that will become the source electrode 5 and drain electrode 6, and then patterned. Furthermore, as a protective insulating film 7 of TET, approximately
Al 2 O 3 , Si 3 N 4 , MgF 2 , etc. with a thickness of 3000 Å is deposited by vacuum evaporation, sputtering, CVD, or the like. Through the above steps, the TFT shown in FIG. 2 is manufactured.
第３図は60℃で直流電圧を印加した時のドレイ
ン電流の時間的変化を示すグラフであり、曲線l1
は第２図に示すTFT、曲線l2は厚さ300Åの
MgF2層がない単体のゲート絶縁膜で他は第２図
と同様に構成されたTFTの特性曲線を示す。約
20分経過後、第１図のTFT構造に相当する曲線
l2のTFTではドレイン電流が初期値の約38％に
まで低下したが、本実施例に相当する曲線l1の
TFTではドレイン電流が初期値の約63％までし
か低下せず、２層構造のゲート絶縁膜を有する
TFTの安定性は顕著であつた。また第４図Ａに
示す如くTFTを液晶表示装置と結線し、ソース
電極Ｓ、ゲート電極Ｇ、ドレイン電極Ｄにそれぞ
れ第４図Ｂに示すパルス電圧VS，VG，VDを生起
させ、容量CLCの液晶をシミユレーシヨン駆動し
たところ、第５図に示す如く初期のオン抵抗の増
加は第２図に示すTFTでは曲線l1で表わされる
ように10％以下であつた。一方、単体のゲート絶
縁膜を有し、他は同一条件で製作されたTFTで
は曲線l2で表わされるようにオン抵抗の増加は20
〜30％に迄達している。更に2000時間経過後の動
作に於いても、曲線l2のTFTではオン抵抗の増
加は40〜50％に達しているが、曲線l1のTFTで
は20％以下に抑制されている。 Figure 3 is a graph showing the temporal change in drain current when a DC voltage is applied at 60°C, and the curve l 1
is the TFT shown in Figure 2, and curve l 2 is the TFT with a thickness of 300 Å.
This shows the characteristic curve of a TFT constructed in the same manner as in Fig. 2 except for the single gate insulating film without the MgF double layer. about
After 20 minutes, the curve corresponding to the TFT structure in Figure 1
In the l 2 TFT, the drain current decreased to about 38% of the initial value, but the drain current of the l 1 TFT corresponding to this example
In TFT, the drain current decreases only to about 63% of the initial value, and it has a two-layer gate insulating film structure.
The stability of TFT was remarkable. Further, the TFT is connected to a liquid crystal display device as shown in FIG. 4A, and pulse voltages V S , V G , and V D shown in FIG. 4 B are generated in the source electrode S, gate electrode G , and drain electrode D , respectively. When a liquid crystal with a capacitance C LC was driven in simulation, as shown in FIG. 5, the initial increase in on-resistance was less than 10% as shown by curve l1 in the TFT shown in FIG. 2. On the other hand, in a TFT that has a single gate insulating film and is manufactured under the same conditions, the on- resistance increases by 20
It has reached ~30%. Further, in operation after 2000 hours, the increase in on-resistance reached 40 to 50% in the TFT of curve l2 , but was suppressed to 20% or less in the TFT of curve l1 .
第６図は本発明の他の実施例を示すTFTの要
部断面構成図である。本実施例は保護絶縁膜をイ
オン性の強い絶縁膜で多層化したものであり、第
２図に示す実施例のゲート絶縁膜ほど顕著ではな
いが、同様な効果を奏する。本実施例でソース電
極５、半導体膜４及びドレイン電極６上に堆積さ
れる保護絶縁膜は半導体層４側に接触する下部保
護絶縁膜７１を前記実施例と同様なイオン性の強
いMgF2等の絶縁膜で構成し、その上にAl2O3，
Si3N4等から成る上部保護絶縁膜７２を堆積した
２層構造より成つている。 FIG. 6 is a sectional view of the main part of a TFT showing another embodiment of the present invention. In this embodiment, the protective insulating film is multilayered with highly ionic insulating films, and although not as remarkable as the gate insulating film of the embodiment shown in FIG. 2, it produces the same effect. In this embodiment, the protective insulating film deposited on the source electrode 5, the semiconductor film 4, and the drain electrode 6 has a lower protective insulating film 71 in contact with the semiconductor layer 4 side made of highly ionic MgF 2 or the like similar to the previous embodiment. It consists of an insulating film of Al 2 O 3 ,
It has a two-layer structure in which an upper protective insulating film 72 made of Si 3 N 4 or the like is deposited.
上記実施例に於いてイオン性の強い絶縁膜とし
てはMgF2以外に電気陰性度の差の大きな化合物
として知られているLiF，ZnS，ZnSe，CaF2，
CeF3等が適用可能である。 In the above embodiment, in addition to MgF 2 , the highly ionic insulating film includes LiF, ZnS, ZnSe, CaF 2 , which are known as compounds with large differences in electronegativity.
CeF 3 etc. are applicable.
〈発明の効果〉
以上詳説した如く本発明によればTFTの安定
性及び信頼性が飛躍的に改善され、従つて、これ
を液晶表示装置の駆動手段として用いた場合、非
常に動作特性の良い表示装置が得られる。<Effects of the Invention> As explained in detail above, according to the present invention, the stability and reliability of the TFT are dramatically improved, and therefore, when this is used as a driving means for a liquid crystal display device, it has very good operating characteristics. A display device is obtained.
スローステートの影響は半導体のバンドギヤツ
プが狭いもので現われ易く、このためバンドギヤ
ツプの狭い半導体材料を用いたTFTに対して本
発明は特に有効となる。 The effects of slow states are more likely to appear in semiconductors with narrow band gaps, and therefore the present invention is particularly effective for TFTs using semiconductor materials with narrow band gaps.
第１図は従来のTFTの構造を示す断面図であ
る。第２図は本発明の一実施例を示すTFTの断
面図である。第３図はゲート電極に直流電圧を印
加した際のTFTの特性変化を説明する説明図で
ある。第４図ＡはTFTの信頼性試験を説明する
等価回路図、第４図Ｂはその印加波形図である。
第５図は第４図の信頼性試験を長時間動作させた
場合のTFTの特性変化を示す説明図である。第
６図は本発明の他の実施例を示すTFTの断面図
である。
１……絶縁基板、２……ゲート電極、３……ゲ
ート絶縁膜、３１……第１のゲート絶縁膜、３２
……第２のゲート絶縁膜、４……半導体膜、５…
…ソース電極、６……ドレイン電極、７……保護
絶縁膜、７１……第１の保護絶縁膜、７２……第
２の保護絶縁膜。
FIG. 1 is a sectional view showing the structure of a conventional TFT. FIG. 2 is a sectional view of a TFT showing an embodiment of the present invention. FIG. 3 is an explanatory diagram illustrating changes in TFT characteristics when a DC voltage is applied to the gate electrode. FIG. 4A is an equivalent circuit diagram explaining a TFT reliability test, and FIG. 4B is an applied waveform diagram.
FIG. 5 is an explanatory diagram showing changes in TFT characteristics when the reliability test shown in FIG. 4 is operated for a long time. FIG. 6 is a sectional view of a TFT showing another embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Insulating substrate, 2... Gate electrode, 3... Gate insulating film, 31... First gate insulating film, 32
...Second gate insulating film, 4...Semiconductor film, 5...
...source electrode, 6...drain electrode, 7...protective insulating film, 71...first protective insulating film, 72...second protective insulating film.
Claims (1)
半導体層が堆積され、該半導体層に接触するソー
ス電極とドレイン電極が具備されて成る薄膜トラ
ンジスタにおいて、前記ゲート絶縁膜は前記ゲー
ト電極表面の陽極酸化膜と前記半導体層に接触す
る電気陰性度の差の大きい化合物の膜から成る２
層構造を有することを特徴とする薄膜トランジス
タ。 ２ 電気陰性度の差の大きい化合物の膜が、
LiF，ZnS，ZnSe，CaF2，MgF2またはCeF3から
成る特許請求の範囲第１項記載の薄膜トランジス
タ。[Claims] 1. A thin film transistor in which a semiconductor layer is deposited on a gate electrode on a substrate via a gate insulating film, and a source electrode and a drain electrode are provided in contact with the semiconductor layer, wherein the gate insulating film is 2 consisting of an anodic oxide film on the surface of the gate electrode and a film of a compound with a large difference in electronegativity in contact with the semiconductor layer;
A thin film transistor characterized by having a layered structure. 2 A film of a compound with a large difference in electronegativity is
A thin film transistor according to claim 1, comprising LiF, ZnS, ZnSe, CaF 2 , MgF 2 or CeF 3 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57211568A JPS59100572A (en) | 1982-11-30 | 1982-11-30 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57211568A JPS59100572A (en) | 1982-11-30 | 1982-11-30 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59100572A JPS59100572A (en) | 1984-06-09 |
| JPH0377670B2 true JPH0377670B2 (en) | 1991-12-11 |
Family
ID=16607934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57211568A Granted JPS59100572A (en) | 1982-11-30 | 1982-11-30 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59100572A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63126277A (en) * | 1986-07-16 | 1988-05-30 | Seikosha Co Ltd | Field effect thin film transistor |
| JPH047876A (en) * | 1990-04-25 | 1992-01-13 | Nec Corp | Thin film transistor |
-
1982
- 1982-11-30 JP JP57211568A patent/JPS59100572A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59100572A (en) | 1984-06-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2757207B2 (en) | Liquid crystal display | |
| JPS626672B2 (en) | ||
| JPS58147069A (en) | Thin film transistor | |
| JPH0582069B2 (en) | ||
| JPH0348671B2 (en) | ||
| JPH0377670B2 (en) | ||
| JPS6146068B2 (en) | ||
| JPH03217059A (en) | Thin film transistor | |
| JPS6361671B2 (en) | ||
| JPH0620136B2 (en) | Thin film transistor element and manufacturing method thereof | |
| JPH0774360A (en) | Preparation of vertical thin film transistor | |
| JP3175225B2 (en) | Method for manufacturing thin film transistor | |
| JPS61145582A (en) | Display unit | |
| JP3021888B2 (en) | Optical waveguide functional element and method of manufacturing the same | |
| JPH0546990B2 (en) | ||
| JPH0234821A (en) | Thin film transistor | |
| JPS63140580A (en) | Thin film transistor | |
| JPS5874079A (en) | Thin film transistor | |
| JPH0691256B2 (en) | Thin film transistor | |
| JPH0462183B2 (en) | ||
| JP2818013B2 (en) | Thin film transistor device and method of manufacturing the device | |
| JPH061835B2 (en) | Thin film transistor | |
| JP2798964B2 (en) | Liquid crystal display | |
| JP2594384B2 (en) | Metal oxide thin film, method of manufacturing the same, and electronic device using the metal oxide thin film | |
| JP3086607B2 (en) | Liquid crystal display |