JPH0375531U - - Google Patents
Info
- Publication number
- JPH0375531U JPH0375531U JP13777189U JP13777189U JPH0375531U JP H0375531 U JPH0375531 U JP H0375531U JP 13777189 U JP13777189 U JP 13777189U JP 13777189 U JP13777189 U JP 13777189U JP H0375531 U JPH0375531 U JP H0375531U
- Authority
- JP
- Japan
- Prior art keywords
- conductive material
- electrode pads
- utility
- electrode pad
- scope
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案に関する電極パツドの断面図。
第２図は従来の電極パツドの断面図。第３図は導
電物質の滴下図。第４図はＩＣチツプの電極パツ
ド表面図である。
１……測定探針、２……保護膜、３……電極パ
ツド、４……導電物質、５……導電物質圧送ノズ
ル、６……例として選択した電極パツド。
FIG. 1 is a sectional view of an electrode pad related to the present invention.
FIG. 2 is a cross-sectional view of a conventional electrode pad. FIG. 3 is a diagram showing the dripping of a conductive substance. FIG. 4 is a surface view of the electrode pads of the IC chip. 1... Measuring probe, 2... Protective film, 3... Electrode pad, 4... Conductive material, 5... Conductive material pressure feeding nozzle, 6... Electrode pad selected as an example.
Claims (1)
覆した構造を特徴とする半導体装置。 A semiconductor device characterized by a structure in which semiconductor electrode pads are selectively coated with a conductive material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13777189U JPH0375531U (en) | 1989-11-27 | 1989-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13777189U JPH0375531U (en) | 1989-11-27 | 1989-11-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0375531U true JPH0375531U (en) | 1991-07-29 |
Family
ID=31684914
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13777189U Pending JPH0375531U (en) | 1989-11-27 | 1989-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0375531U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022031629A (en) * | 2020-07-31 | 2022-02-22 | シトロニックス テクノロジー コーポレーション | Test pad structure of chip |
-
1989
- 1989-11-27 JP JP13777189U patent/JPH0375531U/ja active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2022031629A (en) * | 2020-07-31 | 2022-02-22 | シトロニックス テクノロジー コーポレーション | Test pad structure of chip |
| US11694983B2 (en) | 2020-07-31 | 2023-07-04 | Sitronix Technology Corporation | Test pad structure of chip |
| TWI812987B (en) * | 2020-07-31 | 2023-08-21 | 矽創電子股份有限公司 | Test pad structure of chip |