JPH0373690A - Image descrambling device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a circuit by providing the image descrambling device with a residual calculator consisting of an adder, a comparator, an inverter, and constant value generating circuits corresponding to residual calculation method and calculating a memory address from a spread address. CONSTITUTION:A spread address indicates the output of an adder 2 and a memory address output indicates the output of the residual calculator which is outputted to the upper sides of selectors 7, 8. The constant output circuits 13, 14 output the number of horizontal dots in each scramble system corresponding to the residual calculation method and both of the circuits 13, 14 can be switched in accordance with the corresponding scramble systems. A selector 18 selects the output side of an adder 16 when the spread address exceeds the number of horizontal dots or selects the spread address side when the spread address does not exceed the number in accordance with the output of the comparator 17. Consequently, residual calculation using the number of horizontal dots as a divisor is applied to the spread address and the calculated result is outputted as the memory address.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video descrambling receiving device including an intra-scanning line signal switching method, such as a video descrambling receiving device of this type used in a viewer-side receiving terminal in a pay television system using a broadcasting satellite. The present invention relates to a video descrambling receiving device.

Conventional technology When CATV was first developed in Japan, it was mainly used to prevent difficult viewing of television, but by utilizing the broadband transmission characteristics of coaxial cables and optical cables, it has become possible to provide various services other than television. becomes possible,
In recent years, independent broadcasting using sky channels, disaster prevention systems,
It is developing into a versatile new media of communication, providing conversational services such as automatic medical examination systems, home banking, etc. that connect subscribers with central processing units in management centers. On the other hand, satellite broadcasting is being carried out in Japan as part of the advancement and informatization of communication media accompanying the development of advanced informationization in society, and the aim is to further diversify the public's information needs and enhance broadcasting services. The Paid System for Television Broadcasting by Broadcasting Satellite (dated November 28, 1986), which was planned in 1999, provided guidelines regarding technical conditions. The successful implementation of this fee-based system naturally requires the development of effective and appropriate solutions to the technical problems that may arise, while also adhering to uniform standards.

For example, regarding receiving terminals in these paid systems, a video descrambling receiving device with excellent performance and low cost is one of the promising development targets. In other words, whether it is CATv or a pay television system using broadcasting satellites, the video signal is electrically scrambled and transmitted from the broadcasting provider, and the receiving terminal on the viewer side uses a decoder to convert the scrambled video signal to the original. The service is provided by restoring the video signal. A typical method for scrambling video signals transmitted as analog signals is the intra-scanning line signal switching method, which is particularly important for the confidentiality and security of images (difficulty in unauthorized viewing by non-subscribers). Its major feature is that it is advantageous in terms of:

For this reason, this intra-scan line signal switching system is said to be particularly suitable for pay television systems using broadcasting satellites, as well as the scan line transition system, which has the characteristic of being less affected by the characteristics of the transmission path. In the intra-scanning line signal switching method, deterioration in restoration quality may occur depending on the characteristics of the transmission path and receiving terminal, and this has a particularly large effect when a scrambled video signal is distributed through a cable as an amplitude modulated signal. Therefore, it is being considered to improve the intra-scan line scanning method itself, or to combine it with the scan line transfer method to take advantage of the strengths of both and compensate for their weaknesses. Another disadvantage of the intra-scan line switching method compared to the scan line transition method is that
The memory capacity of the decoder of the receiving terminal is large, and the memory control circuit inevitably becomes complicated. This increases the financial burden on viewers who wish to receive pay-TV services, so this is a problem that cannot be overlooked in order to promote the use of pay-TV services and achieve commercial success. Therefore, as will become clear from what will be described later, the present invention is first directed to overcoming the essential problems of such an intra-scanning line switching method.

A video descrambling receiving apparatus using the intra-scanning line signal switching method is configured as shown in FIG. 2, for example.

The figure shows a 2-line memory system, where 1 is a data flip-flop, which is a pseudo-random number (this is a (indicating the switching point of the video signal during line-by-line scrambling) is latched by a horizontal synchronizing pulse and delayed by one horizontal scanning line.

An adder 2 adds the output of the horizontal scanning line dot counter 4 and the switching point output from the data flip-flop 1. 3 is a remainder calculator which calculates the remainder of the output of adder 2, modulo the number of dots in one horizontal scanning line. The dot counter 4 is reset by a horizontal synchronizing pulse. 5 is a data flip-flop,
Divide the horizontal synchronization pulse by 2 and divide the R/
Generates signals that control W and addresses. 7 and 8 are selectors; the selector 7 is controlled by the output of the data flip-flop 5 inverted by an inverter 6, and the selector 8 is controlled by the output of the data flip-flop 5 directly connected thereto. 9 and 10 are
In the line memory, R/W is performed by the output of the data flip-flop 5, and selection of the counter output 4 and the remainder calculator output 3 is performed alternately for each line by the selector 7.8. That is, when video data is written to (or read from) the line memory, the address of the line memory 7 (or 8) is selected on the counter 4 side (or the remainder calculator 3 side) and read out (or , written)
In this case, the remainder calculator 3 side (or the counter 4 side) is selected.

As a result, descrambled video data is read out line by line alternately from the line memory 9.10. 11
The selector always selects the line memory to be read.

Assuming that the number of horizontal dots in the video signal is 100, the operation of the video descrambling receiving apparatus shown in FIG. 2 will be explained below using the waveform diagram for explaining the operation in FIG.

Note that the symbols (a) to (e) attached to each waveform in FIG. 3 correspond to the same symbols in FIG. 2, respectively. The counter 4 output is reset by the horizontal synchronization pulse and counts up from 0 to 99. What is spread address here?
This is the output of the adder 2, and changes from 30 to 129 when the pseudo-random number latch output is 30 as shown in FIG.

In addition, the memory address is the output of the remainder calculator 3, which is the remainder of the spread address when the number of horizontal dots is 100.Up to 99, it changes in the same way as the spread address, but when it exceeds 100, the spread This is the value obtained by subtracting 100 from the address.

Therefore, in the configuration shown in Figure 2, when writing to memory, the counter output is selected, and when reading,
By selecting the memory address, the video signal is descrambled.

In the video descrambling receiving apparatus having such a configuration, the remainder calculator 3 has conventionally had the configuration shown in FIG. 4. Here, 12 can be adapted to systems with different numbers of dots per horizontal scanning line by changing the method of remainder calculation by changing the mode in the ROM.

Problems to be Solved by the Invention According to such a configuration, for example, if a calculation indicated by 9 bits of input and 8 bits of output is to be performed using a ROM, it is possible to use a ROM with 9 bits of address input and 8 bits of data output. That is, this is possible by using a 29-byte ROM. Furthermore, assuming that the mode can be switched in two ways, that is, the calculation is selected by adding one bit of the address, two types of calculations will be possible, and the capacity of the ROM 12 will be 29 + 1 = 210 bytes. . Furthermore, if it is possible to support 2-bit modes, the capacity of the ROM 12 will be 211 bytes. In addition, this remainder calculation within the video descrambling receiving device is performed by the number 1 within the sampling clock period of the video signal.
0M) lr rate. As a result, high speed, high capacity and expensive ROMs are required.

Based on these problems, the present invention solves the drawbacks and provides a remainder calculator having a simple configuration that is optimal for use in a video descrambling receiving device, and also provides a remainder calculator having such a remainder calculator. It is an object of the present invention to provide a video descrambling receiving device that is novel and highly useful.

Means for Solving the Problems The video descrambling receiving device of the present invention comprises an adder, a comparator, an inverter, and a constant value generation circuit corresponding to the modulus of remainder calculation, and includes a circuit for calculating a memory address from a spread address. It is characterized by being equipped with a remainder calculator, and with this configuration, it is possible to use multiple systems with different numbers of horizontal dots without increasing the circuit scale by simply changing the constant value corresponding to the modulus of remainder calculation. It becomes possible to respond to

EXAMPLES Hereinafter, examples will be described with reference to the drawings in order to better understand the basic principle, specific structure, and operation of the present invention.

FIG. 1 is a block diagram showing the configuration of main parts according to an embodiment of the present invention. This diagram corresponds to the remainder calculator 3 in FIG. Here, the spread address indicates the output of the adder 2 in FIG. 2, and the memory address output indicates the output of the remainder calculator 3, which is output to the upper side of the selector 7.8 in FIG. 13 and 14 are constant output circuits that output the number of horizontal dots of each scrambling system corresponding to the modulus of remainder calculation, and can be switched according to the corresponding scrambling system. 15 is an inverter that inverts all bit outputs coming from the constant output circuits 13 and 14.

An adder 16 calculates (spread address - number of horizontal dots) by adding the output from the inverter 15 and the output of the spread address with the carry input at logic level H. A comparator 17 compares the spread address and the number of horizontal dots. 18 is
In the selector, when the spread address exceeds the number of horizontal dots according to the output of the comparator 17, the adder 16
Select the output side of , and conversely, when it does not exceed, select the spread address side. As a result, a remainder calculation is performed on the spread address modulo the number of horizontal dots, and the result is output as a memory address.

In this way, scrambling systems with different modulus calculation methods when calculating a memory address from a spread address can be handled simply by switching the constant output circuit corresponding to the modulus using a selector. There is no need to increase the circuit scale compared to the above. Further, within the video descrambling receiving device, this remainder calculation needs to be performed at high speed (within one horizontal dot clock), but according to the configuration of the present invention, a high-speed, high-capacity RO
Since there is no need to use M, it is possible to provide an inexpensive video descrambling receiving device.

Effects of the Invention As described above, according to the present invention, there is no need to use a high-speed, high-capacity ROM, so that an inexpensive video descrambling receiving device can be provided.

In addition, by simply switching the constant output circuit with a selector, the method of remainder calculation when calculating the memory address from the spread address can be changed.
It can be said that this method has excellent practical effects without increasing the circuit scale compared to the case where the circuit is used.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a remainder calculator which is a main part of a video descrambling receiving device in an embodiment of the present invention, and FIG.
The figure is a block diagram showing the overall configuration of a video descrambling receiving device, FIG. 3 is a drawing for explaining the operation of the device shown in FIG. 2, and FIG. 4 is a diagram for calculating a memory address from a spread address using a conventional ROM. FIG. 2 is a configuration diagram of a remainder calculator for 13.14...Constant generation circuit 15...Inverter 16...Adder 17...Comparator 18.20...Selector

Claims (2)

[Claims] (1) One or a plurality of switchable constant generation circuits;
an adder that inverts the output of the constant generator, adds a carry to it, and adds it to the spread address; a comparator that compares the spread address with the output of the constant generator; and an output of the comparator. a selector for switching between the spread address and the output of the adder, and a remainder calculator for calculating a memory address by a remainder calculation performed with respect to the spread address modulo the output of the constant generation circuit. A video descrambling receiving device characterized by: (2) In the remainder calculator, the remainder calculation method when calculating a memory address from a spread address is determined only by switching the outputs of the plurality of constant generation circuits and selecting one of them. A video descrambling receiving device according to claim 1, characterized in that: