JP3087444B2 - Scramble circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for secret video communication of television signals. In particular, the present invention relates to a confidential video communication device that randomly converts the order of horizontal periods of an NTSC color video signal and transmits the signal.

[0002]

2. Description of the Related Art Conventionally, when a scramble circuit is used in a transmission device of a concealed video communication device, generally, the scrambling circuit performs concealment by randomly changing the order of horizontal periods of video signals. In this concealment system, video signals are generally converted into PCM data and performed using a storage element. In this case, the video signal containing the color information is converted into PCM data with a clock signal locked to a burst signal in order to faithfully reproduce the color information.

[0003]

However, in such a conventional scramble circuit, in the case of an NTSC video signal, the polarity of the burst signal is inverted every horizontal period, and as shown in FIG. There is a problem that the continuity of the burst signal cannot be maintained in the video signal output on the side. FIG. 4 is a diagram showing an output signal waveform of a conventional scramble circuit. Also, since the continuity is not maintained, it is necessary to switch the burst signal at the output of the transmission side, and the result of descrambling at the reception side is also lost at the output of the reception side because the continuity of the burst signal is lost. There was a problem that the burst signal had to be replaced again.

The present invention solves the above problems,
It is an object of the present invention to provide a scramble circuit that does not need to switch burst signals on the receiving side.

[0005]

According to the present invention, there is provided a clock generator for generating a clock signal based on an input video signal, an address generator for generating a horizontal address, a vertical address and an odd / even address based on the clock signal. A first conversion circuit for converting the input video signal into a digital signal based on a clock signal, a polarity inverter for inverting the odd / even address, an address converter for randomly converting the vertical address, the horizontal address, converted vertical address converted video signal and outputs the first conversion circuit is based on the vertical address and the odd-even address write rare inputs, based on an output of the horizontal address and the polarity inverter analog and frame memory video signal written to have is <br/> read, the output of the frame memory And a second conversion circuit for converting the horizontal address into a video period address and a blanking address. An address switch for selecting the vertical address during a blanking period and selecting the output of the address converter during a video period and outputting the selected output as the converted vertical address.

According to the present invention, a scramble circuit according to claim 1 can be included in a transmitting apparatus.

Further, according to the present invention, the scrambling circuit according to claim 1 can be included in a receiving apparatus as a descrambling circuit.

[0008]

In the scrambling circuit of the transmitting device and the scrambling circuit of the receiving device, the address generator divides the horizontal address into a video period address and a blanking address and outputs them. The address switch selects the vertical address based on the blanking address during the blanking period, selects the output of the address converter during the video period and outputs the converted vertical address to the frame memory, and converts the vertical address during the blanking period. Is not performed.

As described above, there is no need to replace the burst signal on the receiving side.

[0010]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a scramble circuit according to an embodiment of the present invention.

In FIG. 1, a scramble circuit includes a clock generator 8 for generating a clock signal 9 based on an input video signal 1 and a horizontal address 1 based on the clock signal 9.
5, an address generator 10 for generating a vertical address 16 and an odd / even address 17, an analog / digital conversion circuit 2 as a first conversion circuit for converting the input video signal 1 to a PCM data 3 as a digital signal based on the clock signal 9, Polarity inverter 11 for inverting odd / even address 17
An address converter 12 for randomly converting the vertical address 16; a converted vertical address for writing and inputting the output PCM data 3 of the analog-to-digital conversion circuit 2 based on the horizontal address 15, the vertical address 16 and the odd address 17; Address 15 and polarity inverter 11
And a digital / analog conversion circuit 6 as a second conversion circuit for converting output video information 5 of the frame memory 4 into an output video signal as an analog signal.

Here, the feature of the present invention is that the address generator 10 converts the horizontal address into the video period address 18.
A video period address generating circuit 21 and a blanking address generating circuit 22 are provided as means for dividing and outputting the divided data into a blanking address 13. An address switch 14 for selecting the output of the converter 12 and outputting it as the converted vertical address is provided.

The operation of the scramble circuit having such a configuration will be described. FIG. 2 is a diagram showing an output signal waveform of the scramble circuit of the present invention. In FIG. 2, a clock generator 8 generates a clock signal 9 locked to a burst signal based on an input video signal 1. The address generator 10 generates a horizontal address 15, a vertical address 16, an odd / even address 17, and a blanking address 13 based on the clock signal 9. Analog-to-digital converter 2
Converts the input video signal 1 into PCM data 3 based on the clock signal 9 and writes it into the frame memory 4 based on the continuous horizontal address 15, vertical address 16 and odd / even address 17. Here, the order of the video information in the frame memory 4 is the same as that of the input video signal 1. The information stored in the frame memory 4 stored as described above is inverted by the odd / even address 17 of the odd / even address 17, the horizontal address 15 is left as it is, only the vertical address 16 is converted by the address converter 12 and used as a memory read address. And reads the scrambled video information 5 from the frame memory 4.

However, based on the blanking address 13 obtained by dividing the horizontal address 15, an address bypassing the address converter 12 is used only in the horizontal blanking period. Output as is.

The address converter 12 includes a numerical value table for randomly converting numerical values of an input address. The output numerical value condition of this numerical value is such that all the input numerical values are output and there is no same numerical value within one cycle.

The digital-to-analog converter 6 converts the video information 5 thus read from the frame memory 4 into an analog signal and outputs it as an output video signal 7.

In the scramble signal obtained as described above, the order of the images is changed as shown in FIG.
Since the order of the input video signal 1 remains in the horizontal blanking period, the continuity of the burst signal is maintained, so that the receiving side can obtain a stable clock signal without any trouble.

FIG. 3 is a block diagram of a secret video communication apparatus to which the scramble circuit of the present invention is applied. In FIG. 3, the above-described scramble circuit is used as the scramble circuit 31 in the transmission device 30, and the reception device 40
The above-described scramble circuit is used as a descramble circuit 41, and an address converter is inserted into a vertical address.
The same numerical table is used in the address converter.

[0019]

As described above, the present invention has an excellent effect of eliminating the necessity of changing the burst signal on the receiving side.

[Brief description of the drawings]

FIG. 1 is a block diagram of a scramble circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing an output signal waveform of the scramble circuit of the present invention.

FIG. 3 is a block diagram of a secret video communication device to which the scramble circuit of the present invention is applied.

FIG. 4 is a diagram showing an output signal waveform of a conventional scramble circuit.

[Explanation of symbols]

 Reference Signs List 1 input video signal 2 analog / digital converter 3 PCM data 4 frame memory 5 video information 6 digital / analog converter 7 output video signal 8 clock generator 9 clock signal 10 address generator 11 polarity inverter 12 address converter 13 blanking address 14 Address Switch 15 Horizontal Address 16 Vertical Address 17 Odd / Even Address 18 Video Period Address 21 Video Period Address Generator 22 Blanking Address Generator 23 Vertical Address Generator 30 Transmitter 31 Scrambler 40 Receiver 41 Descrambler

Claims (3)

(57) [Claims] 1. A clock generator for generating a clock signal based on an input video signal, an address generator for generating a horizontal address, a vertical address, and an odd / even address based on the clock signal, and the input video signal based on the clock signal A first conversion circuit for converting the vertical address into a digital signal; a polarity inverter for inverting the odd / even address; an address converter for randomly converting the vertical address; Dzu have been converted to output the first conversion circuit
A frame memory video signal writing rare transformed vertical address inputs, said horizontal address and said polar have groups <br/> Dzu to the output of inverter and the written video signal is read out with, the frame A scramble circuit having a second conversion circuit for converting an output of the memory into an analog signal, wherein the address generator includes means for dividing and outputting the horizontal address into a video period address and a blanking address, An address switch for selecting the vertical address during a blanking period based on a blanking address and selecting an output of the address converter during a video period and outputting the selected output as the converted vertical address. circuit. 2. A confidential video communication device comprising the scramble circuit according to claim 1 in a transmission device. 3. A concealed video communication device including the scramble circuit according to claim 1 as a descramble circuit in a receiving device.