JPH05260466A - High definition pay television decoder - Google Patents

Abstract

PURPOSE:To provide an inexpensive decoder by adopting an in-scanning line signal switching system (2-cut system) so as to decode a scrambled pay broadcast with a one-line memory configuration with respect to the high definition pay television decoder by the MUSE system. CONSTITUTION:The decoder is provided with a line memory 208 storing data equivalent to one line and with controller controlled by a clock synchronization regeneration section 148, and the controller has a function that a line memory address is sequentially designated in order of write for a horizontal synchronization period and a guard area period when no signal changeover is implemented, a line memory address for each signal period is cyclicly designated respectively within each period based on an address corresponding to each signal changeover position in each signal period written respectively before one horizontal scanning line as to a color difference signal period and a luminance signal period having a signal switching point by the in-scanning line signal switching scramble and read/write is repeated by the read modified write method for each dot sample.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a high-definition television (MUSE system = Multiple Sub) in which only subscribers who have contracted can unscramble and watch a program.
-Nyquist Sampling Encodin
g (Multiple Sampling Coding) method The present invention relates to a pay broadcast decoder.

[0002]

2. Description of the Related Art In recent years, pay broadcasting has been put into practical use with the expansion of broadcasting satellites. In the paid broadcasting, unlike the conventional broadcasting format by the advertisement fee and the reception fee, it is necessary to deliver the program only to the contracted recipient, and thus the program is normally electrically disturbed (scrambled) and broadcast. Currently, as a video scrambling system for high-definition television, a scanning line signal switching system (hereinafter referred to as a line rotation system), a scanning line transition system, and a combination of these systems are considered.

The following are conventional high definition televisions (MUSs).
E system) A pay-broadcast decoder, in particular, a line rotation system scramble signal decoder unit will be described with reference to the drawings.

As shown in FIG. 3, a conventional high-definition television pay broadcast decoder has a functional configuration centered on a line rotation scramble decoding process. Only an outline is shown. First, from the analog MUSE signal input terminal 153, the normally scrambled MUS
E signal is input, and analog MUS is input by A / D converter 149.
The E signal is converted into a digital MUSE signal. clock·
In the sync reproducing unit 148, a digital signal processing reference clock of 16.2 MHz (hereinafter referred to as VCK) based on the analog MUSE signal and the digital MUSE signal, a video horizontal synchronizing signal (hereinafter referred to as Hp) required in each part of the pay broadcast decoder, etc. To play. The scramble information extraction / decoding section 147 extracts and decodes the scramble-related information multiplexed in the MUSE signal and outputs it to the scramble decoding circuit. The horizontal dot counter 101 displays VCK (16.2).
(MHz) as a reference clock and outputs horizontal sampling numbers 0 to 479 of the MUSE signal. In the data flip-flop 102a, the scramble information extracting / decoding unit 14
The PN (a) signal indicating the signal switching position at the time of scrambling for switching the signal in the scanning line of the color difference signal output from
Output at the timing of Hp. The data flip-flop 102b outputs the PN (b) signal indicating the signal switching position at the time of scrambling for switching the signal within the scanning line of the luminance signal output from the scramble information extraction / decoding unit 147 at the timing of Hp. The timing signal generator 104 outputs a timing signal S1 indicating a horizontal synchronizing signal position and the like, a color difference signal, and a timing signal S2 indicating a luminance signal position based on the output from the horizontal dot counter 101. The adder 105a adds and outputs the output from the horizontal dot counter 101 and the output from the data flip-flop 102a, and the adder 105b outputs the output from the horizontal dot counter 101 and the data flip-flop 102.
The output from b is added and output. In the computing unit 106a,
If the input is d and the output is q, q = 11 + (d-11)
Outputs Mod 94. However, A Mod B
Represents the remainder calculation modulo B with respect to A. In the computing unit 106b, if the input is d and the output is q,
q = 106 + (d−106) Mod 374 is output. The signal changeover switch 112 selectively outputs the outputs of the two computing units according to the color difference signal and the timing signal S2 indicating the position of the luminance signal. Data flip-flop 103
Outputs an alternating line signal that toggles for each Hp by connecting the inverting output terminal to the input terminal and using Hp as a clock input. The logical inversion device 113 inverts and outputs the line alternating signal, the logical sum device 114a outputs the logical sum of the output of the logical inversion device 113 and the output S1 of the timing signal generation unit 104, and the logical sum device 114b outputs the data flip-flop. The logical sum of the output of the block 103 and the output S1 of the timing signal generator 104 is output. Line memories 145a and 145b (hereinafter referred to as RAM (a) and RAM, respectively)
(Referred to as (b)) is written / alternately by the line alternating signal output from the data flip-flop 103 so that when one is read, the other is written.
Read out. The signal changeover switch 110a receives the output signal from the logical sum device 114a, and outputs the RAM (a) 145.
The address changeover line a is changed over, and the signal changeover switch 11
0b is RA by the output signal from the logical sum device 114b.
The address line of M (b) 145b is switched. The logic inverting device 122 inverts and outputs the line alternating signal output from the data flip-flop 103, and the signal changeover switch 108a switches the data line of the RAM (a) 145a by the line alternating signal from the data flip-flop 103. The signal changeover switch 108b causes the RAM (b) 145b to output the output from the logic inverting device 122.
Switch the data line of. The scanning line transfer method scramble decoding unit 143 decodes and outputs the video signal scrambled by the scanning line transfer method, but the description of the internal function is omitted here.

A conventional high-definition television (MUSE system) pay-broadcast decoder composed of the above-mentioned components,
The relationship between the respective constituent elements and the decoding operation of the line rotation scramble will be described below with reference to FIGS. 3 and 4.

First, the line rotation scramble (2-cut system) will be described with reference to FIG. For one scan line as shown in FIG. 4, FIG.
The dot configuration of the scanning line in the original signal (non-scrambled) state of the signal valid screen is shown in FIG. 4B, but the dot configuration after the line rotation scramble (2-cut system) is shown in FIG. Each dot configuration such as synchronization, color difference signal, and luminance signal is shown. During the horizontal synchronization signal (hereinafter referred to as HD) period 200, the dot 11
-10 positions, color difference signal (hereinafter referred to as C signal) period 201
Are the dots 11 to 104, and the guard area 202 is
The dot 105 position and the luminance signal (hereinafter referred to as Y signal) period 203 are the dots 106 to 479 positions, and the scanning line is configured as described above. At the cut point 204 of the line rotation of the C signal, the C signal is scrambled by replacing the front and rear. At the cut point 205 of the line rotation of the Y signal,
The front and rear of the signal are interchanged and scrambled. This cut point is set by a pseudo random number for each scanning line, and the program is scrambled.

Next, the decoding operation of the line rotation scramble when the MUSE signal thus line-rotation scrambled is input to the pay broadcast decoder shown in FIG. 3 will be described with reference to FIGS. 3 and 5. FIG. 5 is a signal waveform diagram showing the signal timing of each part of FIG. First, the MUSE signal input to the MUSE signal input terminal 153 as shown in FIG.
9 digitally converted and scrambled information extraction / decoding unit 14
7, clock / synchronous reproducing unit 148, signal changeover switch 1
08a, 108b, etc. The clock / synchronization reproducing unit 148 reproduces VCK and Hp at the timing shown in FIG.

The output of the data flip-flop 103 is shown in FIG.
The line alternating signal shown in (1) is connected to two memories, and when it is High (hereinafter simply referred to as "H"), the RAM is
(A) 145a is a read state, RAM (b) 145b
Is in a write state, and when it is Low (hereinafter simply referred to as L), the reading / writing of the two RAMs is controlled so as to be the opposite. Now, the decoding operation will be described by taking the case where the RAM (a) 145a is in the reading state and the RAM (b) 145b is in the writing state as an example. At this time, the changeover switches 108a, 108b, 110a, 110
The state of b is shown by the solid line. At this time, RAM (b) 1
The output of the horizontal dot counter 101 is selected as the address of 45b, and the addresses 0 to 0 in the RAM (b) 145b are selected.
In 479, input data is sequentially written. On the other hand, RA
As for the address of M (a) 145a, as shown in FIG. 5, during the HD period when the output of the horizontal dot counter 101 is 0 to 10, the output of the horizontal dot counter 101 is selected and the data is read out in the written order.

Next, the horizontal dot counter 101 output is 1
In the C signal period of 1 to 104, first, C at the time of scrambling
An address is set at the cut point position in the signal, the address of the C signal period is cycled through in order, and the data is read. In the example of FIG. 5, since the cut point signal PN (a) is 3, the C signal reading start address is 11 + 3,
12 + 3, 13 + 3, ..., 104, 11, 12, 1
An address of 3, 14 and C signal period is cycled once. Next,
When the output of the horizontal dot counter 101 is 105, the output of the horizontal dot counter 101 is always selected,
Read the data. Further, during the Y signal period in which the horizontal dot counter 101 outputs 106 to 479, first, an address is set at the cut point position in the Y signal at the time of scrambling, and the addresses of the Y signal period are sequentially cycled to read the data. In the example of FIG. 5, the cut point signal PN (b)
Is 2, the Y signal read start address is 106 + 2.
And sequentially 107 + 2, 108 + 2, ..., 479, 1
The addresses of 06, 107, 108 and the Y signal period are cycled once.

Further, in the next scanning line period, conversely, RA
M (a) 145a is the writing side, RAM (b) 145b
Becomes the reading side, and the line rotation scramble is similarly decoded.

By repeating the above operation alternately in the two RAMs, the line rotation scrambled video signal is decoded and output. Further, when the scanning line transition method scramble is applied, the scanning line transition method scramble is decoded by the scanning line transition method decoding unit 143 in the subsequent stage.

[0012]

However, in the above-mentioned conventional structure, as is clear from FIG. 3, since two line memories are required at the minimum, reduction of parts cost is hindered, and high-definition television pay broadcasting. There is a problem that the decoder cannot be constructed at low cost.

The present invention solves the above-mentioned conventional problems, and uses one line memory to decode a line rotation scramble (two-cut system) signal as in a conventional high-definition television pay broadcast decoder. An object is to provide a high-definition television pay broadcast decoder.

[0014]

In order to achieve the above object, a high-definition television pay broadcast decoder according to the present invention comprises two fixed horizontal scanning lines of a first horizontal line stored in a line memory. A memory address indicating a signal switching point in the first area of the video signal scrambled by the 2-cut scanning line signal switching method having two signal switching positions for the area. From the line memory, the line memory is read out so as to make one round in the first area, and the first horizontal line
The video signal of the area is read to write the scrambled video signal of the first area of the second horizontal line continuous to the first horizontal line to the memory address which becomes an empty area, and The line memory is read from the memory address indicating the signal switching point in the second area of the video signal so as to make one round in the second area, and the video signal of the second area of the first horizontal line is read. The scrambled video signal of the second area of the second horizontal line continuous with the first horizontal line is written to the memory address which becomes an empty area by reading.

[0015]

According to the present invention, in the above-described structure, a line rotation scramble (2-cut system) decoding circuit structure, which has conventionally required two line memories, has a line memory corresponding to one line and a signal switching circuit. For the horizontal synchronization period and the guard area period which are not performed, the line memory addresses are sequentially specified in the order of writing, and for the chrominance signal period and the luminance signal period having the signal switching points by the signal switching scrambling in the scanning line, each one horizontal From the address corresponding to each signal switching position in each signal period written before the scanning line, the line memory address in each signal period is circulated in each period, and the read-modify-write method is used for each dot sample. By repeating reading and writing, 1-line memory structure And thus to.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, the high-definition television pay broadcast decoder according to the present embodiment shows a functional configuration centering on a line rotation decoding process. Regarding other scanning line transition scrambling decoding processing units, etc. Indicates only an outline. Analog MUSE to input terminal 153
A signal is normally input in a scrambled state, and the A / D converter 149 converts the analog MUSE signal into a digital MUSE signal. In the clock / synchronization reproducing unit 148, a digital signal processing reference clock of 16.2 MHz (hereinafter referred to as VCK) based on the analog MUSE signal and the digital MUSE signal.
(Hereinafter referred to as "Hp") and a video horizontal synchronizing signal (hereinafter referred to as "Hp") necessary for each part of the pay broadcast decoder. The scramble information extraction / decoding section 147 extracts and decodes the scramble-related information multiplexed in the MUSE signal and outputs it to the scramble decoding circuit. The horizontal dot counter 101 uses VCK (16.2 MHz) as a reference clock, and horizontal sampling numbers 0 to 479 of the MUSE signal.
Is output. Data flip-flops 102a, 102
In b, the PN (a) and PN (b) signals output from the scramble information extraction / decoding unit 147 are output at the timing of Hp. The adders 201a and 201b cumulatively add PN (a) and PN (b) for each Hp, and the remainder calculators 203a and 203b respectively supply a color difference signal (hereinafter referred to as C signal) period and a luminance signal (hereinafter referred to as Y signal). Called)
The remainder is calculated using the dot sample numbers 94 and 374 in the period as a modulus. Data flip-flops 202a and 202b
Then, the remainder calculators 203a, 203
The output of b is output as a latch. Timing signal generator 10
4, the timing signal S1 and C signal indicating the horizontal synchronizing signal position, etc. based on the output of the horizontal dot counter 101,
A timing signal S2 indicating the Y signal position is output.

In the adders 205a and 205b, the remainder calculators 203a and 203b and the horizontal dot counter 1 are respectively provided.
01 output is added, and in the arithmetic unit 106a, the input is d,
If the output is q, q = 11 + (d-11) Mod
94 is output. In the computing unit 106b, if the input is d and the output is q, q = 106 + (d−106) Mod37
4 is output. The signal changeover switch 207 selectively outputs the outputs of the two arithmetic units according to the timing signal S2 indicating the C signal and Y signal positions. Signal changeover switch 211
Then, according to the timing signal S1 indicating the position of the horizontal synchronizing signal, the output of the counter 101 and the signal changeover switch 21
1 output is selectively output. The line memory 208 descrambles by writing the scrambled video signal, changing the order, and reading the scrambled video signal. The 3-state data flip-flop 209 latches and outputs the video data to the line memory 208 at the timing of VCK. The data flip-flop 210 latches and outputs the data read from the line memory 208. The logic inverter 212 inverts and outputs VCK. As in the conventional example, the scanning line transfer method scramble decoding unit 143 decodes and outputs the video signal scrambled by the scanning line transfer method.
Here, description of internal functions is omitted.

Regarding the high-definition television pay broadcast decoder composed of the above-described components, the relationship and operation of the components will be described below with reference to FIGS. 1 and 2.

As shown in FIG. 2, description will be made with reference to the signal waveform diagram of the signal timing of each part in FIG. First, MUSE
The MUSE signal input to the signal input terminal 153 is A / D
The data is digitally converted by the converter 149 and input to the scramble information extraction / decoding unit 147, the clock / synchronization reproducing unit 148, the 3-state data flip-flop 209, and the like. In the clock / synchronization reproducing unit 148, as in the conventional example, VCK, Hp
Are reproduced at the timing shown in FIG. Counter 10
As shown in FIG. 2, 1 is reset by Hp and counts and outputs horizontal dots. Now, as shown in Figure 2, PN
(A) is 30, 80, 50, ..., PN (b) is 130,
180, 150, ... First, P
The description will be given from the N (a) side. Data flip-flop 10
The 2a output outputs PN (a) for each Hp. Further, if the previous state of the remainder calculator 203a is 70 as shown in FIG. 2, the output of the remainder calculator 203a outputs (70 + 30) Mod 94 => 6 when Hp is input.
However, A Mod B indicates a remainder calculation modulo B with respect to A.

Further, this signal is added / calculated by the adder 205a and the calculator 106a as follows.
As shown in FIG. 2, when the output of the computing unit 106a is j and the output of the counter 101 is i in the C signal period, j = 11 +
(6 + i-11) Mod94.

Next, regarding the PN (b) side, PN
Processing similar to that of (a) is performed, and j = 106 + (300 + i−106) Mod 3 when the output of the computing unit 106b is j and the output of the counter 101 is i in the Y signal period.
74.

Further, at this time, the address input of the line memory 208 is performed by the signal changeover switches 207 and 211, the counter 101, the arithmetic unit 106a, and the arithmetic unit 106.
2, the counter 101 is output in the HD period and the guard area, the calculator 106a is output in the C signal period, and the calculator 106b is output in the Y signal period as shown in FIG.

On the other hand, the read / write (hereinafter referred to as R / W) terminal of the line memory 208 selects R in the first half of each address period of 16.2 MHz rate and W in the latter half. Further, at this time, the 3-state data flip-flop 209 is configured to operate when the line memory 208 is in the R state.
A high impedance state is set (in FIG. 2, the state of the data terminal of the line memory 208 is written to the memory,
The read data are indicated by d and D, respectively, and each number is indicated by the number in the writing order). As a result, the line memory 208 repeats the read-modify-write operation, and the read address is relative to the write address one horizontal scanning line before, and is 94 in the C signal period.
Modulo PN (a) and in the Y signal period, the line rotation scramble of each signal period is decoded by reading from a position PN (b) distant from 374.

As described above, according to this embodiment, one line memory and the line memory are sequentially arranged in the order of writing video signals in the horizontal synchronization period and the guard area period in which no signal switching is performed. An address corresponding to each signal switching position in each signal period written one horizontal scanning line before is specified for a color difference signal period and a luminance signal period having a signal switching point by scanning line signal switching scramble. From the above, the line memory address of each signal period is cyclically designated within each period, and the control means for repeatedly controlling the reading and writing by the read-modify-write method for each dot sample provides a two-line memory with a one-line memory configuration. Same as a conventional high-definition television pay broadcast decoder with , It is possible to decode the multiplex sampling coded signal scrambled by two cut-scanning line in the signal switching method having the signal switching two positions in each scan line.

[0026]

As is apparent from the above embodiments, according to the present invention, the simple structure of the one-line memory structure enables
It is possible to realize the same function as that of a conventional high-definition television pay broadcast decoder having a line memory, and to realize an inexpensive high-quality high-definition television pay broadcast decoder.

[Brief description of drawings]

FIG. 1 is a block diagram of a high-definition television pay broadcast decoder according to an embodiment of the present invention.

FIG. 2 is a timing signal waveform diagram for explaining the operation of the present invention.

FIG. 3 is a block diagram of a conventional high-definition television pay broadcast decoder.

FIG. 4 is a high-definition television scanning line configuration diagram showing scrambling within a scanning line signal switching system (2-cut system).

FIG. 5 is a timing signal waveform diagram for explaining the operation of a conventional high-definition television pay broadcast decoder.

[Explanation of symbols]

101 Timing Generator 208 Line Memory 102a, 102b, 202a, 202b Data Flip-Flop 203a, 203b Residue Calculator 201a, 201b, 205a, 205b Adder 106a, 106b Arithmetic Unit 207, 211 Signal Switching Device

Claims (1)

[Claims] 1. A high-definition television (multiple sampling coded signal system) scrambled by a 2-cut system scan line signal switching system having two signal switching positions for two fixed areas in one horizontal scanning line. )
A line memory capable of writing / reading the video signal by one horizontal line component and a control means for controlling writing / reading of the line memory are provided, and the control means is provided in two regions for each horizontal line of the video signal. And the signal signal of the first horizontal line stored in the line memory, and the signal switching point in the first area of the video signal of the first horizontal line. From the address indicating the first area, the line memory is read so as to make one round in the first area, and the video signal of the first area of the first horizontal line is read, so that the first address is set to an empty area. Write the scrambled video signal of the first area of the second horizontal line continuous to the horizontal line of, and switch the video signal of the first horizontal line to the signal switching point in the second area. From the address indicated, along with reading the said line memory to cycle through the second region,
By reading out the video signal of the second area of the first horizontal line, the scrambled video signal of the second area of the second horizontal line continuous to the first horizontal line is provided at an address which becomes an empty area. A high-definition television pay broadcast decoder adapted to output read-modify-write address information to the line memory for writing.