KR970011544B1 - Image scrambling system - Google Patents

Abstract

A video signal scrambling device using conversion method includes an A/D converter for converting an input composite video signal into a digital signal, line memories 2 and 3 for storing the output signal of the A/D converter 1, a synchronous signal separator 5 for separating the horizontal sync signal from the input composite signal, a clock generator 6 for generating a sampling clock from the horizontal sync signal, a D/A converter 4 for receiving the clock signal and converting the digital signals outputted from the A/D converter 1 and line memories 2 and 3 into analog signals, a data slicer 7 for detecting the initial data in the vertical blanking interval period of the composite video signal, a RAM 8 for storing the output signal of the data slicer 7, a microprocessor 9 for controlling the line memories using the data stored in the RAM, an inverter 11 for inverting the output signal of the A/D converter and transmitting it to the line memories, a line memory 12 for receiving the address outputted from the microprocessor and generating the MSB of data corresponding to the address, a latch 13 for triggering the MSB outputted from the line memory 12 by one horizontal interval, and an address counter 15 for counting the address set at every horizontal interval and transmitting it to a video interval detector 16.

Description

Video signal scrambling device using switching method

1 is a block diagram of a video signal scrambling apparatus using the switching method of the present invention.

2 is a luminance state diagram of an image signal for determining whether to switch data on the next line.

(A)-(E) of FIG. 3 is an exemplary diagram for determining whether to switch the next line at P point.

4 is a block diagram of a conventional video signal scrambling apparatus.

5A is a waveform diagram of a scrambled composite video signal.

(B) is the original composite video signal waveform diagram descrambled.

* Explanation of symbols for main parts of the drawings

1: A / D converter 2,3,12: Line memory

4: D / A converter 5: Synchronous separator

6: Clock Generator 7: Data Slicer

8: RAM9: microprocessor

10,14: buffer 11: inverter

13: latch 15: address counter

16: Image segment detector.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for scrambling an image signal using an intersion method. In particular, the present invention relates to an image signal by determining whether a video signal corresponding to a luminance level of an image signal of a scan line is black / white switched. The present invention relates to a video signal scrambling apparatus using a switching method suitable for scrambling / descrambling.

Prior to describing a conventional scrambling apparatus, a scrambling method for preventing illegal viewing of a pay TV receiver is described as follows.

First, the scrambling method is largely divided into an analog method and a digital method. Among them, there are various methods. Among these, the line rotation method, which is the most widely used digital scrambling method, is described as follows.

That is, the line cyclic scheme descrambles the scrambled signal once more, thus descrambling is performed to restore the original signal. Thus, scrambling or descrambling has the same principle.

Therefore, the descrambling performed at the receiving side will now be described with reference to FIG.

First, its configuration includes an A / D converter 31 for converting and outputting an input composite video signal into a digital signal, two line memories 32 and 33 for storing a signal output from the A / D converter 31; A synchronous signal separator 34 for separating a horizontal synchronous signal from the input synthesized signal, a clock generator 35 for generating a sampling clock from the horizontal synchronous signal separated from the synchronous signal separator 34, and the clock generation A D / A converter 36 which receives the clock signal output from the unit 35 and converts the digital signal output from the line memories 32 and 33 of the A / D converter 31 into an analog signal, and a composite video signal. A data slicer 38 for detecting initial data of a random number generator 37 in a vertical blanking interval (VBI), and an output signal of the data slicer 38 Random number generator 37 using RAM 39 and data stored in RAM 39 The microprocessor 40 to control, the random number generator 37 operating by receiving initial data from the microprocessor 40, and the output values of the random number generator 37 give addresses to the line memories 32 and 33. It is made by connecting to the address generator 41 which provides. The operation relationship is as follows.

First, when the scrambled composite signal as shown in (a) of FIG. 5 passes through the descrambling circuit as shown in FIG. 4, it is restored to the normal original composite video signal as shown in (b) of FIG. The composite video signal is scrambled as shown in FIG. 5A by the address in the line memories 32 and 33 for the point P of 5 degrees (b).

In addition, since the position of the point P is randomly generated by the random number generator 37 for each horizontal line, the scrambled image is similar to the noise screen and cannot be recognized at all.

The random number generator 37 transmits initial data for each field during the vertical retrace period in each field. The signal is received by the data slicer 38 and stored in the RAM 39. Then, the microprocessor 40 Is supplied to the random number generator 37, the P-point value generated at the transmitting side can be accurately known at the receiving side.

The reason is that the random number generator 37 of the scrambler on the transmitting side and the descrambler on the receiving side are configured in the same manner, so that the P point value generated for each horizontal scan line becomes the same as long as the initial data provided for each field is the same.

When the P point value generated in this way is supplied to the address generator 41, the address generator 41 reads the line memory (B) so that the image signal stored as shown in FIG. 5 can be read as shown in FIG. 32, 33) to supply address values.

In addition, the use of two line memories (32, 33) is to operate the read / write oppositely by one horizontal line alternately, where the input / output terminals of the A / D and D / A converters (31, 36) are 8 It is assumed that the bit is assumed and 1024 samplings are performed on one horizontal line (10 address lines).

However, such a configuration is accompanied by an increase in the price by the random number generator 37, and also descrambles the signal using a method of dividing the video signal section by P points, so that deterioration of image quality occurs at the portion where the scrambled signal is divided. Even if the original signal is restored to the original signal, there is a problem that the image quality is lower than the video signal before scrambling.

The present invention does not include an address generator and a random number generator in the conventional scrambling circuit to solve the above disadvantages, and includes a line memory, a latch, an address counter, an image segment detector, and a plurality of logic elements for each field. At the point corresponding to the data to be transmitted, each horizontal scan line obtains the information of the 'low' or 'high' signal according to the luminance to determine whether or not to perform data conversion on the horizontal scan line. An object of the present invention is to provide an image signal scrambling apparatus, which will be described below in detail with reference to the accompanying drawings.

, EN) 제어하는 버퍼(14)와, 상기 동기분리기(5)에서 분리출력된 매수평구간마다 설정된 어드레스를 계수하여 라인메모리(12)와 영상구간 검출기(16)에 전달하는 어드레스 계수기(15)와, 상기 어드레스 계수기(15)에서 계수출력된 어드레스를 합성영상신호의 각 구간에 시간비례로 나누어 영상이 실리는 구간이 검출되게 버퍼(14)를 인에이블시키는 영상구간 검출기(16)로 구성된 것이다.As shown in FIG. 1, the apparatus of the present invention includes an A / D converter 1 for converting and outputting an input composite video signal into a digital signal, and a line memory 2 for storing signals output from the A / D converter 1; 3, a synchronous signal separator 5 for separating a horizontal synchronous signal from the input synthesized signal, a clock generator 6 for generating a sampling clock from the horizontal synchronous signal separated from the synchronous signal separator 5, And a D / A converter 4 which receives the clock signal output from the clock generator 6 and converts the digital signal output from the A / D converter 1 and the line memories 2 and 3 into an analog signal. A data slicer (7) for detecting initial data in a VBI (Vertical Blanking Inteval) section of a composite video signal, a RAM (8) for storing an output signal of the data slicer (7), and a RAM A microprocessor (9) for controlling the line memory (12) using the data stored in (8); A buffer 10 for supplying or blocking the output signal of the A / D converter 1 to the line memories 2 and 3, and the output signal of the A / D converter 1 by inverting the line memory 2, 3, a line memory 12 for receiving the address output from the microprocessor 9 and generating the most significant bit (MSB) of data corresponding to the address, and the line memory ( A latch 13 for triggering the best bit output from 12) for one horizontal section, a signal output from the trigger from the latch 13, and an image section detected by the image section detector 16; Enable the inverter 11

(EN) buffer 14 and an address counter 15 for counting an address set for each horizontal section separated from the sync separator 5 and transferring it to the line memory 12 and the image section detector 16. And an image section detector 16 for enabling the buffer 14 to detect a section in which an image is loaded by dividing the address counted by the address counter 15 in each section of the composite video signal in proportion to time. .

Referring to the effects of the present invention configured as described above with reference to (a)-(e) of FIGS. 2 and 3 as follows.

First, since the existing circuit such as the A / D converter 1 operates the same as described above, the description of its operation is omitted in order to avoid redundant description.

The largest size of the present invention is to circulate arbitrary points during the image section as in the conventional case, thereby scrambled, without changing the data during the image section of one horizontal scan line, or the line memory (2, 3). The data conversion method of scrambling was selected while selecting whether to store the data in the memory.

That is, selecting whether to enable the buffer 10 or enable the inverter 11, and the method of selecting the buffer 10 is an intermediate level in which the luminance of any point in the horizontal scan line immediately before the corresponding horizontal scan line is at an intermediate level. If it is above (i.e., MSB = 1), the inverter 11 is selected and if it is below the middle level (i.e., MSB = 0), the buffer 10 is selected.

However, the section for selecting the buffer 10 and the inverter 11 is performed only in the video signal section, not in the horizontal scan section. This is to scramble the video signal so that the sync and color synchronization signals are left as they are.

It is the video section detector 16 which controls this, and the video section can set the section in which an image is loaded by dividing the addresses 0-1023 output from the address counter 15 to each section of a composite video signal in proportion to time. .

In this manner, when the buffer 14 is enabled by setting the output of the image section detector 16 to 'high' only in the image section, the buffer 14 selects the buffer 10 and the inverter 11 only during the image section. Done.

In this case, since the buffer 14 is disabled in the section other than the image section, the output of the buffer 14 becomes 'low' and always selects the buffer 10.

In addition, the input of the buffer 14 is obtained when the most significant bit (MSB) of a specific address of the line memory 12 passes through the latch 13, where only a specific address is generated randomly in each transmission field for each field and is vertical. This is an address output from the microprocessor 9 via the data slicer 7 and the RAM 8 at the receiving end to send the data carried in the retrace section (that is, the VBI section).

As shown in FIG. 2, the luminance signal of the video data corresponding to this address is at the P2 point (MSB = 1) if it is at or above the intermediate level, and at P1 (MSB = 0) if it is at or below the intermediate level.

That is, in the present invention, since the middle of the image section is not cut as in the conventional art, the line memories 2 and 3 increase in series from 0 to 1023 for both read / write addresses, so that the address counter 15 has no need for the scan line dedicated FIFO ( First In First Out) memory can be used.

In this way, the part which has been switched data on the transmitting side can not reproduce the normal screen by switching again on the receiving side, and the part which is normally sent on the transmitting side can be processed normally on the receiving side, so that the whole screen can be correctly mounted.

On the other hand, (a)-(e) of FIG. 3 is an example of determining whether to switch the next line at point P by transmitting sinusoids of various levels, and (a) of FIG. 3 is the most significant bit (MSB) of data at point P. ) Is changed to the next line, and (b) in Figure 3 is the scan line transmitted to the negative sine wave, so it is converted and restored to the sine wave, and the most significant bit (MSB) of P point is 'low' so The third line (C) of Fig. 3 is the high bit (MSB) of P point is 'high', so the next line is switched on the transmitting side and the next line is switched as it is transmitted. Since the most significant bit of MSB is 'low', the next line is processed as it is, but if it is converted, it is restored to a normal sine wave, and (e) of FIG. 3 shows that the next line is normal because the most significant bit (MSB) of P point is 'low'. As it is transmitted in sinusoidal wave, You can handle it as it is.

As described above, at the point where the data transmitted for each field corresponds, obtain 'low' or 'high' signal information according to the luminance signal for each horizontal scan line, and then switch data or not for the next horizontal scan line. Therefore, it is not necessary to separately configure an expensive random number generator and an address generator, so that the scrambling apparatus can be configured at a low price.

Claims (1)

An A / D converter 1 for converting and outputting the input composite video signal into a digital signal, a line memory 2 and 3 for storing the signal output from the A / D converter 1, and the input composite signal A synchronous signal separator 5 for separating the horizontal synchronous signal, a clock generator 6 for generating a sampling clock from the horizontal synchronous signal separated from the synchronous signal separator 5, and the clock generator 6 outputted from the clock generator 6; A D / A converter 4 for receiving a clock signal and converting a digital signal output from the A / D converter 1 and the line memories 2 and 3 into an analog signal, and VBI (Vertical Blanking Inteval) of the composite video signal. The data slicer unit 7 which detects initial data in the section, the RAM 8 which stores the output signal of the data slicer unit 7, and the data stored in the RAM 8 A microprocessor 9 for controlling the memory 12 and an output signal of the A / D converter 1 A buffer 10 for supplying or cutting off the circuits 2 and 3, an inverter 11 for inverting the output signal of the A / D converter 1 and transferring it to the line memories 2 and 3, and the micro Line memory 12 receiving the address output from the processor 9 and generating the best bit (MSB) of data corresponding to the address, and triggering the best bit output from the line memory 12 during one horizontal period. Enable the buffer 10 and the inverter 11 to receive the latch 13, the signal output from the trigger 13 from the latch 13, and the image section detected by the image section detector 16.

(EN) buffer 14 and an address counter 15 for counting an address set for each horizontal section separated from the synchronous separator 5 and transmitting the counted address to the line memory 12 and the image interval detector 16; And an image section detector 16 for enabling the buffer 14 to detect a section in which an image is loaded by dividing the address counted by the address counter 15 in each section of the composite video signal in proportion to time. Image signal scrambling apparatus using the method.

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