JPH0373072A - High-speed picture processing circuit - Google Patents

Abstract

PURPOSE:To improve speed for processing image data by the rotation and/or reduction and enlargement processing of the image data, which are stored in a memory, with the configuration of a hardware. CONSTITUTION:Plural address adding registers 12-14 are provided to hold a constant to be determined based on the leading address of the memory to be accessed and the page width of the memory, a means 11 is provided to suitably take out the constant from the plural address adding registers 12-14 corresponding to the condition of picture processing. Then, a means 15 is provided to suitably add the constant to the leading address and to update the address. Corresponding to the condition of the picture processing such as the processing of rotation and the processing of reduction, etc., the constant to be stored in the plural address adding registers is determined and an order for the constant to be taken out form the address adding registers 12-14 is also determined corresponding to the condition of the picture processing. Thus, since the address for accessing the memory can be obtained as the circuit output of the hardware configuration, the processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a high-speed image processing circuit, and more particularly to a high-speed image processing circuit that can perform image processing such as rotation and reduction of image data at high speed.

(Prior Art) An example of a conventional image processing method will be described with reference to FIGS. 6 and 7. FIG. 6 is a bitmap diagram, and FIG. 7 is an address/data correspondence diagram in the memory. Figure 7(a)
1 shows the correspondence between addresses and data before processing, and (1) in the same figure shows the correspondence between addresses and data after rotation processing.

Now, suppose that N bits by N bits of image data are stored in the first memory 1 as shown in FIG. 6, and a case will be considered in which the data is rotated 90° clockwise. Here, it is assumed that N bits are A bytes.

First, the 1 byte shown in the bitmap diagram (
Focusing on ×1-byte image data 1a, and assuming that the address of 1-byte data alLa12, . . . , aln is Xl, as shown in FIG. 7(a), the following 1 byte data a21, a22,...
..., the address of a, 2n is (X1+A), the last 1
Byte data a nl, a n2,..., a
The address of nn is (X1+15A). Note that one byte is assumed to be 16 bits (ie, n=16) here.

When the process of rotating the data 90'' clockwise starts, the CPU (not shown) accesses the first memory 1, first specifies address X1, and reads the 1 byte stored at the address. transfer the data in parallel to shift register 2. When the transfer is completed, the CPU transfers the
The address (X 1 +A) of memory 1 is specified and the corresponding 1-byte data is transferred to shift register 2 in parallel. Similarly, 1 byte of data at addresses (X1+2A), . . . (X1+15A) of the first memory 1 are transferred to the shift register 2 in parallel.

The data thus stored in the shift register 2 is then cut out one byte at a time in the vertical direction. for example,
As shown in FIG. 6, all, a21,...
. . , 1 byte of data of anl is cut out and transferred to the address shown in FIG. 7(b) in the second memory 3.

That is, the CPU selects address 0 of memory 3 of scoop 2.
is specified, and the 1-byte data cut out in the vertical direction is stored in the second memory 3.

When this operation is completed, the next 1 byte of data is vertically cut out from the shift register 2 and stored at address A of the second memory 3 specified by the CPU. Similarly, the operation of sequentially cutting out the data stored in the shift register 2 one byte at a time in the vertical direction and the operation of storing this at addresses 2A, 3A, . . . , 15A of the second memory 3 are performed. It is done alternately. Through the above operations, data obtained by rotating the 1 byte x 1 byte data clockwise by 90'' is obtained in the second memory 3.

Thereafter, similar operations are repeated to obtain image data obtained by rotating the image data 1a stored in the first memory 1 clockwise by 90' in the second memory 3.

The above explanation is an example of rotating the data 90° clockwise, but the same can be done when rotating the data 270° clockwise.

(Problems to be Solved by the Invention) As is clear from the above description, in the conventional image processing method, the address calculation operation for reading all the image data in the first memory 1 into the shift register 2, the shift The image data extracted from register 2 is transferred to the second
Since the arithmetic operation of the address for writing into the memory 3 is performed by the program of the CPU, that is, the processing is performed by software, there is a problem that the number of questions to be processed becomes large.

The purpose of the present invention is to eliminate the problems of the conventional method described above,
An object of the present invention is to provide an image processing circuit that can perform image data rotation processing at high speed.

(Means and Effects for Solving the Problems) In order to achieve the above object, the present invention includes a plurality of address addition registers that hold constants determined based on the start address of the memory to be accessed and the page width of the memory; The present invention is characterized in that it includes means for appropriately extracting a constant from the plurality of address addition registers according to the mode of image processing, and means for appropriately adding the constant to the first address to update the address.

In the present invention, the constants stored in the plurality of address addition registers are determined depending on the aspect of image processing such as rotation processing and reduction processing.

Further, the order in which the constant numbers are taken out from the address addition register is also determined depending on the mode of the image processing.

Then, the extracted constants are sequentially added to the first address, and the image data stored in the memory is accessed using the address obtained by this operation.

As a result, the address for accessing the memory can be obtained as a circuit output of the hardware configuration, and the processing speed can be increased.

(Example) The present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 8 is a memory in which image data before processing and image data after processing are stored, and 9 is a memory having a size of 1 byte (for example, 16 bits) x 1 byte.
270') This is a shift register for the same diversion. 10 is CP
U, 11 is an address decoder that decodes the address output from the CPU 10, 12, 13, 14 is an address addition register that stores addition data for adding addresses, 15 is an adder, and 16 is an address decoder that outputs an address. This is an address register that latches the output of the adder 15. Further, 17 is a first memory address buffer for holding the address output from the vibrator 15 and accessing the memory 8 using the address, and 18 is a CPU l
0 is the second memory address buffer used when accessing the memory 8 during normal operation.

Next, the operation of this embodiment will be explained. When the CPU10 accesses the memory 8 during normal operation, the memory chip select signal (M
EMC3 signal)lla becomes active. For this reason,
The second memory address buffer 18 becomes operational,
The CPU I O accesses the memory 8 via the buffer 18 .

Next, the operation of rotating 90'' clockwise will be explained. As shown in FIG. It is assumed that the area 8b is divided into a second area 8b in which processed image data is stored, and the text width is A1 bytes. Focusing on the area 8al of 1 byte x 1 byte in the first area 8a, If the start address of the area 8al is AO, the address corresponding to the area 8al is A.
O~(AO+15AI). The area 8al is 90
'In order to perform clockwise rotation processing, the area 8al is once transferred to the shift register 9, and the area 8al is transferred to the shift register 9.
The data rotated in one direction (at 90'') can be cut out byte by byte and transferred to the area 8bl of the second area 8b.If the start address of the area 8bl is BO, the transfer destination address is BO. ~(BO+15AI).

The correspondence between the read address and the write address (transfer destination address) when processing the next 1 byte x 1 byte area to the right of the area 8al of the first area 8a is shown in the middle part of FIG. It becomes like this. That is, the addresses of the first area 8a (AO+1) to (AO+15A,
+1) and write it to addresses (BO+16AI) to (BO+30AI) of the second area 8b.

Here, with reference to FIG. 1, the operation of rotating 90'' clockwise will be explained in detail.It will be easier to understand if FIG. 2.3 is also referred to.

First, the CPU 10 stores the text congestion At of the memory in the first address addition register 12. The storage is performed by the CPU
Data A1 from l0 and the first address addition register 1
This is done by outputting an address that triggers 2. T of the first address addition register 12 indicates a trigger terminal.

Similarly, CPU10 also stores BO in the second address addition register 13 and AO1O2O3 address addition register 14.

Next, the address decoder 11 sends a signal sl as shown in FIG. 4 to the E (enable) terminal of the second address addition register 13 in response to a signal from the CPU II. When the signal sl is input, the second address addition register 13 sends the data AO to the adder 15 during the L level period TO. The signal sl is the address register 1
6 and the E terminal of the first memory address buffer 17.

As a result, the first memory address buffer 17 is enabled during the L level period TO, and the data AO, which is the output of the adder 15, is input to the memory 8 via the first memory address buffer 17. Ru. In this way, the address AO of the memory 8 is accessed, and the image data read from the memory 8 is temporarily transferred to the CPU 10.
The data is then transferred from the CPU 10 to the shift register 9.

Next, when the signal sl rises, the address register 16 latches the data AO at its edge 11.

Next, the address decoder 11 continuously sends the signal S() to the E terminal of the first address addition register 12. Then, the data A1 stored in the first address addition register 12 is Each time sl goes to L level, it is read out and added to the data latched in the address register 16 in an addition 415.The addition result is sent to the first memory address buffer 17, thereby storing data in the °C memory. Further, the addition result is latched in the address register 16 every time the re-edge h of the signal sl occurs.

By the above operation, the addresses (AO to AO+) of the memory 8 are changed.
15Al) is accessed and the corresponding data is transferred to the shift register 9.

When the transfer is completed, the transfer register 9 then registers 9.
When 0'' = data rotated in one direction is cut out one byte at a time, and the operation moves to the area 8bl of the second area 8b of the memory 8a. First, the address register 16 is cleared, and the third address addition register 14 The signal S() is sent from the address decoder 11. Then, the data BO is read from the third address addition register 14, enters the adder 15, and its output is sent to the first memory address buffer 17. As a result, the address BO of the memory 8 is accessed.The data BO is accessed from the address register 16 at the rising edge h of the signal St.
latched to.

From the next timing, the signal sl is continuously sent to the E terminal of the first address addition register]2. As a result, memory 8 has addresses (BO+AI), (BO+
2 A1. ) , -... -... (BO+15A1.)
are sequentially accessed, and image data corresponding to statement 1 is sequentially stored at the addresses.

Through the above operations, the image data in the area 8al of the memory 8 is rotated 90'' clockwise and stored in the area 8bl.

When the operation is completed, the first area 8a of the memory 8 is
The process moves on to rotation processing of the 1 byte x 1 byte image data on the right side of the area 8al inside. When this operation starts, the set value of the second address addition register 13 is (AO+1)
and the third address addition register 14
The set value is changed to (Bo +16AI), and the same operation as described above is repeated.

When the above operations are performed on all the image data stored in area 8a of memory 8':jSl,
Image data obtained by rotating the image data by 90° clockwise can be obtained in the second area 8b.

Next, the operation when simultaneously applying rotation and reduction processing to the image data stored in the first area 8a of the memory 8 will be explained. Here, the operation of rotating 90 inches clockwise and reducing the size by 2/3 will be explained with reference to FIG.

When reducing the image data by 2/3 times, it is necessary to reduce both the horizontal and vertical directions of the image data by 2/3 times, so when reading data from the memory 8, one line is thinned out for every three lines. , writing from the shift register 9 to the memory 8 is performed such that one line is thinned out for every three lines. For this purpose, the read and write addresses of the memory 8 need only be in the order shown in FIG.

Therefore, the CPU 10 in FIG.
The operation is to set the data AO to 4.

Next, the data AO set in the third address addition register 14 is read out, and the address AO of the memory 8 is accessed in the same manner as described above.

After accessing the address AO, the data AI set in the first address addition register 12 is then read out, and the address (AO+AI) of the memory 8 is accessed. Next, the data 2AI set in the second address addition register 13 is read out, and the address (
An+3AI).

Thereafter, the first address addition register 12 and the second
The data set in the address addition register 13 are read alternately, and the address of the memory 8 is determined. When this operation is repeated, the image data of 1 byte x 1 byte in area 8a, 1 of memory 8 is reduced by 2/3 times in the vertical direction and stored in the shift register 9.

Next, when transferring the image data from the shift register 9 to the area gbt of the memory 8, each of the first, second, and third address addition registers 12, 13, and 14 has the following information:
Data At, O, and BO are set.

Then, first, data BO is read from the third address addition register 14, and thereby the address B of the memory 8 is read out.
O is accessed. Then, 1 byte of data rotated 90'' from the shift register 9 is stored in the address BO.Next, data A1 is read from the first address addition register 12, and the address (BO+
A1) is accessed. Next, data Al is read out from the first address addition register 12 again, and the memory 8
address (BO+2Al) is accessed. At the next timing, data 0 is read from the second address addition register 13, so the address of the memory 8 does not change and the address (BO+2Al) is accessed again.

In this manner, when the same address in the memory 8 is accessed twice in succession, the next image data is overwritten on the image data previously stored at the address, and the core image data is erased.

In other words, the image data of the nucleus has been thinned out.

When the above operations are repeated, image data reduced by 2/3 in the horizontal direction is obtained on the area gal.

By repeating the above operations, all the image data in the first area 8a of the memory 8 is rotated 90° clockwise and reduced to 2/3 times.

Note that the above operation was an example in which the image data was rotated 90 degrees clockwise, but rotation by 270 degrees clockwise also applies to the first to third address addition registers 12 to 1.
It is clear that this can be achieved by simply changing the data value set to 4 and the reading order. Furthermore, it goes without saying that the reduction processing is not limited to 2/3 times, and enlargement processing is also possible.

Further, although the present invention uses three address addition registers, the present invention is not limited to this.

(Effects of the Invention) As is clear from the above introduction, according to the present invention, in order to rotate and/or reduce or enlarge image data stored in the memory, an address for accessing the memory is programmed. Since this can be done with a hardware configuration rather than through clearing, the processing speed of image data can be significantly increased.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the present invention, Fig. 2 is an explanatory diagram of data transfer in rotation processing operation, Fig. 3 is an explanatory diagram of address conversion, and Fig. 4 is a signal applied to the E terminal of the address addition register. FIG. 5 is an explanatory diagram of address conversion during rotation and reduction processing, FIG. 6 is a conceptual diagram of a conventional image processing system, and FIG. 7 is an explanatory diagram of the address conversion. 8...Memory, 9...Shift register, 10...
CPU.

Claims (1)

[Claims] (1) A plurality of address addition registers that hold constants determined based on a start address and a memory page width, means for selectively enabling the plurality of address addition registers, and a means for selectively enabling the plurality of address addition registers; means for repeatedly adding a constant from the address addition register, means for accessing memory using the output of the addition means as an address, and means for updating settings of the start address and the constant in the address addition register. A high-speed image processing circuit, comprising: a high-speed image processing circuit capable of performing processes such as rotation and reduction of image data stored in the memory at high speed.