JPH0371816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power supply voltage detection circuit that detects a power supply voltage at a predetermined level and generates a control signal, such as a reset signal for returning an electronic circuit device to an initial state.

In electronic circuit devices, it is important to set the internal state of the circuit device to a predetermined initial state when the power is turned on or when there is an abnormality in the power supply voltage, to ensure that the circuit operates normally thereafter. This is a great feature.

For example, a semiconductor integrated circuit device is equipped with a terminal (hereinafter referred to as a reset terminal) for applying the above-mentioned reset signal, that is, a reset signal. It is possible to automatically apply a reset in the event of a voltage abnormality (so-called power-on reset), or to force a reset by applying an external reset signal to this terminal.

FIG. 1 is a diagram showing an example of a circuit in which a reset terminal is provided with a predetermined time constant in order to automatically perform a power-on reset when the power is turned on. In the semiconductor integrated circuit device, 2 is a reset terminal, 3 is a power supply terminal, and 4 and 5 are resistors and capacitors for providing a time constant. In this circuit, when the power is turned on, the capacitor 5 is charged through the resistor 4, and this terminal voltage is supplied as a reset signal to the reset terminal 2 for a certain period of time, and the semiconductor integrated circuit device 1 is reset.

Further, FIG. 2 shows an example of a circuit in which a clock pulse is applied to the reset terminal 2 to forcefully apply a reset. In this circuit, as shown in the figure, a clock pulse is applied to the reset terminal 2 of the semiconductor integrated circuit device 1, the switch element 6 connected to the reset terminal 2 is made conductive, and the charging path of the capacitor 7 is closed. Therefore, a circuit configuration is adopted in which the capacitor 7 is charged.

By the way, in the conventional circuit shown in the figure, if the rise of the power supply voltage is gradual, the rise of the voltage at the reset terminal 2 will follow the rise of the power supply voltage. Power-on reset may not work.

Figure 3 is a diagram showing this situation, and Figure 3a shows the power supply voltage when the rise of the power supply voltage is steep.
FIG. 3b shows the relationship between V _S and the reset terminal voltage V _R , and FIG. 3b shows the relationship between both voltages when the power supply voltage rises slowly.

As shown in the figure, in Figure 3a, the reset period is set to a sufficient length and the reset function is activated when the power supply voltage V _S rises and becomes sufficiently stable, but in Figure 3b, the reset function is activated. The period is short, and there is a risk that the reset function will operate at a time when the power supply voltage has not sufficiently risen. Also, if you turn the power on and off quickly, the reset terminal 2
The charge accumulated in the capacitor connected to the power supply may not be sufficiently discharged, and the power-on reset may not work.

As described above, conventional circuits still have problems that need to be solved.

The present invention has been made in view of the above-described disadvantages of the conventional circuit, and provides a method for outputting a predetermined control signal, for example, a reset signal for activating the reset function of an electronic circuit device, in response to fluctuations in power supply voltage. The present invention provides a power supply voltage detection circuit that can perform the following functions.

The present invention includes a first power supply voltage detection means that detects a first voltage value and generates a logic level signal, and a second voltage value that is higher than the first voltage value and generates the logic level signal. a second power supply voltage detection means, a gate circuit, and a reset/set-flip-flop circuit;
The logic level signal from the first power supply voltage detection means is inverted and the reset/set-flip signal is inverted.
A logical product signal of the logic level signal from the second power supply voltage detection means and the output signal of the reset set flip-flop circuit is applied to the set input terminal of the flop circuit.
The logic level signal from the power supply voltage detection means is synthesized with the inverted signal and NOR logic to generate the reset signal.
The power supply voltage detection circuit includes feedback circuit means for applying to the reset input terminal of the set-flip-flop circuit.

The configuration and operation of the power supply voltage detection circuit of the present invention will be described in detail below with reference to the drawings.

FIG. 4 is a diagram showing the configuration of a power supply voltage detection circuit according to an embodiment of the present invention, showing first and second power supply voltage detection sections 8 and 9 having different detection levels, and gates to which these outputs are input. It consists of a circuit section 10 and a reset/set (RS) flip-flop 11 which operates upon application of the output of this gate circuit section. Note that the gate circuit section 10 has 2
The output signal of the RS flip-flop 11 is fed back to one of the input terminals of the AND circuit 14.

In the power supply voltage detection circuit of the present invention configured as described above, the detection level of the first power supply voltage detection section 8 is set so as to detect a voltage value at a lower level than that of the second power supply voltage detection section 9. Moreover, both detect a voltage value of a predetermined level and generate a high level "H" output in a logical operation. Such a power supply voltage detection section is configured as shown in FIG. 5, for example.

FIG. 5 is an example of a circuit in which a single power supply voltage detection section is constructed using MOS transistors, and as shown in the figure, the gate and drain are commonly connected,
The source of one enhancement MOS transistor 16 whose common connection point is connected to the power supply terminal 31 and the drain of the other depletion MOS transistor 17 whose gate and source are commonly connected and whose common connection point is connected to the ground point. are commonly connected, and furthermore, an output terminal 18 is attached to this common connection point. The detection level of the power supply voltage detection section configured in this manner can be arbitrarily set by selecting the conduction resistance value of the enhancement MOS transistor 16.

That is, in both the first power supply voltage detection section 8 and the second power supply voltage detection section 9, the characteristics of the MOS transistor 17 on the side not involved in detection level setting are made the same, while the characteristics of the MOS transistor 17 on the side involved in detection level setting are made the same. If the relationship α>β is established between the conduction resistance values α and β of the MOS transistor 16, the above-mentioned relationship, that is, the first power supply voltage detection section 8 is lower than the second power supply voltage section 9, is established. The detection level is set.

For example, when a power supply voltage as shown in FIG. 6a is applied to the power supply voltage detection circuit of the present invention, the following circuit operation is performed, and the RS
A desired signal is output to the output terminal Q of the flip-flop 11.

That is, at time _t1 just before the power supply voltage rises, the output levels of both the first and second power supply voltage detection sections 8 and 9 are both at the "L" level, as shown in FIG. 6b and c. be. Therefore, both outputs of inverters 12 and 13 go to the "H" level, and the RS flip-flop 11 is controlled by the signal at the set input terminal S, and its output Q goes to the "H" level as shown in FIG. becomes. by the way,
The AND circuit 14 includes the output of the inverter 13 and the RS
It is coupled to the output of flip-flop 11, and since both outputs are at the "H" level under the above circumstances, the output level is also at the "H" level. Therefore, the output level of the NOR circuit 15 becomes "L" level, and there is no signal to the reset input terminal R of the RS flip-flop 11, so that no inversion of the output occurs.

When the power supply voltage rises and reaches the detection level A of the first power supply voltage detection section 8 at time _t2 , the first power supply voltage detection section 8 detects this voltage level and its output level becomes "H". level. Therefore, the output level of the inverter 12 becomes "L" level, but the input level of the AND circuit 14 does not change, and therefore the output level of the NOR circuit 15 also does not change.

When the power supply voltage further increases and reaches the detection level B of the second power supply voltage detection section 9 at time _t3 , both the first and second power supply voltage detection sections 8 and 9 detect the power supply voltage, and both Both output levels are “H”
In addition, the output levels of both inverters 12 and 13 are both at the "L" level. For this reason,
The output level of the AND circuit 14 becomes the "L" level, the two inputs of the NOR circuit 15 both become the "L" level, and therefore the output level of the NOR circuit 15 becomes the "H" level. RS flip-flop 1
1 is controlled by the signal of the reset input terminal R at this timing, and the level of its output terminal Q is "H".
The level is reversed to "L" level.

Next, a case will be described in which a fluctuation Vf ₁ occurs in which the power supply voltage reaches a predetermined value, drops to an intermediate level between detection levels B and A, and then returns to the predetermined value. This corresponds to the case where the power supply includes ripples. In this case, in Figure 6,
At time _t4 when the power supply voltage passes detection level B, the level of the second power supply voltage detection unit 9 changes from "H" level to "L" level, and from "L" level to "H" level at time _t5 . However, since the output level of the first power supply voltage detection section 8 is held at the "H" level, the potential level of the output terminal Q of the RS flip-flop 11 does not change, and its level remains at the "L" level. is maintained. Next, a case where a fluctuation Vf ₂ in which the power supply voltage falls below the detection level A occurs will be described. This is the case, for example, when large power supply voltage fluctuations need to be detected and circuit operation reset. In this case, as shown in FIG. 6, the output level of the second power supply voltage detection section 9 changes at times t ₆ and t ₉ , while the output level of the first power supply voltage detection section 9 changes at times t ₇ and t ₈ . The output level of section 8 changes. 1st
At time _t7 when both the output levels of the second power supply voltage detection sections 8 and 9 become "L" level, the RS flip-flop 11 is controlled by the signal of the set input terminal S, and the potential level of its output terminal Q is changes to “H” level, then the first and second
At time _t9 , when both the output levels of the power supply voltage detection units 8 and 9 become "H" level, the RS flip-flop 11 is again controlled by the signal of the reset input terminal R, and the potential level of its output terminal Q becomes "L". “It becomes a level.

Based on the above operation, the potential level of the output terminal Q of the RS flip-flop 11 changes as shown in FIG. 6d, and this is taken out as a control signal. Therefore, by utilizing the falling edge when the potential level of the output terminal Q is inverted from the "H" level to the "L" level, it is possible to generate a reset signal for power-on reset of the electronic circuit device. can.

With the power supply voltage detection circuit of the present invention described above, (1) the power supply voltage can be reliably detected even when the rise of the power supply voltage is gradual;

(2) Even if ripples are superimposed on the power supply,
This can be absorbed as long as it does not fall below a preset detection level.

(3) Even if the power is turned on and off quickly, it can be correctly detected and, for example, a reset signal for power-on reset to an electronic circuit device can be reliably generated.

It is possible to solve all the problems that remained with conventional circuits.

As is clear from the above explanation, according to the power supply voltage detection circuit of the present invention, the reset operation of the electronic circuit device can be performed reliably and stably, and the reliability of the electronic circuit device can be significantly improved. can.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional circuit in which the reset terminal has a predetermined time constant, Fig. 2 is a circuit diagram showing an example of a conventional circuit in which reset is forcibly applied by a clock pulse, and Fig. 3 a. , b are voltage characteristic diagrams showing the relationship between the power supply voltage and the reset terminal voltage, FIG. 4 is a circuit diagram showing an embodiment of the power supply voltage detection circuit of the present invention, and FIG. 5 is the power supply voltage detection section shown in FIG. FIGS. 6A to 6D are timing diagrams showing the relationship between changes in the power supply voltage and the output levels of the main parts of the power supply voltage detection circuit. 1... Semiconductor integrated circuit device, 2... Reset terminal, 3, 31... Power supply terminal, 4... Resistor, 5, 7
...Capacitor, 6...Switch element, 8,9...
...Power supply voltage detection section, 10... Gate circuit section, 11
...RS flip-flop, 12,13...Inverter, 14...AND circuit, 15...NOR circuit, 16,17...MOS transistor, 18...
...Output terminal.

Claims (1)

[Claims] 1 a first power supply voltage detection means that detects a first voltage value and generates a logic level signal; a second power supply voltage detection means that detects a second voltage value higher than the first voltage value and generates a logic level signal; The first power supply voltage detection means includes a gate circuit and a reset/set flip-flop circuit, and the gate circuit inverts the logic level signal from the first power supply voltage detection means to detect the reset/set/flip-flop circuit. is added to the set input terminal of the flop circuit, and the second
A logical product signal of the logic level signal from the first power supply voltage detection means and the output signal of the reset/set flip-flop circuit is combined with a signal obtained by inverting the logic level signal from the first power supply voltage detection means.
A power supply voltage detection circuit comprising feedback circuit means for synthesizing NOR logic and applying it to the reset input terminal of the reset-set-flip-flop circuit.