JPH0371497A - Reading method for semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the data reading speed by applying a read voltage to a drain line, and precharging a gate line and then reading held data out of a semiconductor memory element when the data held in the semiconductor memory element is read. CONSTITUTION:Memory elements M1 - M8 are provided at respective intersections of gate lines G1 and G2 and drain lines D1 - D4 which are arranged in matrix, and the drain lines D1 - D4 are applied with the read voltage V+ through MOS transistors(TR) 11 - 14. Then the gate lines G1 and G2 are precharged with gate line select signals GA1 and GA2 and after data of memory elements M1 - M4, and M5 - M8 are determined, the data are read out. Consequently, data read signals CA1 - CA4 need not be give time width for charging-up operation and the data read speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for reading a semiconductor memory capable of high-speed reading.

[Prior Art] Conventionally, reading data from a semiconductor memory is performed by the following method. Hereinafter, the case of a mask ROM as a semiconductor memory will be explained as an example.

FIG. 5 shows a schematic configuration for reading data in a mask ROM having eight memory elements M1 to M8. The memory element Ml-M8 is configured using MOS transistors, and has gate lines Gl arranged in a matrix.

It is provided at each intersection between G2 and the drain line Di-D4. The memory elements Ml to M8 store data "
The gate electrodes of the elements storing 12 are selectively connected to the corresponding gate lines Gl and G2. In this case, a memory element storing data "0", for example M2. The gate electrode of M7 is not connected to gate lines Gl and G2. Furthermore, the memory elements M1 to M8 have their drain electrodes connected to the corresponding drain lines D1 to D4, and their source electrodes grounded.

The drain lines D1 to D4 are connected to drain electrodes of column switches 1 to 4 made up of MOS transistors. The column switches 1 to 4 are sequentially turned on by a data read signal applied to the gate electrode, that is, a column selection signal, and the drain lines D1 to D4
are sequentially selected and connected to the buffer circuit 10. The buffer circuit 10 is mainly composed of a MOS transistor Tl-73, and amplifies data read out from the memory elements M1 to M8 via the drain line DI-D4 and column switches 1 to 4 and outputs the data to an output terminal OUT. Output from

The semiconductor memory configured as described above is driven according to the timing chart shown in FIG.

In FIG. 6, GAI and CA2 are gate line selection signals, and CAL-CA4 is a column selection signal. First of all,
A gate line selection signal GAI is applied to the gate line Gl, and memory elements Ml-M4 on the gate line G2 are selected. Then, while the gate line selection signal GAI is at a high level, the column selection signal CAl-
When CA4 is applied, column switches 1 to 4 are sequentially turned on, and data held in memory elements M1-M4 is sequentially read out via drain lines D1-D4 and buffer circuit 10.

Next, when the gate line selection signal CA2 is applied to the gate line G2, the column selection signal CA2 is applied to the gate line G2 as in the above case.
Data held in memory elements M5 to M8 is sequentially read out via drain lines DI to D4 and buffer circuit 10 in synchronization with L-CA4.

[Problems to be Solved by the Invention] Data stored in the semiconductor memory is read as described above, but in the conventional data reading method, when reading data, the gate line Gl.

It is necessary to keep the hook column switches 1 to 4 on for a time period t or longer for G2 to charge up, which causes the problem that the time width of the column selection signals CAL-CA4 becomes wide and it takes time to read data.

The present invention was developed in view of the above-mentioned circumstances, and an object of the present invention is to provide a semiconductor memory reading method that can improve the data reading speed of a semiconductor memory.

[Means and effects for solving the problem] The present invention provides a semiconductor memory in which semiconductor memory elements are arranged in a matrix and a gate electrode and a drain electrode are connected to a gate line and a drain line, respectively. A voltage is applied to precharge the gate line when reading the data held in the semiconductor memory element, and then the data held in the memory element is read out.

By precharging the gate line before reading data as described above, there is no need to provide a time width for charging up the data read signal, and the stored data can be reliably read out using a read signal with a short time width. It is possible to improve the data read speed.

Further, in the present invention, the memory area is divided into two areas, the memory elements in each memory area are precharged with a certain time difference, and then the data held in each memory element is sequentially read out. be.

By precharging two memory areas with a certain time difference as described above, precharging can be completed while data is being read from the other memory area, thereby reducing wasted precharging time. Without this, it becomes possible to read data continuously, and the data reading speed can be further improved.

[First embodiment Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an example in which a mask ROM is implemented as a semiconductor memory, and to simplify the explanation, the case is shown in which eight memory elements M1 to M8 are arranged in two rows and four columns. The memory element Ml-M8 is configured using MOS transistors, and has gate lines Gl and G2 and drain lines Dl to D arranged in a matrix.
4 at each intersection. In the memory elements M1-M8, the gate electrodes of the elements storing data "1" are selectively connected to the corresponding gate lines G1 and G2. In this case, a memory element storing data "0", for example M2. The gate electrode of M7 is connected to the gate lines Gl, G
2 is not connected.

Furthermore, in the memory element Ml-M8, the drain electrode is connected to the corresponding drain line Di-D4, and the source electrode is grounded.

A read voltage V+ is supplied to the drain line Di-D4 via MOS transistors 11-14. The drain electrodes of the MOS transistors 11-14 are connected together with the gate electrodes to the V+ power supply, and the source electrodes are connected to the drain lines D1-D4.

The drain line DI-D4 is connected to the drain electrodes of column switches 1 to 4 made up of MOS transistors. The column switches 1 to 4 are sequentially turned on by a column selection signal applied to the gate electrode.
Drain lines D1 to D4 are sequentially selected and connected to the buffer circuit 10. The buffer circuit 10 is mainly composed of a MOS transistor Tl-73, and amplifies the data read from the memory element Ml-M8 and outputs the amplified data from the output terminal OUT.

Next, the data read operation for the semiconductor memory will be explained with reference to the timing chart of FIG. In the same figure, GAI and CA2 are gate line selection signals, and C
AL-CA4 is a column selection signal. Gate line selection signal GAIGA2 selects gate line G1. When G2 is selected, the column selection signal CAR-CA4 is applied, but the gate line selection signals Gl and G2 rise earlier than the column selection signal CAR-CA4 by the time t required to charge up the gate lines Gl and G2. While column selection signals CAI to CA4 are being output, they are held at a high level state.

Therefore, when reading data, first, the gate line selection signal GAI is applied to the gate line C1, and the gate line C1 is precharged. The above memory element M
Since the read voltage is applied to l-M4 through the MOS transistors 11 to 14, when the precharging of the gate line G1 is completed after the time, the gate line C
4-bit data on memory elements M1 to M
The data of 4 is confirmed. In this state, column selection signals CAL to CA4 shown in FIG.
are sequentially read out via the

Next, when the gate line selection signal CA2 is applied to the gate line G2, the column selection signal CAl-
Data held in memory elements M5 to MB is sequentially read out via drain lines Di to D4 and buffer circuit 10 in synchronization with CA4.

Gate line selection signal GAI as described above.

By precharging the gate lines Gl and G2 by CA2 and reading the data after the data in the memory elements M1 to M4 and M5 to M8 is determined, the pulses of the column selection signals CAL to CA4 are changed as shown in FIG. It becomes possible to read data while reducing the width to a fraction of the conventional width. In the timing chart in Figure 2, 4
The time to output bit data is the precharge time t
In this case, data can be read at twice the speed of the conventional method. Further, the data read speed can be increased to the limit of the switching speed of the column switches 1 to 4.

[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4. In the first embodiment, after reading all the data of the memory elements Ml-M4 on the gate line Gl,
The precharge operation is performed by supplying the gate line selection signal GA2 to the next gate line G2. Data is not read during this precharge period, but in the second embodiment, the memory area is By dividing the memory into systems, the recharging operation can be performed efficiently and data can be read out continuously.

That is, as shown in FIG. 3, the memory area is divided into a first memory area MA and a second memory area MB, the first memory area MA is configured with the memory circuit shown in FIG. MB has gate line cut, G12
memory elements M11 to M18 provided above, MOS transistors 11 to 14 that supply read voltage V+ to drain lines D5 to D8 of the memory elements Mll to M1g;
Column switches 5 to 8 that select drain lines D5 to D8 constitute a memory circuit similar to that of the first memory area MA. The gate lines Gll and G12 are
Gate line selection signal GAI1. Column switches 5 to 8 are selected by column selection signal CA5.
~ Controlled on/off by CA8.

The 8-bit data read out via the column switches 1 to 4 in the first memory area MA and the column switches 5 to 8 in the second memory area MB is input to the buffer circuit 10. That is, this buffer circuit 10 is shared by the memory circuits of the first memory area MA and the second memory area MB.

In the above configuration, the first memory area MA and the second memory area MB are read-out controlled at the same timing as in the first embodiment, but as shown in the timing chart of FIG. 2nd for area MA
Gate line selection signals GA5 to GA8 and column selection signal C are supplied to the memory area MB with a delay of precharge time t.
A5 to C1B are given.

Therefore, first, the gate line selection signal GAI is applied to the first memory area MA to start the precharging operation of the gate line G2. Then, after the precharge time t has elapsed, the column selection signals CAL-CA4 are sequentially applied to turn on the column switches 1-4, and the data held in the memory elements M1-M4 on the gate line GI are transferred to the drain lines D1-D4 and the column switches 1-4. The data are sequentially read out via the buffer circuit 10.

Further, after the gate line selection signal Gl is applied,
After the precharge time t has elapsed, the second memory area MB
On the other hand, a gate line selection signal GAII is applied to start a precharging operation of the gate line Gll. That is, while data is being read from the memory elements M1-M4, the gate line Gll is precharged. Therefore, when data reading from memory elements M1 to M4 in the first memory area MA is completed,
Precharging of the gate line Gll in the second memory region MB is completed, and data reading from the memory region MB side becomes possible. In this state, column selection signals CA5 to CA&
is applied, the column switches 5 to 8 are sequentially turned on, and the data held in the memory element Mll-M14 on the gate line Gll is transferred to the drain lines D5 to DB and the buffer circuit 10.
are sequentially read out via the

Further, while the data held in the memory elements Mll-14 is being read out from the second memory area MB by the column selection signals CA5-CA8, the gate line selection signal G2 is applied to the first memory area MA side, and the gate line selection signal G2 is applied to the first memory area MA side. Precharging for G2 is performed.

Thereafter, stored data is read out alternately from the first memory area MA and the second memory area MB in the same manner.

As described above, according to the second embodiment, the first memory area MA and the second memory area MB are provided, and the gate line G is precharged while data from the other area is being read. 1. Therefore, the precharge operation can be performed efficiently and data can be read out continuously.

[Effects of the Invention] As detailed above, according to the present invention, in a semiconductor memory in which semiconductor memory elements are arranged in a matrix and a gate electrode and a drain electrode are connected to a gate line and a drain line, respectively, the drain line A read voltage is applied to the semiconductor memory element, and the gate line is precharged when reading data held in the semiconductor memory element.
After that, the data held in the memory element was read out using the RBJ signal, so there was no need to charge the memory element when the read signal was applied, and the Li output 1-
It is possible to reliably read out stored data without using a signal, thereby improving the data read speed.

Furthermore, in the present invention, the memory area is divided into two areas, and each memory area precharges the memory elements while data is being read in the other memory area, thereby reducing waste during precharging. Without this, it becomes possible to read data continuously, and the data reading speed can be further improved.

In the above embodiments, a case has been described in which the present invention is implemented in a mask ROM, but it can also be implemented in a semiconductor memory other than a mask ROM in the same manner as in each of the above embodiments.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a circuit configuration when reading data from a conductive memory according to a first embodiment of the present invention, FIG. 2 is a timing chart for explaining the operation of the same embodiment, and FIG. A block diagram showing the circuit configuration when reading data in the second embodiment of the invention, FIG. 4 is a timing chart for explaining the operation of the second embodiment, and FIG. 5 shows the circuit configuration when reading data from a conventional semiconductor memory. FIG. 6 is a timing chart for explaining the operation of FIG. 5. Ml-MB, Mll-Mlg...memory element, G
l. G1. Gll, G12...Gate line, DI
-D8...Drain line, 1-8...Column switch, 10...Buffer circuit, 11-14.21-2
4...MOS) transistor, MA...first memory area, MB...second memory area.

Claims (2)

[Claims] (1) Semiconductor memory elements are arranged in a matrix, and gate electrodes and drain electrodes are connected to gate lines, respectively.
In a semiconductor memory connected to a drain line, a voltage supply means for supplying a read voltage to the drain line, a precharging means for precharging the gate line when reading data held in the semiconductor memory element, and a precharging means for precharging the gate line when reading data held in the semiconductor memory element; A method for reading a semiconductor memory, comprising: data reading means for reading data held in the memory element after precharging the gate line. (2) Semiconductor memory elements are arranged in a matrix, and gate electrodes and drain electrodes are connected to gate lines, respectively.
first and second memory means connected to a drain line; voltage supply means for supplying a read voltage to the drain line; and voltage supply means for supplying a read voltage to the drain line; The present invention further comprises a precharging means for precharging the gate lines with a certain time difference, and a data reading means for sequentially reading data held in the memory elements in the first and second memory means after the precharging. Features: A reading method for semiconductor memory.