JP3158477B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art As shown in FIG. 9, a conventional semiconductor memory device includes a pair of bit lines BL1 to BL4 for writing or reading complementary data, and a pair of bit lines BL1 to BL4.
A word line W1 perpendicularly intersecting BL4 and a bit line pair B
Any one of bit lines BL1 and BL4 of L1 to BL4
Or a memory cell array block composed of memory cells M1 and M2 existing at the intersection of BL2 and BL3 with word line W1. FIG. 9 shows a bit line pair BL1, BL2, B
For two sets of L3 and BL4, the word line is driven by the drive signal φW
, Only two memory cells M1 and M2 present at the intersection of the word line W1 and the bit lines BL1 and BL3 are shown. Further, the bit line pair BL1 and BL2 are connected to a sense amplifier 901 driven by a drive signal φS, and complementary data is differentially amplified by the sense amplifier 901 to generate a column switch drive signal φ.
The signal is transmitted to the partial I / O line pairs IO1 and IO1B via the column switch 902 controlled by Y.

On the other hand, a sense amplifier 90 similarly driven by a signal φS also applies to a pair of bit lines BL3 and BL4.
3 and transmitted to the partial I / O line pair IO2, IO2B by the column switch 904 controlled by the signal φY.

The I / O line pairs IO1 to IO2B and the sense amplifiers 901 and 903 are connected to bit lines BL1 and BL2; BL3 and BL4 as the memory cells M1 and M2 are miniaturized.
Since it has become impossible to arrange them between the books, they are alternately arranged outside the memory cell array blocks M1 and M2. 2 out of the memory cell array blocks M1 and M2
Sets of partial I / O line pairs IO1, IOB; IO2, IO2
B is an I / O bus switching control signal φ as shown in FIG.
I / O selector switches 905 and 90 to which IL and φIR are supplied
6, one of the partial I / O lines IO1 to IO2B
Is transmitted to the IO line pair IO, IOB.

The above-described drive signals φW, φS, φY, φIL, φI
R and the like are generated by the control circuit 907 shown in FIGS. In the following, description will be made in order. First, an address signal Xi or Yj is generated by taking in a chip select signal CS (overline) from an address input terminal together with their inverted signals Xi (overline) and Yj (overline). (The AND circuit 908 and the inverter 9 in FIG. 11)
09). The generated X0 to Xm and their inverted signals are supplied to an AND circuit 910 to generate a word line drive signal φW. In FIG. 11, X0 to X
Only the AND circuit 910 where m is input and φW is generated is shown. Similarly, the column switch drive signal φY is generated by an AND circuit 911 to which the remaining address bits Y1 to Yn except for the Y01 bit and their inverted signals are supplied. FIG. 11 shows only the AND circuit 911 in which Yn is input from Y1 and φY is generated. Address bits Y0 not used for generating column switch drive signal φY are supplied to AND circuits 912 and 913 shown in FIG.
It is used to generate O bus switching control signals φIL and φIR.

Next, the operation of the conventional example will be described in time, assuming that the address bits supplied to the address input terminals are all "1". When the chip select signal CS (overline) changes from "1" to "0", the address bits XI and Yj are all "1" and its inverted signal Xi.
Since (overline) and Yj (overline) are all "0", only .phi.W of the word line drive signal becomes "1". Thereby, the memory cells M1 and M2 are connected to the bit lines BL1 and B1, respectively.
L3 and each bit line pair BL1 to BL4
Causes a voltage difference. On the other hand, when a certain period of time has elapsed after the selection by the chip select signal CS (over line), the sense amplifier drive signal φS becomes “1” and the sense amplifiers 901 and 90
3 are activated, and these voltage differences are further amplified.

Since all the address bits Yj are "1", only φY of the column switch drive signal is "1".
And the voltage difference between the bit line pairs BL1, BL2 and BL3, BL4 is changed via the column switches 902, 904 to the partial I / O lines IO1, IO1B and IO2, IO2B, respectively.
Is transmitted to Since φIR is "1", IO of these partial I / O line pairs is connected to IO and IOB.
2, a partial I / O line pair of IO2B.

[0008]

In a conventional semiconductor memory device, a memory cell and a bit line are connected by selecting a word line, and the voltage between a pair of bit lines, that is, the level of an input signal to the sense amplifier, is increased in all sense amplifiers. Almost equal. Therefore, the accessed data arrives at the sense amplifier almost simultaneously with the other data read at the same time, and amplification is started. However, of the amplified data, only specific data is accessed, and the technical idea of treating this specific data separately from other data has not been adopted in the conventional example. Therefore, focusing only on the accessed data, signal propagation on the bit line has not yet been performed at a sufficient speed, and in particular, the increase in the number of bit line pairs increases the use for parasitic between adjacent bit line lines. As a result, the delay of the accessed data increases, and the power consumption also increases.

[0009]

The gist of the present invention is that a plurality of memory cells arranged in a matrix in a row direction and a column direction and the memory cells in the row direction of the plurality of memory cells are simultaneously selected. A memory cell array comprising a plurality of word lines and a plurality of first and second digit lines respectively connected to the memory cells in the column direction of the plurality of memory cells, and for reading data from the selected memory cells; , A plurality of first sense amplifiers and a second sense amplifier for respectively amplifying signals of the plurality of first digit lines and the second digit lines, wherein the plurality of memory cells and the word lines are provided. Are divided so that the number of memory cells connected to each of the digit lines is substantially equal to each other, and each of the digit lines is cut off at substantially the center so that the first and second memory cells are separated.
And a first transistor which is turned on and off by a first switch signal is provided between the separated digit lines of the respective first digit lines, and a first transistor of each of the second digit lines is provided. A second transistor which is turned on and off by a second switch signal is provided between the separated digit lines, and the first transistors corresponding to the respective digit lines of the first group of the respective first digit lines are provided. A third transistor which is turned on / off by a first data transfer signal is provided between each of the second digit lines and a corresponding one of the first digit lines of the first group of the second digit lines. A fourth transistor which is turned on and off by a second data transfer signal is provided between the first digit line and each digit line of the second group of the first digit lines. A fifth transistor which is turned on and off by the second data transfer signal is provided between the second digit line and a corresponding second sense amplifier, and each digit of a second group of the second digit line is provided. In a semiconductor memory device provided with sixth transistors that are turned on and off by the first data transfer signal between a line and a corresponding second sense amplifier, respectively, When reading data from a memory cell connected to the first digit line, the first, fourth, and fifth transistors are turned off, and the second, third, and sixth transistors are turned on, and the first group is turned on. When reading data from a memory cell connected to the second digit line of the flip-flop, the second, third, and sixth transistors are turned off and the first, fourth, and fourth transistors are turned off.
The fifth transistor is turned on, and the first transistor of the second group is turned on.
When reading data from the memory cell connected to the digit line of the second line, the first, third, and sixth transistors are turned off, the second, fourth, and fifth transistors are turned on, and the second group is turned on. When reading data from a memory cell connected to the second digit line of the second
Turning off the fifth transistor, and setting the first, third, sixth
Is to control the levels of the first and second switch signals and the first to fourth data transfer signals so as to turn on the transistor.

[0010]

When the address information is supplied and the memory cell to be accessed is determined, the control circuit sets the bit line for transmitting the data bit read from the accessed memory cell to the switch of the first switch group. By selectively opening and closing, one partial bit line is separated from the other partial bit line, and the signal amount on the partial bit line transmitting data bits is increased.

[0011]

Next, an embodiment of a semiconductor memory device according to the present invention will be described with reference to the drawings.

FIG. 1 shows a memory cell array block 100 of a semiconductor memory device according to an embodiment of the present invention, sense amplifiers 101 and 102, and partial I / O lines IO1, IO1B, I.
FIG. 3 is a circuit diagram showing the periphery of O2 and IO2B. FIG. 2 shows a partial I / O line IO1 to IO2B and an I / O line changeover switch 1.
3 and FIG. 7 are circuit diagrams of a control circuit 105 for generating the control signals shown in FIG. 1 and FIG.

As shown in FIG. 1, the semiconductor memory device has a pair of bit lines BL1 to BL4 and sense amplifiers 101 and 102 arranged at both ends of the bit line. Switch Q which is constituted by a MOS transistor and is controlled by control signals φc1 and φc2.
It is divided by D1 to QD2. Here, the switches QD1 to QD2 responding to the control signal φc1 will be described. The switch QD1 is provided between the bit lines BL1L and BL1R, the switch QD2 is provided between the bit lines BL2L and BL2R, The switch QD3 is provided between the bit lines BL3L and BL3R, and the switch QD4 is provided between the bit lines BL4L and BL4R. Each of the bit lines BL1 to BL4 is connected to the partial bit line BL1.
It is divided into L-BL4L and BL1R-BL4R. Each of the partial bit lines BL1L to BL4L, BL1R to BL
4R and the sense amplifiers 101 and 102, a switch QC1L controlled by both control signals φD1 and φD2
To QC4L, QC1R to QC4R.

Here, the switch to which the control signal φD1 is input will be described. The switch QC1R is connected to the partial bit line BL.
1R, switch QC2R to partial bit line BL2, switch QC3L to partial bit line BL3L, switch
C4L is provided corresponding to partial bit line BL4L, and exists between partial bit lines BL1R to BL4R and sense amplifier 102.

Similarly, for control signal φD2, switch QC3R is connected to partial bit line BL3R and switch QC4R
Corresponds to the partial bit line BL4R, the switch QC1L corresponds to the partial bit line BL1L, and the switch QC2L corresponds to the partial bit line BC2L, and connects the partial bit lines BL1L to BL4L to the sense amplifier 101. Therefore,
Partial bit lines BL1L to BL4L, BL1R to BL4R
Are the switches QC1R to QC4R, QC1
L to QC4L, sense amplifier drive signals φSR, φSR
Are input to the sense amplifiers 101 and 102 which are activated by the column switches 106 and 107 which are controlled by the column switch drive signals φYR and φYL.
A signal is transmitted to the / O line pair IO1, IO1B or IO2, IO2B.

The partial I / O line pairs I / O1 to IO2B are shown in FIG.
As shown in (1), the signals are selectively connected to the I / O line pair IO, IOB via the I / O changeover switches 103, 104 by the control signals φIL, φIR.

The memory cell array block 100 shown in FIG. 1 has four bit lines BL1 to BL4, two word lines WL and WR driven by a drive signal φWL and two word lines WL and WR driven by a drive signal φWR. , Word line WL and partial bit line B
The memory cell M1L, which exists at the intersection of L1L and BL3L,
M2L, word line WR and partial bit lines BL1R and BL
Although only the memory cells M1R and M2R existing at the intersection of the 3Rs are shown, it is to be noted that these are merely a part.

The above control signals and drive signals are shown in FIGS.
Are generated by the control circuit 105 indicated by. In the following, description will be made in order. First, as shown in FIG. 3, address signals Xj and Yj are inverted signals Xi (overline) and Yj.
Address information together with the address line
It is generated by the AND circuit 110 in response to the chip select signal CS (over line) from i and Aj. AND circuits 111 and 11 to which the signals X0 to Xm generated in this manner and their inverted signals X0 (overline) and Xm (overline) are input.
2, the word line drive signals φWR and φWL are generated. In the case of FIG. 3, an AND circuit 111 that receives signals X0 to Xm and generates a word line drive signal φWR, and an AND circuit that receives signals X0 (overline) and X1 to Xm and generates a word line drive signal φWL Only 112 is described. The column switch drive signal φY is generated by an AND circuit or the like to which the remaining bits Y1 to Yn excluding the Y01 bit and their inverted signals are input. In the case of FIG.
, And only the AND circuit 113 that generates the column switch drive signal φY is described.

FIG. 4 shows AND circuits 114 and 115 for generating control signals φL and φR in response to an address signal Y0 not used for generating the column switch drive signal φY and its inverted signal Y0 (overline). Inverters 116 to 118 and OR circuit 11 shown in FIG.
9, 120, AND circuits 121 and 122 receive sense amplifier drive signals φSL and φSR, AND gates 123 and 124 supply column switch drive signals φYL and φYR,
5, 126 generate control signals .phi.c1 and .phi.c2 for switches for separating bit lines into partial bit lines.

FIG. 6 shows switches QC1L to QC4L, QC1R to SQ4L which are present between sense amplifiers 101 and 102 and partial bit lines BL1L to BL4L, BL1R to BL4R.
AND circuits 127 to 130 for generating signals φD1 and φD2 for controlling QC4R, OR circuit 131, inverter 132
To 134. In FIG. 6, the value at point A is determined by the exclusive OR of two input values X0 and Y0.

FIG. 7 shows an inverter 135 for generating control signals φIL and φIR of the I / O switch shown in FIG. 2 and AND circuits 136 and 137.

Next, the operation of this embodiment will be described with reference to the waveform diagram of FIG. In the following description, it is assumed that all the address information of the address input terminal is "1". First, the chip select signal CS (overhead line) in FIG.
To "0", the signals Xi and Yj are all "1",
The inverted signals Xi (overline) and Yj (overline) are all "0".
Becomes

At this time, since the point A in FIG. 6 is in the state of "0", the control signal φD2 changes from "1" to "0" while the control signal φD2 remains "1". Therefore, the partial bit lines BL1R and BL2R in FIG. 1 are disconnected from the sense amplifier 102, and the partial bit lines BL3L and BL4L are disconnected from the sense amplifier 101.

Next, the control signal φR in FIG. 4 becomes “1” and the control signal φc2 in FIG. 5 becomes “0”. However, since the control signal φc1 remains in the “1” state, the partial bit lines BL3L and BL3R and BL4L and BL4R are separated by the N-channel MOS transistors QD3 and QD4.

Thereafter, X0 to Xm in FIG. 3 are all "1".
Therefore, only the word drive signal φWL becomes “1”, the word line WR is driven, and the memory cells M1R and M2R are connected to the partial bit lines BL1R and BL3R, respectively. In general, the voltage difference obtained between a pair of bit lines is determined by the ratio of the total capacity of a bit line to the capacity of a memory cell. Therefore, the voltage difference obtained between BL3R and BL4R where a partial bit line pair is separated is Are the partial bit line pairs BL1L and BL2L,
The value is larger than the voltage difference obtained between BL1R and BL2R. Therefore, a voltage difference larger than that of sense amplifier 101 is input to sense amplifier 102 driven by sense amplifier drive signal φSR, and sense amplifier 102 performs differential amplification at a higher speed than sense amplifier 101. The control signals φSL and φSR in FIG. 5 are configured so that the control signal φL becomes “1” after the control signal φR becomes “1”. That is, in this example, the control signal φ
SR becomes “1” before the control signal φSL, and drives the sense amplifier 102 before the sense amplifier 101. Similarly, transmission of a signal to the partial I / O line can start earlier when the sense amplifier operates first, so that the control signal φYR becomes “1” before φYL.

The I / O switch 103 shown in FIG.
Since the control signal φIR of FIG. 7 becomes “1” at 104, the partial I / O line pair IO2, IO2B and the I / O line pair IO, IO
B is connected.

The case where the address information of the address input terminal is all "1", that is, the case where the memory cell M2R of FIG. 1 is accessed has been described. Similarly, when only the bit Y0 is "0" and all others are "1", the data of the memory cell M1R in FIG. 1 is accessed, and the I / O is transmitted via the partial I / O line pair IO2, IO2B. The signal is transmitted to the line pairs IO and IOB. When the bit X0 is "0" and all others are "1", the data of the memory cell M2L is stored in the partial I / O line pair IO1, IO1.
Transmitted to I / O line pair IO, IOB via B, bits X0 and Y0 are "0", and all others are "1".
In the case of, the data of the memory cell M1L is transmitted to the I / O line pair IO, IOB via the partial I / O line pair IO1, IO1B.

[0028]

As described above, according to the present invention, the length of the bit line to which the memory cell to be accessed is connected can be reduced, and the amount of signals input to the sense amplifier can be increased. And the data in the memory cell can be read at high speed. In addition, since the bit line capacity to be charged and discharged is reduced, there is an effect that the operation current consumption of the entire memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a memory cell array of a semiconductor memory device of the present invention.

FIG. 2 is a block diagram showing partial I / O line switching shown in FIG.

FIG. 3 is a logic circuit diagram for generating each control signal in FIGS. 1 and 2;

FIG. 4 is a logic circuit diagram for generating each control signal in FIGS. 1 and 2;

FIG. 5 is a logic circuit diagram for generating each control signal in FIGS. 1 and 2;

FIG. 6 is a logic circuit diagram for generating each control signal in FIGS. 1 and 2;

FIG. 7 is a logic circuit diagram for generating each control signal in FIGS. 1 and 2;

FIG. 8 is a time chart.

FIG. 9 is a memory cell array block diagram of a conventional semiconductor memory device.

FIG. 10 is a block diagram showing switching of the partial I / O line shown in FIG. 9;

FIG. 11 is a logic circuit diagram for generating each control signal in FIGS. 9 and 10;

FIG. 12 is a logic circuit diagram for generating each control signal in FIGS. 9 and 10;

[Explanation of symbols]

M1L, M1R, M2L, M2R, M1, M2 Memory cells BL1L, BL1R, BL2L, BL2R, BL3L,
BL3R, BL4L, BL4R Partial bit lines BL1, BL2, BL3, BL4 Bit lines IO1, IO1B, IO2, IO2B Partial I / O lines IO, IOB I / O lines QC1L, QD1, QC1R, QC2L, QD2, QC
2R, QC3L, QD3, QC3R, QC4L, QD
4, QC4R MOS N channel transistor

Claims (2)

(57) [Claims] A plurality of memory cells arranged in a matrix in a row direction and a column direction; a plurality of word lines for simultaneously selecting a plurality of memory cells in a row direction of the plurality of memory cells; A memory cell array including a plurality of first and second digit lines connected to memory cells in a column direction of the plurality of memory cells, and reading data from the memory cells in a selected state; There are a plurality of first sense amplifiers and a second sense amplifier for respectively amplifying signals of the second digit lines, and the plurality of memory cells and word lines are connected to the respective digit lines. The number of memory cells is divided so as to be substantially the same, and the respective digit lines are separated at substantially the center to form first and second groups, and the respective first digit lines are separated. A first transistor that is turned on and off by a first switch signal is provided between the separated digit lines, and is turned on and off by a second switch signal between the separated digit lines of the second digit lines. And a second transistor, which is turned on by a first data transfer signal between each digit line of the first group of each first digit line and the corresponding first sense amplifier. , A third transistor to be turned off, and a second data transfer signal between each digit line of the first group of each second digit line and the corresponding first sense amplifier. And a fourth transistor which is turned on and off by the second sense amplifier between each digit line of the second group of each first digit line and the corresponding second sense amplifier. A fifth transistor which is turned on and off by a second data transfer signal, and is provided between each digit line of the second group of the second digit lines and the corresponding second sense amplifier. In a semiconductor memory device provided with a sixth transistor that is turned on and off by the first data transfer signal,
When reading data from the memory cells connected to the first digit line of the first group, the first, fourth,
When the fifth transistor is turned off and the second, third, and sixth transistors are turned on and data is read from the memory cell connected to the second digit line of the first group, the second , The third and sixth transistors are turned off, and the first, fourth and fifth transistors are turned on,
When reading data from the memory cells connected to the first digit line of the second group, the first, third and sixth data are read out.
The second transistor is turned off and the second, fourth, and fifth transistors are turned on to read data from the memory cell connected to the second digit line of the second group. The levels of the first and second switch signals and the first to fourth data transfer signals are set so that the fourth and fifth transistors are turned off and the first, third and sixth transistors are turned on. A semiconductor memory device characterized by controlling. 2. The operation start time of the first and second sense amplifiers is calculated from the memory cells of the first group.
When reading data, the first amplifier is faster than the second amplifier, and when reading data from the memory cells of the second group, the second amplifier is faster than the first amplifier. The semiconductor memory device according to claim 1.