JPH037139B2 - - Google Patents

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Publication number
JPH037139B2
JPH037139B2 JP15981383A JP15981383A JPH037139B2 JP H037139 B2 JPH037139 B2 JP H037139B2 JP 15981383 A JP15981383 A JP 15981383A JP 15981383 A JP15981383 A JP 15981383A JP H037139 B2 JPH037139 B2 JP H037139B2
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JP
Japan
Prior art keywords
semiconductor
layer
solid layer
type
solid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP15981383A
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Japanese (ja)
Other versions
JPS6052067A (en
Inventor
Toshio Baba
Takashi Mizutani
Masaki Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP58159813A priority Critical patent/JPS6052067A/en
Priority to DE8484304300T priority patent/DE3480631D1/en
Priority to EP84304300A priority patent/EP0133342B1/en
Priority to US06/624,333 priority patent/US4695857A/en
Publication of JPS6052067A publication Critical patent/JPS6052067A/en
Priority to US07/043,046 priority patent/US4792832A/en
Publication of JPH037139B2 publication Critical patent/JPH037139B2/ja
Granted legal-status Critical Current

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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843—Source or drain regions of field-effect devices
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/737—Hetero-junction transistors
    • H01L29/7371—Vertical transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236—Superlattices; Multiple quantum well structures
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    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035236—Superlattices; Multiple quantum well structures
    • H01L31/035254—Superlattices; Multiple quantum well structures including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table, e.g. Si-SiGe superlattices
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    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/32—Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
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    • H01S5/00—Semiconductor lasers
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    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
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    • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
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    • H01S5/00—Semiconductor lasers
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    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
    • H01S5/347—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIBVI compounds, e.g. ZnCdSe- laser

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Description

【発明の詳細な説明】 本発明は禁止帯幅が大きなＰ型半導体を実現で
きる超格子の構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a superlattice structure capable of realizing a P-type semiconductor with a large forbidden band width.

従来の化合物半導体への不純物のドーピング方
法は、SiやGeの単元素からなる元素半導体への
ドーピングと同様に、一様に化合物半導体中に不
純物を含有させるものである。GaAs、InPのよ
うな禁止帯幅が2.0eV以下の化合物半導体では、
このようなＰ型不純物を一様に分布させた構造に
よつても容易にＰ型半導体を得ることができる
が、ZnSe、CdSeといつた−半導体に代表さ
れる禁止帯幅が2.0eV以上のワイドギヤツプ化合
物半導体では、従来構造ではＰ型半導体が得られ
ないものが多い。 Conventional methods for doping impurities into compound semiconductors uniformly incorporate impurities into the compound semiconductor, similar to doping into elemental semiconductors made of single elements such as Si or Ge. In compound semiconductors such as GaAs and InP with a forbidden band width of 2.0 eV or less,
Although it is possible to easily obtain a P-type semiconductor with such a structure in which P-type impurities are uniformly distributed, it is possible to easily obtain a P-type semiconductor with a structure in which the P-type impurity is uniformly distributed. In many wide-gap compound semiconductors, P-type semiconductors cannot be obtained with conventional structures.

従来のＰ型不純物をドーピングした化合物半導
体の構造について図面を用いて説明する。 The structure of a conventional compound semiconductor doped with a P-type impurity will be explained with reference to the drawings.

第１図は従来のＰ型不純物をドーピングした化
合物半導体の概略断面図である。１は半導体基
板、２はＰ型不純物、３はＰ型不純物２を均一に
含有し半導体基板１の上に形成した化合物半導体
層である。 FIG. 1 is a schematic cross-sectional view of a conventional compound semiconductor doped with P-type impurities. 1 is a semiconductor substrate, 2 is a P-type impurity, and 3 is a compound semiconductor layer uniformly containing the P-type impurity 2 and formed on the semiconductor substrate 1.

従来構造ではＰ型が得られない禁止帯幅の大き
な半導体の例としてZnSeがあり、このZnSe中へ
のAuのドーピングを説明すると次のようになる。
分子線エピタキシ（MBE）法により基板温度400
℃とし、Zn位置に置換すればＰ型不純物として
働くと考えられるAuを１×1018cm-3含有する
ZnSeを成長させても、ｎ型のZnSeしか得られな
い。この理由は、添加不純物に応じてZnSe内に
固有欠陥が生じ、自己補償がなされるためであ
る。したがつて、自己補償効果のあるZnSeでは
他の成長方法や他のＰ型不純物を用いても同様に
Ｐ型半導体は得られない。 ZnSe is an example of a semiconductor with a large forbidden band width in which a P-type cannot be obtained with a conventional structure.The doping of Au into ZnSe is explained as follows.
Substrate temperature of 400℃ using molecular beam epitaxy (MBE) method
℃, and contains 1×10 18 cm -3 of Au, which is thought to act as a P-type impurity if substituted at the Zn position.
Even if ZnSe is grown, only n-type ZnSe can be obtained. The reason for this is that inherent defects occur in ZnSe depending on the added impurities, and self-compensation occurs. Therefore, with ZnSe, which has a self-compensating effect, a P-type semiconductor cannot be obtained even if other growth methods or other P-type impurities are used.

この解決手段としては従来構造とは異なり、Ｐ
型不純物と自己補償効果のある半導体とを空間的
に分離する新しい構造が必要である。 As a solution to this problem, unlike the conventional structure, P
New structures are needed that spatially separate type impurities and self-compensating semiconductors.

本発明の目的は、かかる従来構造の持つ欠点を
除去し、禁止帯幅が大きなＰ型半導体が実現でき
る超格子の構造を提供することにある。 An object of the present invention is to provide a superlattice structure that eliminates the drawbacks of the conventional structure and can realize a P-type semiconductor with a large forbidden band width.

本発明の超格子の構造は、正孔波長以下の厚さ
を有する第１の固体層と、該第１の固体層より電
子親和力と禁止帯幅との和が大きく第１の固体層
中の正孔がトンネル可能な厚さを有する第２の固
体層の少なくとも２種類の固体層を交互に積層し
た積層構造を持ち、Ｐ型不純物が第１の固体層だ
けに含有されていることを特徴とする。 The structure of the superlattice of the present invention includes a first solid layer having a thickness equal to or less than the hole wavelength; It has a laminated structure in which at least two types of solid layers are alternately laminated, the second solid layer having a thickness that allows hole tunneling, and the P-type impurity is contained only in the first solid layer. shall be.

一般に電子親和力と禁止帯幅との和が異なる半
導体の積層構造において、電子親和力と禁止帯幅
との和が小さな半導体の厚さが正孔波長以下にな
ると量子効果が顕著になり、この半導体内には新
たなエネルギ準位（量子化準位）が形成される。
さらに、電子親和力と禁止帯幅との和が大きな半
導体の厚さがこの半導体中を量子化準位の正孔が
トンネルできるほどに薄くなると、正孔は量子化
準位において積層構造の膜中を自由に運動できる
ようになる。本発明の構造はこの条件を満たして
いるため、第１の固体層から発生する正孔は量子
化準位において積層構造全体に広がる。したがつ
て、第１の固体層がＰ型半導体であれば、積層構
造全体もＰ型半導体とすることが可能となる。 In general, in the stacked structure of semiconductors with different sums of electron affinities and bandgap widths, when the thickness of the semiconductor with a small sum of electron affinities and bandgap widths becomes less than the hole wavelength, quantum effects become noticeable, A new energy level (quantization level) is formed.
Furthermore, when the thickness of a semiconductor with a large sum of electron affinity and forbidden band width becomes thin enough to allow holes at the quantization level to tunnel through the semiconductor, the holes enter the layered film at the quantization level. You will be able to exercise freely. Since the structure of the present invention satisfies this condition, holes generated from the first solid layer spread throughout the stacked structure at the quantization level. Therefore, if the first solid layer is a P-type semiconductor, the entire stacked structure can also be made of a P-type semiconductor.

以下、本発明について実施例を示す図面を参照
して詳細に説明する。 EMBODIMENT OF THE INVENTION Hereinafter, the present invention will be described in detail with reference to drawings showing embodiments.

第２図は本発明の第１の実施例を示した模式的
断面図である。第２図において第１図と同じ番号
のものは第１図と同等物で同一機能を果すもので
あり。４はＰ型不純物２を含有し正孔波長以下の
厚さを有する第１の固体層、５は該第１の固体層
４より電子親和力と禁止帯幅との和が大きく、第
１の固体層４中の正孔がトンネル可能な厚さを有
する第２の固体層である。第１の固体層４と第２
の固体層５とが交互に積層し、積層構造を形成し
ている。 FIG. 2 is a schematic cross-sectional view showing the first embodiment of the present invention. Components in FIG. 2 with the same numbers as in FIG. 1 are equivalent to those in FIG. 1 and perform the same functions. 4 is a first solid layer containing a P-type impurity 2 and having a thickness equal to or less than the hole wavelength; 5 is a first solid layer having a larger sum of electron affinity and forbidden band width than the first solid layer 4; A second solid layer having a thickness through which holes in layer 4 can tunnel. The first solid layer 4 and the second solid layer 4
The solid layers 5 are alternately stacked to form a stacked structure.

本実施例を、半導体基板１としてGaAs、不純
物２としてBe、第１の固体層４として厚さ５Å
のGaAs、第２の固体層５として厚さ15ÅのZnSe
を用いて説明すると次のようになる。 In this example, GaAs is used as the semiconductor substrate 1, Be is used as the impurity 2, and the thickness of the first solid layer 4 is 5 Å.
GaAs, 15 Å thick ZnSe as second solid layer 5
The following is an explanation using .

GaAs中での室温におけるBeの活性率はほぼ
100％であるので、５ÅのGaAs中にはドープし
たBeのほとんどが活性化してBe量とほぼ同量の
正孔はGaAsの充満帯端よる0.7eV低い量子化準
位においてこの膜全体に広がる。GaAsとZnSeの
電子親和力はほとんど等しいため、電子の量子化
準位はほとんど現われない。したがつて、この膜
の等価的な禁止帯幅は2.1eVとなる。 The activity rate of Be in GaAs at room temperature is approximately
Since it is 100%, most of the Be doped in the 5 Å GaAs is activated, and the holes, which are almost the same amount as the amount of Be, spread throughout the film at a quantization level 0.7 eV lower than the edge of the GaAs filling band. . Since the electron affinities of GaAs and ZnSe are almost equal, almost no electron quantization level appears. Therefore, the equivalent forbidden band width of this film is 2.1 eV.

結晶成長方法としてMBEを用い、膜全体の平
均的Be濃度として１×1018cm-3をドーピングした
結果、室温での正孔濃度して１×1018cm-3が得ら
れた。この結果より、禁止帯幅が2.1eVと大きな
半導体であるのにかかわらず、高い正孔濃度を有
するＰ型半導体が得られることがわかる。 Using MBE as a crystal growth method, the film was doped with an average Be concentration of 1×10 18 cm −3 , resulting in a hole concentration of 1×10 18 cm −3 at room temperature. This result shows that a P-type semiconductor with a high hole concentration can be obtained even though the semiconductor has a large forbidden band width of 2.1 eV.

第３図は本発明の第２の実施例を示した模式的
断面図である。第３図において第１、第２図と同
じ番号のものは第１、第２図と同等物で同一機能
を果すものであり、６は不純物２を含有し正孔波
長以下の厚さを有する半導体層、７は該半導体層
６より電子親和力と禁止帯幅との和が大きく半導
体層６中の正孔がトンネル可能に厚さを有する絶
縁体層である。 FIG. 3 is a schematic sectional view showing a second embodiment of the present invention. In Figure 3, the same numbers as in Figures 1 and 2 are equivalent to those in Figures 1 and 2 and have the same function, and 6 contains impurity 2 and has a thickness less than the hole wavelength. The semiconductor layer 7 is an insulating layer that has a larger sum of electron affinity and forbidden band width than the semiconductor layer 6 and has a thickness that allows holes in the semiconductor layer 6 to tunnel.

不純物としてＢ、半導体層６として厚さ５Åの
Si、絶縁体層７として厚さ15ÅのCaF2を用い、
MBE法により本構造を構成した結果、新しい正
孔の量子化準位はSiの充満帯端より0.7eV低くな
り、さらに新しい電子の量子化準位がSiの伝導帯
端より1eV高くなるため、禁止帯幅として2.8eV
が得られた、そして膜全体の平均のＢ濃度として
１×1018cm-3ドープしたのに対し、１×1018cm-3
の正孔濃度が得られた。 B is used as an impurity, and a thickness of 5 Å is used as the semiconductor layer 6.
Using Si, CaF 2 with a thickness of 15 Å as the insulator layer 7,
As a result of constructing this structure using the MBE method, the quantization level of new holes is 0.7 eV lower than the Si filling band edge, and the new electron quantization level is 1 eV higher than the Si conduction band edge. 2.8eV as forbidden band width
was obtained, and the average B concentration of the entire film was doped with 1×10 18 cm −3 , whereas 1×10 18 cm −3
The hole concentration was obtained.

上記の本発明の２つの実施例については、Ｐ型
不純物が第１の固体層全体に含有されているとし
たが、Ｐ型不純物のドーピングを第１を固体層全
体ではなく、第１の固体層のうち第２の固体層と
の界面近傍を除く領域だけとしてもよく、またＰ
型不純物を含有しない第１の固体層がデバイ長以
上の厚さに積層していなければ積層構造の中に存
在しても良い。すなわち積層構造中のすべての第
１の固体層中に不純物が含まれている必要は必ず
しもない。また、積層構造としては２種類の固体
層を交互に積層したものだけしか示さなかつた
が、３種類以上の固体層を積層したものであつて
も、正孔が量子化準位で膜全体に広がる構造であ
れば良く、この構造でもＰ型半導体が得られるこ
とは明らかである。３種類の固体層を積層したも
のの例としては、GaAs／AlAs／ZnSeがあり、
GaAs／ZnSe系よりもさらに禁止帯幅の広いもの
が容易に実現できる。 In the above two embodiments of the present invention, the P-type impurity is contained in the entire first solid layer, but the P-type impurity is doped not in the entire solid layer but in the first solid layer. Only the region of the layer excluding the vicinity of the interface with the second solid layer may be used, and P
The first solid layer containing no type impurities may be present in the stacked structure as long as it is not stacked to a thickness equal to or greater than the Debye length. That is, it is not necessarily necessary that all the first solid layers in the laminated structure contain impurities. In addition, although only two types of solid layers are laminated alternately as a laminated structure, even in a laminated structure of three or more types of solid layers, holes are distributed throughout the film at the quantization level. It is sufficient that the structure is wide, and it is clear that a P-type semiconductor can be obtained even with this structure. An example of a stack of three types of solid layers is GaAs/AlAs/ZnSe.
A device with a wider forbidden band width than the GaAs/ZnSe system can be easily realized.

第１の固体層中に含有するＰ型不純物として
は、第１の固体層がSi、Ge等の元素半導体では
Ｂ、Al、Ga、In、Tl等、GaAs、IsP等の−
化合物半導体では、Be、Mg、Zn、Cd、Ｃ等、
ZnTe、CdTeの−化合物半導体ではAu、
Ag、Cu等であつても良い。 The P-type impurities contained in the first solid layer include B, Al, Ga, In, Tl, etc. when the first solid layer is an elemental semiconductor such as Si or Ge, and -
In compound semiconductors, Be, Mg, Zn, Cd, C, etc.
ZnTe, CdTe - Compound semiconductors include Au,
It may also be Ag, Cu, etc.

本発明の実施例では積層する固体層として格子
整合のとれた半導体または絶縁体について述べた
が、一般に積層構造においては各層の界面におい
て格子不整合によるストレスが緩和されるため、
格子整合のとれてない半導体または絶縁体の積層
構造でも本発明を実現することは可能である。さ
らに、Miscibility Gapに相当する組成
（InGaAsSb、InAsPSb等）で予想される光学的
および電気的特性を有するＰ型半導体も本発明に
より実現することができる。 In the embodiments of the present invention, lattice-matched semiconductors or insulators have been described as the stacked solid layers, but in general, in a stacked structure, stress due to lattice mismatch is alleviated at the interface of each layer.
It is possible to realize the present invention even with a laminated structure of semiconductors or insulators with no lattice matching. Furthermore, a P-type semiconductor having optical and electrical properties expected with a composition corresponding to the Miscibility Gap (InGaAsSb, InAsPSb, etc.) can also be realized by the present invention.

本発明の構造は実施例で示した材料以外のあら
ゆる半導体および絶縁体の組合せに対し適用可能
である。例えば、−化合物半導体間の組合せ
ではZnTe／CdSe、−と−の化合物半導
体の組合せではGaP／ZnS、InP／CdS、その他
の半導体の組合せとしてはCuGaSe2／ZnSe、半
導体と絶縁体の組合せではSi／MgO−Al2O3スピ
ネル化合物、GaP／CaF2などがある。 The structure of the present invention is applicable to all combinations of semiconductors and insulators other than those shown in the examples. For example, ZnTe/CdSe is a combination between - compound semiconductors, GaP/ZnS, InP/CdS is a combination of - and - compound semiconductors, CuGaSe 2 /ZnSe is a combination of other semiconductors, and Si is a combination of a semiconductor and an insulator. /MgO- Al2O3 spinel compound, GaP/ CaF2 , etc.

本発名の構造を得る方法としては、原理にはど
んな結晶成長方法であつても良いが、数Åの膜厚
制御性が必要となるため、MBE法やMOCVD
（Metal Organic Chemical Vapor Deposition）
法が適している。中でもMBE法は原料の入つた
炉から出る分子線をシヤツタの開閉だけで制御で
きるため、遷移層が数Åの急峻な界面を容易に実
現することができ、さらにコンピユータによる自
動制御が容易であるため最も適した方法である。 In principle, any crystal growth method can be used to obtain the structure of this invention, but since film thickness controllability of several angstroms is required, MBE, MOCVD, etc.
(Metal Organic Chemical Vapor Deposition)
law is appropriate. In particular, in the MBE method, the molecular beams emitted from the furnace containing the raw materials can be controlled simply by opening and closing the shutter, so it is easy to create a steep interface with a transition layer of several angstroms, and it is also easy to automatically control using a computer. This is the most suitable method.

本発明により禁止帯幅が広いＰ型半導体を実現
できるので本発明を用いたＰ型半導体により青色
発行の光デバイスや高温での使用な可能なトラン
スポートデバイスが実現できる。 Since the present invention makes it possible to realize a P-type semiconductor with a wide forbidden band width, a blue-emitting optical device and a transport device that can be used at high temperatures can be realized using a P-type semiconductor using the present invention.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来構造のＰ型不純物をドープした半
導体の模式的断面図、第２、第３図は本発明の第
１、第２の実施例を示した模式的断面図である。 １……半導体基板、２……Ｐ型不純物、３……
化合物半導体層、４……第１の半導体層、５……
第２の半導体層、６……半導体層、７……絶縁体
層。 FIG. 1 is a schematic sectional view of a semiconductor doped with a P-type impurity having a conventional structure, and FIGS. 2 and 3 are schematic sectional views showing first and second embodiments of the present invention. 1... Semiconductor substrate, 2... P-type impurity, 3...
Compound semiconductor layer, 4... first semiconductor layer, 5...
Second semiconductor layer, 6... semiconductor layer, 7... insulator layer.

Claims (1)

【特許請求の範囲】[Claims] １ 正孔波長以下の厚さを有する半導体層からな
る第１の固体層と、該第１の固体層より電子親和
力と禁止帯幅との和が大きく第１の固体層中の正
孔がトンネル可能な厚さを有する第２の固体層の
少なくとも２種類の固体層を交互に積層した積層
構造を持ち、Ｐ型不純物が第１の固体層だけに含
有されていることを特徴とする超格子の構造。1. A first solid layer made of a semiconductor layer having a thickness equal to or less than the hole wavelength; A superlattice having a laminated structure in which at least two types of solid layers of the second solid layer having a thickness as high as possible are alternately laminated, and a P-type impurity is contained only in the first solid layer. structure.
JP58159813A 1983-06-24 1983-08-31 Structure of super lattice Granted JPS6052067A (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP58159813A JPS6052067A (en) 1983-08-31 1983-08-31 Structure of super lattice
DE8484304300T DE3480631D1 (en) 1983-06-24 1984-06-25 SEMICONDUCTOR STRUCTURE WITH HIGH GRID DENSITY.
EP84304300A EP0133342B1 (en) 1983-06-24 1984-06-25 A superlattice type semiconductor structure having a high carrier density
US06/624,333 US4695857A (en) 1983-06-24 1984-06-25 Superlattice semiconductor having high carrier density
US07/043,046 US4792832A (en) 1983-06-24 1987-04-24 Superlattice semiconductor having high carrier density

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58159813A JPS6052067A (en) 1983-08-31 1983-08-31 Structure of super lattice

Publications (2)

Publication Number Publication Date
JPS6052067A JPS6052067A (en) 1985-03-23
JPH037139B2 true JPH037139B2 (en) 1991-01-31

Family

ID=15701806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58159813A Granted JPS6052067A (en) 1983-06-24 1983-08-31 Structure of super lattice

Country Status (1)

Country Link
JP (1) JPS6052067A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH077847B2 (en) * 1984-12-17 1995-01-30 株式会社東芝 Semiconductor light emitting element
JPS6294923A (en) * 1985-10-22 1987-05-01 Nec Corp Method of impurity doping for semiconductor material
JP2545785B2 (en) * 1986-02-04 1996-10-23 ソニー株式会社 Compound semiconductor
JP2653471B2 (en) * 1988-05-24 1997-09-17 日本電信電話株式会社 Semiconductor device
JP7406887B2 (en) * 2019-08-07 2023-12-28 キヤノン株式会社 Photoelectric conversion device, radiation imaging system, photoelectric conversion system, mobile object

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742116A (en) * 1980-08-26 1982-03-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor superlattice crystal
JPS57164573A (en) * 1982-02-26 1982-10-09 Hitachi Ltd Semiconductor device
JPS5815892A (en) * 1981-07-17 1983-01-29 松下電器産業株式会社 One-tub type dehydrating washer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5742116A (en) * 1980-08-26 1982-03-09 Nippon Telegr & Teleph Corp <Ntt> Semiconductor superlattice crystal
JPS5815892A (en) * 1981-07-17 1983-01-29 松下電器産業株式会社 One-tub type dehydrating washer
JPS57164573A (en) * 1982-02-26 1982-10-09 Hitachi Ltd Semiconductor device

Also Published As

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