JPH0371052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital rotational position detection device using a resolver, and the present invention relates to a digital rotational position detection device using a resolver.
PLL) is used to convert both phase and frequency into a counter output that corresponds to the output, and subtraction is performed between the output and the counter output that commands the resolver excitation frequency, and the rotational position is detected as a digital quantity.
Hereinafter, a detailed explanation will be given based on the illustrated embodiment.

FIG. 1 is a block diagram of the embodiment, in which the reference oscillator 1
and a first counter that counts this oscillator output and outputs a frequency command to the resolver excitation source.A PLL circuit 3 that generates a counter output synchronized with the resolver output including two rotation position information, the above counter output of the PLL circuit 3 and the first counter The subtractor 4 performs subtraction between the output of the counter 2 and detects the rotational position. The resolver 5 includes an excitation circuit 6 as an excitation source, a two-phase excitation winding 7, and an output winding 8 on the rotating side.
The PLL circuit 3 includes a phase comparator 9 that compares the phases of the second counter output of the feedback signal and the resolver output, a low-pass filter 10, a voltage-controlled oscillator 11, and a second counter 12 that counts the output frequency of this oscillator. Ru.

If the excitation frequency of the resolver 5 is ω, then the two-phase excitation inputs can be expressed as sin ωt and cos ωt, and if the rotational position is θ _n , the resolver output can be expressed as sin (ωt + θ _n ). Resolver excitation input sin ωt, cos
ωt is given by the excitation circuit 6, but the excitation frequency ω is determined from the output of the first counter 2. The resolver output sin(ωt+θ _n ) is converted into a frequency-multiplied synchronization signal via the PLL circuit 3, frequency-divided by the second counter 11, and then subtracted from the first counter output.

In the time chart in Figure 2, the first counter 2
Output S ₁ , second counter 11 output S ₂ of the PLL circuit,
The output S ₃ of the subtracter 4, the output S ₄ from the reference oscillator 1, and the output S ₅ from the voltage controlled oscillator 10 of the PLL circuit.
shows the relationship between That is, the first counter 2 is
The oscillation output _S4 is counted, and each time the counter value reaches a value corresponding to a predetermined excitation frequency ω, it is reset to generate the stepwise sawtooth waveform _S1 shown in the figure. The frequency multiplication PLL circuit 3 uses a phase comparator 8 to determine the phase difference between the resolver output sin (ωt + θ _n ) and the feedback signal output S ₂ of the second counter 11, and passes it through a low-pass filter 9 to a voltage controlled oscillator 10. In addition, a frequency-multiplied oscillation output _S5 is generated to make the phase difference zero, the frequency is divided by the second counter 11, and a step-like sawtooth waveform _S2 synchronized with the resolver output is sent to the subtracter 4. Output. The subtracter 4 subtracts the output S ₁ of the first counter 2 and the output S ₂ of the second counter 11 of the PLL circuit, and captures the frequency deviation of the resolver input/output signal due to rotation as a rotational position for each bit. , producing the output waveform _S3 shown. The subtracter 4 output _S3 is a bit output corresponding to the frequency division ratio of the first and second counters 4 and 11,
For example, if the frequency division ratio is 1/1000, the resolver is 1/1000.
When it rotates 360 degrees, it will output 1000 bits corresponding to the above frequency division ratio. In Figure 3,
The above S ₁ , S ₂ , and S ₃ waveforms are shown in their entirety.
The counter outputs S ₁ and S ₂ are reset and return to zero every time the excitation frequency and resolver output frequency reach one cycle, but the subtraction of these two output waveforms S ₁ and S ₂ is as follows.
This is continued regardless of the above reset, and continues until the frequency division ratio reaches 1000 bits. That is, the output S ₃ of the subtractor 4 is exactly at the time T ₁ shown in the figure.
When 1000 bits are reached, the resolver has rotated 361 degrees, which is one rotation, and it is once reset to return to zero and continues detecting the resolver rotational position in subsequent rotations.

The subtracter output _S3 indicating the resolver rotation position is the second
As is clear from the figure, this is a digital signal that repeatedly contains ripples every time one bit is added, and when this is taken in, it must be done at appropriate timing to remove these ripples N. FIG. 4 shows a block diagram of the embodiment, in which the D flip-flop 12
Using the latch circuit 13, the output _S4 of the reference oscillator 1 is sampled with the output _S5 of the voltage controlled oscillator 10, and the latch output is commanded at the time when the phase difference is reversed by one cycle, and the output _S3 of the subtractor 4 is latched. The S ₃ output waveform is captured at time points t ₁ , t ₂ , t _{3 .} . . in FIG. 2 and output as a rotational position detection signal. That is, 1
It is sampled every time the bit changes, and the ripple N between them is automatically cut off. In addition, FIG. 5 shows a block diagram of another embodiment.
Using an inverter 14 and a latch circuit 15, a latch command is output using the inverted output of the output _S4 of the reference oscillator 1, and the _S3 output waveform is sampled.
In the time chart shown in the figure, timings t ₁ ', t ₂ ', t ₃ ', . . . are the sampling points at this time, and the S ₃ output is taken in and output as a rotational position detection signal. Note that the voltage controlled oscillator 10 is used as a latch command.
A similar effect can be obtained by using the inverted output of the output.

As described above, the present invention is a digital rotational position detection device using a resolver, which uses a PLL circuit to generate a frequency multiplied signal that is phase synchronized with the resolver output, and outputs a second counter output of this frequency multiplied signal and a reference oscillator. The reference signal from the first counter is counted and subtracted from the output of the first counter which outputs the excitation frequency command signal, and the rotational position of each bit of the subtraction result of the first and second counter outputs is output. The rotational position resolution is determined according to the frequency division ratio of the first and second counters, and by adjusting the output frequencies of the reference oscillator and voltage controlled oscillator, it is possible to select an appropriate resolution according to the application, and also to The output waveform contains ripples for each bit, but by selecting an appropriate sampling timing, all of these ripples can be removed, and the rotational position can be detected accurately with the resolution corresponding to the frequency division ratio mentioned above. .

[Brief explanation of drawings]

In the drawings, Fig. 1 is a block diagram of the embodiment, Fig. 2 is a block diagram of the embodiment, and Fig. 2 is a block diagram of the embodiment.
Figure 3 is a time chart for explaining the operation, Figure 4 is a time chart for explaining the operation.
FIG. 5 is a block diagram of an embodiment of ripple removal. 1... Reference oscillator, 2... First counter, 3
...PLL circuit, 4...subtractor, 5...resolver,
8... Phase comparator, 9... Low pass filter, 1
0... Voltage controlled oscillator, 11... Second counter, 12... D flip-flop, 14... Inverter, 13, 15... Latch circuit.

Claims (1)

[Claims] 1. A reference oscillator, a first counter that counts the output of this oscillator and outputs a frequency command to the resolver excitation source, and a second counter that counts the output of the oscillator and outputs a frequency command to the resolver excitation source.
a phase comparator that compares the phases of the counter outputs;
A PLL circuit consisting of a low-pass filter, a voltage controlled oscillator, and a second counter; a subtracter that performs subtraction between the second counter output of this PLL circuit and the first counter output and outputs rotational position information; A digital rotational position detection device using a resolver, characterized in that it is equipped with sampling means for removing ripples from the output of a subtracter. 2. The sampling means is comprised of a flip-flop that outputs a latch command when the phase difference between the reference oscillator output and the voltage-controlled oscillator output is reversed, and a latch circuit that latches the subtracter output in response to this latch command. A digital rotational position detection device using a resolver as described in scope 1. 3. A digital device using a resolver, characterized in that the sampling means is composed of an inverter that outputs a latch command when the reference oscillator output or the voltage controlled oscillator output is inverted, and a latch circuit that latches the subtracter output in accordance with the latch command. type rotation position detection device.