JPS6079221A - Digital-type rotary position detector using resolver - Google Patents

Abstract

PURPOSE:To detect accurately a turning position, by converting a phase-modified resolver output signal into a counter output corresponding to both phase and frequency using a phase-locked loop and performing subtraction between said output and the one commanding the resolver exciting frequency. CONSTITUTION:When an excitation frequency of a resolver 5 is defined as omega, excitation inputs of 2-phase are sin omegat and cos omegat and for a turning position being thetam, the resolver output can be expressed as sin (omegat+thetam). The outputs sin omegat, cos omegat are given by the excitation circuit 6, and the excitation frequency omega is determined by the output of the first counter. Sin (omegat+thetam) of the revolver is converted to a synchronized signal of multiplication by frequency times through a PLL circuit 3 and after division by the second counter 11, a substration is performed between the first counter output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Dinkle-type rotational position detection device using a resolver, and uses a phase-locked loop (hereinafter referred to as TI'LL) to transmit a phase-modulated resolver output signal.
It converts into a counter output corresponding to both the phase and frequency, and subtracts it by 9 with the counter output that commands the resolver excitation frequency, and detects the rotational position with the digital camera. A detailed description will be given based on the illustrated embodiment.

FIG. 1 is a block diagram of the embodiment.1. I, l; bef (oscillator (1) and a first counter (2) that counts the oscillator output and outputs a frequency command to the resolver excitation source; PLL that generates a counter output synchronized with the resolver output including rotational position information; a circuit ('3), a subtracter (4) that performs subtraction between the counter output of the PLL circuit (3) and the output of the first counter (2) to detect the rotational position, and a 0 resolver configured as follows. (5) comes from the excitation circuit (6) of the excitation source, the two-phase excitation winding (7), and the output winding (8) on the one-rotation side.
Lf, the circuit (3) includes a phase comparator (9) that compares the phase of the second counter output of the feedback signal and the resolver output.
), low-pass filter (10), [pressure-controlled oscillator (1)
1') A second counter (12) that counts the oscillator output frequency.

If the excitation frequency of the resolver (5) is ω, then the two-phase excitation input is join act , cosωL, and if the rotational position is θm, the resolver output is min'(ωt
0 resolver excitation input ginω(, respectively represented by -1-(7m).

cios 1. It is given by the excitation circuit (6), but the excitation frequency ω is determined from the output of the first counter (2). The resolver output sin (ωt+θm) is P
After the frequency multiplication synchronization signal via the LL circuit <3>*, the first
Deenergization is performed between the counter output and the counter output.

Second @ time chart Ic, first counter (2) output S1. Second counter (11) output S2 of PLL circuit
．． Subtractor (4) output S3. Output S4 from reference oscillator (1). Furthermore, the relationship between the output S51 from the voltage controlled oscillator (10) of the PLL circuit is shown. That is, the first counter (2) A counts the oscillation output S4, and is reset every time the counter value reaches a value corresponding to a predetermined excitation frequency ω, and generates the step-like sawtooth waveform S1 shown in the figure. generate. The frequency multiplication PLL circuit (3) is a phase comparator (8)
Then, the phase difference between the resolver output sin (ωt + θm) and the second counter (11) output S2 of the signal is determined, and it is applied to the voltage controlled oscillator (10) via the low-pass filter (9), and the above Oscillation output of frequency multiplication with zero phase difference, generation of force S5, second counter (11)
, and outputs a step-like sawtooth waveform S2 in synchronization with the resolver output to the subtracter (4). The subtracter (4) outputs the first counter (.2) output S1. Then, the output S2 of the second counter (11) of the PLL circuit is decremented, and the frequency shift of the input/output signal due to rotation is captured as a rotational position for each bit, and the output waveform S3 shown in the figure is generated.

The subtracter (4) output S3 is the first . Second counter (4)
, (11) is the bit output corresponding to the division ratio.For example, if the division ratio is 1/1000, the resolver is
When rotated 360 degrees, 1 corresponding to the above frequency division ratio
000 bits will be output. In Figure 3, the above S
1182183 waveform is shown in its entirety. The second counter outputs S, , S2 are reset and return to zero each time the excitation frequency and resolver output frequency reach one cycle, but these two output waveforms S1. The subtraction in S2 is continued regardless of the above-mentioned reset, and is performed until the frequency division ratio reaches 1000 bits. That is, the output S3 of the subtracter (4) reaches exactly 1000 bits at the time T1 shown in the figure, and the resolver has rotated 360 degrees for one rotation. As is clear from FIG. 2, the subtracter output S3 indicating the C resolver rotation position, which continues detection of the resolver rotation position, is equal to the doubling pressure applied by 1 pin, and the double pressure applied.

This is a digital signal that repeatedly contains ripples N, and its capture must be done at appropriate timing to remove these ripples N. FIG. 4 shows a block diagram of the embodiment, which shows the D flip 70 tube (12) and the latch circuit (13).
), sample the reference oscillator (1) output SA with the voltage controlled oscillator (10) output S5, command the latch output at the time when the phase difference is reversed by one cycle, and latch the energy reducer (4) output S3. The S3 output waveform is 1 in Figure 2.
1, 12, 13, etc., and output as a rotational position detection signal. In other words, every time one bit changes, the ripple N is sampled and the ripple N during that time is automatically cut off. Fig. 5 shows a block diagram of another embodiment. A latch circuit (15) is used to output a latch command with the inverted output of the reference oscillator (1) output S, and the output waveform of S is sampled.
, r, t3/... The glue timing is the sampling point at this time, and the S3 output is taken in and output as a rotational position detection signal. Note that the same effect can be obtained by using the inverted output of the voltage controlled oscillator (10) as the latch command.

As described above, the present invention uses a resolver-based noti-digital rotational position detection device, generates a frequency multiplied signal that is phase-synchronized with the resolver output using a PLL circuit, and outputs the second counter output of this frequency multiplied signal and a base thread oscillator. The first counter counts the reference signal from the first counter and outputs the excitation frequency command signal. It outputs the second counter output range and the rotational position for each bit of the result. The rotational position resolution is determined according to the frequency division ratio of the second counter, and by adjusting the output frequency of the reference oscillator and voltage controlled oscillator, it is possible to select the appropriate resolution according to the application, and the output waveform of the energy reduction result. Although each bit contains ripples, all of these ripples can be removed by selecting an appropriate sampling timing, and the rotational position can be accurately detected with a resolution corresponding to the frequency division ratio.

[Brief explanation of drawings]

In the drawings, FIG. 1 is a block diagram of an embodiment, and FIG. 2 is a block diagram of an embodiment. Figure 3 is a time chart explaining the operation, Figure 4 24 yen 5
The figure is a block diagram of an embodiment of ripple removal. (1)... Reference oscillator (2)... First counter (3)... 1) L L circuit (4)... Decreasing Q, unit (5) Resolver (8)... Phase comparator ( 9) Low-pass filter (10) Voltage controlled oscillator (11) Second counter (12) -1) Flip-flop (14) Inverter (13), (t5) Latch circuit applicant Shinko Electric Co., Ltd. Agent Patent Attorney Sai # Haruya Procedural Amendment (Method) 59.2.14 1. Display of case 1988 Patent Application No. 188032 2
Name of the invention Digital rotational position detection device 3 using a resolver, relationship with the case of the person making the correction %Drinking applicant Representative Shigeru Inomata Telephone Tokyo (274) 1111 (main representative) 4 representatives 〒516

Claims (1)

[Claims] 1. A first counter that counts the reference oscillator output and outputs a frequency command to the resolver excitation source, and a phase comparison between the resolver output and the second counter output of the feed pulse signal. with a phase comparator. A PLL circuit consisting of a low-pass filter, a voltage controlled oscillator, and a second counter, a reducer that subtracts the second counter output of the PLL circuit and the first counter output and outputs rotational position information. . A digital rotational position detection device using a resolver, characterized by comprising sampling means for removing ripples from the output of the subtracter. 2. The sampling means is configured to output a latch command when the phase difference between the reference oscillator output and the voltage controlled oscillator output is reversed.
The flop and this latch command cause the output of the Q reducer to be
A special gamma feature characterized by a latch circuit that locks
``Digital rotational position detection device using a resolver according to claim 1. 3. The sampling means is an inverter that outputs a latch command when the output of the reference oscillator or the output of the voltage controlled oscillator is inverted, and A digital rotational position detection device using a resolver, characterized by comprising a latch circuit that latches the output of a subtracter.