JPS5912215B2 - Phase-locked closed circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase-locked closed circuit (hereinafter referred to as PLL), and particularly to a PLL suitable for use in a demodulation circuit.

Conventionally, in order to reproduce a transmission signal subjected to carrier wave suppression such as a vestigial sideband (VSB) transmission system, a demodulator uses PLL technology to generate a signal synchronized in frequency and phase with the carrier wave.

FIG. 1 shows a typical configuration example of such a PLL circuit.

The phase comparator 1 receives two AC input signals (f s , f c
) acts as a kind of multiplier for the detected phase difference (
A voltage Vd proportional to the amount of change over time of θS-θC) is output.

Further, the voltage controlled oscillator 4 (hereinafter referred to as vCO) is controlled by the input voltage Vd, and operates to bring t'c closer to f8.

Therefore, finally f S = f e and the system becomes stable.

However, since circuits with this type of configuration handle analog signals, (1) there are many adjustment points, (2) they are susceptible to noise, (3) they are susceptible to aging, and (4) fs
There was a drawback that the response time was long due to the transient characteristics until reaching = fc.

Some methods have digitized the phase comparator as a means to alleviate these drawbacks, but in any case, in the end, the VC
Since the output frequency changes depending on the input voltage to VCO, the output frequency changes due to fluctuations in the power supply voltage, and when there is no input signal, the output is determined by the free running frequency of vCO, so various auxiliary circuits are required. There was a drawback.

The present invention attempts to completely digitalize the PLL by eliminating vCO, solve the above-mentioned drawbacks of the conventional technology at once, and provide a PLL with excellent stability, reliability, and high productivity. .

A block diagram of a circuit according to the invention is shown in FIG.

Now, when the input fs enters the digital phase comparator 8, the third
As shown in the figure, the output f from frequency divider 7.

lag signal fgx or lead signal f according to the phase difference with
g2 is output.

FIG. 4 shows an example of a well-known circuit for generating an input signal f'o to the frequency divider 7.

If the input fstfe to the phase comparator 8 is in the same phase and there is no output fg1.1g2 from it, the reference pulse f.

is output as is as f′o, but the advance signal f
When g2 comes, AND gate G1 is closed.

At this time, since the AND gate G2 is also closed, the output f'o of the phase matching device 6 is stopped.

Therefore, the output f of the frequency divider 7 is
.

The phase of is delayed. On the other hand, when the delay signal fg1 comes, both gates G1 and G2 open, so that the output f of the phase matching device 6 is obtained.

is a reference pulse f.

In addition, a signal d-fo delayed by a predetermined amount by delay element DL is added.

Therefore, twice the normal input pulse is supplied to the frequency divider 7, and the output fC of the frequency divider 7 is advanced in phase by an amount corresponding to 1/2 of the generation period of the delayed signal. .

In this way, the phase of the output fc of the frequency divider 7 is changed in steps.

Furthermore, the set value N of the frequency division ratio setter 9 is changed based on the output information from the phase comparator 8, etc., and the output frequency is changed.

One way to set N is to set f□”Nofs in advance.
N.

is set, and after the phase of fe approaches the phase of fS (for example, as mentioned above, since the phase difference becomes 1/2 in the 1-week period, π/25 = 5 in 5 cycles of t's). .) lag signal fg1 or lead signal fg (with a phase difference within order e)
The pulse width of 2 is the output f of the reference oscillator 5.

The number of cycles is counted as a unit, and when a lagging signal is output, N is decreased, and when a leading signal is output, N is increased.

The amount of N to be changed at once is f.

The system is decoded based on the count number of , and the system is controlled to reduce the occurrence of late signals and progress signals.

In this way, when f8 occurs or when the phase difference changes rapidly, fc can be quickly followed by the phase matching circuit, and the division ratio N can be changed even when f8 changes slowly. Therefore, it becomes possible to continuously follow fc.

As described above, by removing vCO from the PLL circuit, a circuit configuration that is resistant to stain pressure fluctuations, maintains the previous oscillation frequency even when there is no input, and has a short time (pull-in time) to reach f 8 = f o is created. It becomes possible.

On the other hand, in the transmission of a signal including a DC component, such as image transmission in a facsimile, there may be cases where the input signal f8 is not present for a long period of time.

In such a case, set N and phase by counting the carrier wave frequency during the synchronization period when it is guaranteed that the input signal consists of carrier wave components only, and do not operate the phase comparator outside of the synchronization period. Synchronization is maintained by a correction circuit that corrects quantization errors.

A block diagram in such a case is shown in FIG.

The frequency counter 11 uses the input signal f8 as a reference signal f.

is counted as a unit.

Now 8 f8 pulses are b f. If it corresponds to a pulse, a natural number N that satisfies the relationship b/a = (N natural numbers times a decimal number) is found, and this is transferred to the frequency division ratio setting device 9 to set the frequency division ratio N.

On the other hand, the decimal number is supplied to the quantization error correction circuit 10.

The quantization error correction circuit 10 includes a frequency counter 11
In order to correct the quantization error that occurred when determining the frequency division ratio N from the frequency count number of the carrier wave, the gate of the phase matching device is operated every several cycles (for example, a cycle of f8), and as described above. f.

By suppressing or adding pulses, the error due to quantization is at most f for a period of f8.

control so as not to exceed an amount equivalent to one period of .

Therefore, the switch SW is set to the A side during the synchronization period and to the B side outside the period.

As mentioned above, the vCO used in conventional PLL circuits has been abolished, and a phase matching device that changes the phase in steps and a frequency division ratio setter that changes the output frequency by changing the division ratio of the frequency divider are used. P of the device according to the invention as a main component
The LL circuit is configured.

Therefore, in the configuration based on the present invention, (1) it is stable against power supply voltage fluctuations, and (2) an output synchronized with the immediately previous input signal can be obtained even when there is no input signal.

(3) It has a short pull-in time, which is a significant advantage, especially since (2) above is an essential element for signal transmission that includes DC component data, such as in facsimile.

In addition to the above, according to the present invention, it is possible to completely digitalize the circuit, so (4) it is resistant to noise; (5)
It has features such as being less susceptible to aging and (6) requiring fewer adjustment points, making it possible to provide a demodulator that is more stable and more productive than conventional ones.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional PLL circuit, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an example of a time chart of a phase converter, and Fig. 4 is an example of a configuration of a phase matching circuit. , 5th
The figure is a block diagram of another embodiment of the invention. 5... Reference oscillator, 6... Phase matching device, 7... Frequency divider, 8... Phase comparator, 9... Frequency division ratio setter, 1
0... Quantization error correction circuit, 11... Frequency counter.

Claims (1)

[Claims] 1. A phase comparator that generates a signal according to the phase difference between the human input signal and the frequency divider output signal, a reference oscillator that generates a reference signal, and a reference signal supplied to the frequency divider from the phase comparator. A phase matching device that controls according to the signal, a frequency counter that counts the input signal and calculates the division ratio and quantization error, and a frequency divider that sets the division ratio of the frequency divider according to the output of the frequency counter. a ratio setter, a quantization error correction circuit that supplies a phase matching device with a signal that controls the reference signal supplied to the frequency divider according to a quantization error signal from a frequency counter, a phase comparator and a quantum 1. A phase-locked closed circuit comprising: switching means for selectively inputting the output of the conversion error correction circuit to a phase matching device.