JPS6038661A - Digital speed detecting apparatus - Google Patents

Abstract

PURPOSE:To make it possible to digitally detect a speed from a low rotary speed to a high rotary speed, by detecting phase difference by using a phase locked loop control circuit. CONSTITUTION:A wave form shaping circuit 31 inputs a frequency modulation signal with frequency of fo+ or -ftheta induceed to the secondary winding 13 of a synchroscope 10 and performs the wave form shaping thereof to obtain a digital square wave. A phase comparator 33 outputs the digital square signal subjected to wave form shaping in the wave form shaping circuit 31 and inputs the output signal of a frequency divider 32 to output a predetermined pulse signal. That is, control is performed so as to coincide the phases of two pulse signals with frequencies fo+ or -ftheta, fo+ or -theta' inputted to the phase comparator 33 and, at this time, the output of the phase comparator 33 comes to ''L'' while a deviation counter 34 stops counting and the count data thereof comes to a constant value fo. This data fo comes to a digital rotary speed as it is. Therefore, a speed from a low rotary speed to a high rotary speed can be digitally detected.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a speed detection device that uses an inductive speed detector (synchro) to detect the speed or rotational speed of a speed-detected object.

Conventionally, DC tachometer generators have been generally used as rotational speed detectors, but since these DC tachometer generators have contact brushes on their rotating parts, they have problems in terms of reliability and require maintenance and inspection. Another possibility is to use a microcomputer in the speed control circuit to A/D convert the changing current output of the DC tacho generator, but this is expensive and requires low detection accuracy at low speeds when applied to a feed servo system. There are problems in terms of this, and controllability and speed stability cannot be expected. Furthermore, although pulse generators are suitable for digital processing, their output is not continuous signal, so there is a problem with detection accuracy at low speeds near zero. In order to improve this At, the number of pulses per revolution must be extremely increased, which is expensive and requires processing of high frequency signals, which is impractical.

This is I-1, female, 1, induction type speed detector (synchro)
If , the frequency fR of the output signal is fR=f
o±'' 几-・・・・・・ (1) 7.20 Here, fO: excitation frequency, n: rotational speed (rpm) p is the number of poles of the synchro, and when the rotational speed n is zero, Even at this time, AC No. 1.1 having an excitation frequency fo is induced in the secondary winding, so the rotational speed can be detected continuously down to zero. This rotational speed can be detected by converting the frequency modulated signals W, fR induced into the secondary winding into a digital square wave number 41-, and counting the frequency lυ1 using a high-frequency clock. There is a method in which a square wave signal is frequency multiplied by N times and counted for a certain period of time.

In the former method, K K (1
/'r-1/To) (K: constant, T: count value at a certain rotation speed, TO: count value at stop) and use this as the rotation speed. In this method, since the period of the digital square wave changes depending on the rotation speed, the rotation speed detection time also changes accordingly. Although these two methods differ in that the sampling time varies and is constant, they are essentially the same in that they are detection methods in which an excitation frequency fo is added, and the microcomputer Subtraction processing of 10 minutes of excitation frequency is required in the previous stage or inside. In addition, when applying the latter method to a feed servo system with a speed control range of θ to 100θ (r, p, m), the current detection accuracy is insufficient, so it is difficult to stabilize the low speed range below / (rpm). It was not possible to detect the correct speed.

Therefore, an object of the present invention is to provide a digital speed detection device that can accurately digitally detect the speed or rotational speed of a speed-detected object from low rotation to high ti (rotation) using synchronization. do.

The digital speed detection device of the present invention uses a PLL (phase
The locked loop) control circuit digitally detects the rotational speed from low to high rotation by detecting the phase difference.

The present invention will be explained below with reference to drawings of embodiments. FIG. 1 is a block diagram of a digital tsuji degree detection device according to an embodiment of the present invention. Synchro 10 has p number of poles,
2-phase 7th winding // on the stator side.

/, 2, and a single-phase a-order winding /3 are provided on the rotor side, and the excitation frequency is rO. The excitation circuit θ generates a sine wave signal of 111 and supplies these to the /secondary winding // and /2 of the synchro /θ. Now, let the rotational speed of the rotor be n(
rpm) Toshiyo narrow - Mi fO・・・・・・・・・・・・・・・ +2)
/S θ. The direction of the rotating magnetic field by the secondary winding /l/2 of the synchronizer 10 is made clockwise as shown in the figure. According to equation 111, when the rotation direction of the rotor is in the same direction as the rotating magnetic field, a frequency modulation signal of frequency fn=fo-f is generated, and when the rotation direction is in the opposite direction, a frequency modulation signal of frequency fa=fo+fO is generated.31.
■The signal is induced in the a-order winding/3 of the synchronizer/θ,
The signal is taken out to the outside through a slip ring, a brush, or a rotary transformer (not shown), and is also input to the digitized phase-locked loop control circuit 30. Excitation frequency f
The value of o is selected to be higher than the value of fθ (maximum value) f max when the rotational speed n of the rotor is maximum, and therefore the frequency fR of the frequency modulation signal induced in the secondary winding /3 does not become zero even when the rotational speed n of the rotor is zero, and a frequency modulation signal corresponding to the rotational speed is generated over the entire range of the rotational speed of the rotor.

Figure 2 shows digitized phase-locked loop control circuit 3.
0 is a block diagram showing details of 0. FIG. The waveform shaping circuit 3/ has one frequency (f
A frequency modulation signal (o±fθ) is input and the waveform is shaped into a digital square wave.

The frequency divider 32 divides the frequency of the output signal of the pulse train addition/subtraction circuit 3B, which will be described later, into 1/N. The phase comparator 33 is the waveform shaping circuit 3
Input the digital square θU whose waveform has been shaped by
Based on the signal 〇, a pulse signal with a duty cycle corresponding to the phase difference between the two is output. The deviation counter 311 is
Phase comparator 33 counts. This deviation counter 3'l
The output fθ' is input to the programmable oscillator 3,
The number of pulses is N-fθ' (N: frequency divider 32's frequency division specific volume Courne series (,'-i No. 5 is generated. Add and subtract values, that is, calculate (fc±N-fc values).

1iiJ frequency divider 32 divides this frequency (fo-kN'
Signal 1 of fc: Divide by '/N to obtain frequency fc
/N±fθ←f○±fθ' (, jj3 is the phase comparator 3
Give feedback to 3.

In the 4'+i'i configuration of 1°, the 1,',l, and fo:l-fc frequencies (fo:l-fc) input to the phase comparator 33 are
The phase of the two-horn pulse signal -) of fOJ:l') is controlled to match 5, and at this time, the output of the phase comparator 33 becomes "loaf", and the deviation counter 3'l stops counting, and the count data remains constant. The count data fθ becomes the value fO.This count data fθ directly becomes the digital rotation speed.

Now, the number of poles p-g of synchro 10, the excitation frequency fo-1
13? (H2), rotational speed n −/(rp
In case m), the frequency of the output signal of the waveform shaping circuit 37' is I1, 306 ±006 (H2). Frequency divider 3.2
(7) If N is 216, then n = 0. / (
In order to have a resolution of (rpm), the output of the programmable oscillator 35 must be
! ;It must be l13 Otsu9 (H2). This is the output of the programmable oscillator 3S when the output of the three deviation counters is /bit.

Therefore, the number of bits required to have a data resolution up to n=/000 (rl)m) is 1.213<
10000 (,!14 to 73~/l. If the number of poles p of the synchronizer 10 changes, by changing the gain of the programmable oscillator 3, fc, and the division ratio N of the frequency divider 3.2. n = / 000 with the same number of bits
(rpm).

Furthermore, by using a count clock that is sufficiently higher than the output frequency of the phase comparator 33, the responsiveness of speed detection can be improved.

Since the present invention detects the speed digitally using a phase-locked loop control circuit, the detection accuracy is good up to 115 speeds, the responsiveness is excellent, and stable speed control can be realized even in the low range. Furthermore, speed data can be collected with a constant sampling time, making it suitable for processing by a microcomputer. Also, D/
By using an A converter, the detected speed data can be converted to D/
It is also possible to convert A and provide analog feedback like in the Cong Song Dynasty.

q 17ri Fit Explanation of Figure 1n1 Figure 1 is a schematic configuration diagram of a digital speed detection device according to an embodiment of the present invention;
FIG. 2 is a block diagram showing i(=Mn) of the digital one-dimensional locked loop control circuit of FIG.

10 herring black.

20 = excitation circuit.

30: Digitized phase-locked loop control circuit.

3/: Waveform shaping circuit.

3.2S frequency divider.

33: Phase comparator.

3'l: Deviation counter.

3S: Programmable oscillator.

3.B: Pulse train addition/subtraction circuit.

Claims (1)

[Scope of Claims] A synchronizer that excites a stator winding with a U-phase sine wave signal and sends a frequency modulation signal induced to a rotor winding coupled to a speed detection object; A waveform shaping circuit that shapes a waveform; a frequency divider with frequency division of N; and a phase that inputs the output signal of the waveform shaping circuit and the output signal of the frequency divider and outputs a pulse signal according to the phase difference between them. A comparator, a deviation counter that counts the output signal of the phase comparator described in 01 and outputs it digitally, and a programmable oscillator 2 that inputs the output of the deviation counter and outputs a pulse train signal that is multiplied by N. , a pulse train addition/subtraction circuit that adds or subtracts a signal with a frequency obtained by multiplying the excitation frequency of the stator winding by N and the output signal of the programmable oscillator, and outputs the result to the frequency divider; A digital speed detection device, characterized in that a speed signal of the speed detected object is generated as a digital value from a count value.