JPH0370303A - Fm detection circuit - Google Patents

Abstract

PURPOSE:To obtain a digital FM detection signal with excellent S/N by detecting a digital data corresponding to the highest level of the detection signal when a 1st digital data and a 2nd digital data are swept out and outputting the data as a digitized FM detection signal. CONSTITUTION:The circuit consists of an antenna AMT, an RF amplifier 1, a mixer 2, a voltage controlled oscillator(VCO) 3, a narrow band pass filter 4, a level detection circuit 5, a sample-and-hold circuit 6, a switch circuit 7, a comparator circuit 8, a 256 counter 9, a D/A converter circuit 10, an adder circuit 11, an OR circuit 12 and latch circuits 13, 14. Then the highest level of a detection signal, at an oscillating frequency in response to the sweepout output from the 1st digital data to the 2nd digital data is detected and the digital data corresponding to the highest level is detected and it is outputted as a digitized FM detection signal. Thus, the digital FM detection signal with excellent S/N is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an FM detection circuit, and more particularly to an FM detection circuit that converts an FM detection signal into a digital signal and outputs the digital signal.

[Problems to be solved by conventional techniques and inventions] Conventionally,
Various FM detection circuits have been proposed that convert an FM detection signal into a digital signal and output the digital signal.

However, since the conventional detection circuit generally has a poor noise level to carrier ratio C/N, it is not possible to obtain a sufficient noise level to FM detection signal ratio, that is, a sufficient S/N.

Therefore, an object of the present invention is to provide an FM detection circuit that can obtain a digital FM detection signal with a good S/N ratio.

[Means to solve the problem]

In order to achieve the above object, the FM detection circuit made according to the present invention sequentially sweeps output from the first digital data to the second digital data, and when the second digital data is reached, the FM detection circuit outputs the first digital data again. digital data output means for sweeping output; local oscillation control means for adding the digital data and tuning data from the digital data output means and outputting the added data as a control signal for a local oscillator; F obtained by mixing the signal and the FM signal
a narrowband bandpass filter that passes the M intermediate frequency signal; a detection means that detects the output of the bandpass filter; and when the digital data output means sweeps and outputs from the first digital data to the second digital data. , detection means for detecting the highest level of the detection signal from the detection means and detecting digital data corresponding to the highest level, and an F converting the output of the detection means into a digital signal.
It is characterized by outputting an M detection signal.

[For production]

In the above configuration, when the digital data output means sequentially sweeps output from the first digital data to the second digital data, the oscillation frequency of the local oscillator is controlled by the local oscillator control means according to the addition data of the digital data and the tuning data. Change. As a result, the FM intermediate frequency signal changes in accordance with the digital data, and as the intermediate frequency signal passes through the narrowband bandpass filter, the bandpass filter apparently narrows the intermediate frequency band to 1.
It's getting hotter.

The intermediate frequency signal that has passed through the bandpass filter is detected by the detection means, and the detected signal is further input to the detection means. The detection means detects the highest level of the detection signal by the oscillation frequency of the local oscillator according to the sweep output from the first digital data to the second digital data, and detects the digital data corresponding to the highest level. .

Since the digital data detected by the detection means corresponds to an FM detection signal, it is output as a digital FM detection signal.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a circuit block diagram showing an embodiment of the FM detection circuit according to the present invention.
2 is a mixer, 3 is a voltage controlled oscillator (hereinafter referred to as VCO) that functions as a local oscillator, and 4 is a narrow amplifier that passes the intermediate frequency (hereinafter referred to as IF) signal from mixer 2. Bandpass filter (hereinafter referred to as narrowband BPF), 5 is a diode drawer 5,
6 is a sample/hold circuit (hereinafter referred to as 372 circuit) consisting of capacitor C2 and amplifier Amp2, 7 is a capacitor C8 and amplifier Amp, and a higher level detection circuit;
8 is a switch circuit connected between the level detection circuit 5 and the S/P circuit 6, and 8 is a comparison circuit for comparing the outputs of the level detection circuit 5 and the S/P circuit 6.

9 sequentially sweeps and outputs 8-bit digital data from the first digital data "0" to the second digital data r255J, and outputs the second digital data r255. , the 256 counter outputs the first digital data "0" again and sequentially sweeps and outputs the digital data. 10 is a D/A converter that converts the 8-bit digital data of the 256 counter 9 into a D/A converter. circuit, 11 is the D/A
This is an addition circuit that adds the analog signal voltage from the conversion circuit 10 and the tuning signal voltage, and outputs the added voltage to the VCO 3 as a control voltage.

12 is 256. The count value (digital data) of counter 9 is r255. 13 is an OR circuit to which the trigger signal from the "H" level counter reset pulse outputted when the transition from r□, and the output signal of the comparison circuit 8 are input;
A first latch circuit that latches the digital data of the 256 counter 9 by the output of the R circuit 12;
This is a second latch circuit that latches the latch output of the first latch circuit 13 in response to a trigger signal from the counter 9.

The output of the OR circuit 12 is supplied together with the first latch circuit 13 as a control signal to the switch circuit 7 to control on/off of the switch circuit 7. Furthermore, a digital FM detection signal output is obtained as the output of the second latch circuit 14.

The operation of the above-mentioned configuration will be explained with reference to the timing chart of FIG.

The 256 counter 9 sequentially counts up from "O" as shown in FIG. 2(a) using the external clock shown in FIG. 2(b).
r255. When it reaches "O", it returns to "O" and repeats the count-up operation again. That is, as described above, the first digital data "0" is sequentially swept out to the second digital data r255J, and when the second digital data r255J is reached, it returns to the first digital data "0" and the sweep output is performed again. do. Also, when returning from this r255J to "0", as shown in Figure 2 (
A counter reset pulse of "H" level is output as shown in b).

The digital data of the H.256 counter 9 is converted into an analog signal voltage by a D/A conversion circuit 10, and the tuning signal voltage and the analog signal voltage are added by an addition circuit 11. The added voltage is supplied to vCO3 as a control voltage, and its oscillation frequency is controlled. The VC
The local oscillator signal from O3 is mixed with the FM signal from RF amplifier 1 in mixer 2, and an FMIF signal is output to the output of mixer 2. The IF signal is passed through the narrowband BPF 4, so that noise components are sufficiently removed. Here, since the frequency of the local oscillation signal from ■C○3 is constantly fluctuating by the 256 counter 9, the apparently narrow band BPF 4 sweeps the IF band as shown in FIG. Narrowband BP
The output signal of F4 is level detected by the level detection circuit 5 to obtain a detected level signal as shown in FIG. 2(C).

First, when the 25G counter 9 changes from "r255" to "0", the counter reset signal shown in FIG. 2(d) is output as described above. The output of the OR circuit 12 has a second
The reset signal is outputted as shown in FIG. 3(f) and is supplied as a trigger signal to the first latch circuit 13 and an on control signal to the switch circuit 7. In response, the first latch circuit 13 is provided with latch data as shown in FIG.
As shown in b), the first digital data "o" of the 256 counter 9 is latched. Furthermore, when the switch circuit 13 is turned on, the level detection circuit 5 is connected to the S/P circuit 6.
The output from the detector is input manually, and the detection level at that time is held as shown in FIG. 2 (8).

Next, when the 256 counter 9 counts up sequentially, the local oscillation frequency of the VCO 3 changes according to this digital data, and the output of the level detection circuit 5 changes according to the IF signal from the narrow band BPF 4 as shown in Fig. 2 (C). and change. At this time, the output of the level detection circuit 5 is input to the positive phase input of the comparison circuit 8, and the output of the S/P circuit 6 is input to the negative phase input. Therefore, when the output of the level detection circuit 5 becomes larger than the output of the S/P circuit 6, the comparison circuit 8 outputs an "H" level peak detection pulse as shown in FIG. 2(e).

The detection pulse is input to the OR circuit 12, which outputs an "H" level pulse as shown in FIG. 2(f).

This turns on the switch circuit 7, and the S/P circuit 6 samples/holds the detection level of the level detection circuit 5 at this time, as shown in FIG. 2 (8). Also, the above OR circuit 1
Since the pulse of the output of the comparator circuit 8 is also input to the first latch circuit 13, the latch circuit 13 receives the local oscillation frequency of the VCO 3 when the output of the comparator circuit 8 reaches the rH level as shown in FIG. 2(h). The digital data of the 256 counter 9 that determines the value is latched.

Then, the 256 counter 9 receives the second digital data “2”.
55'', the counter reset pulse shown in FIG. 2(d) is output, and this pulse causes the counter reset pulse to start as shown in FIG. 2(i).
The latch data of the latch circuit 13 is transferred to the second latch circuit 1.
FM from the output of the second latch circuit 14.
Outputs the detected signal as a digital signal.

With the above operation, the 256 counter 9 changes from "0" to r.
By sweeping to '255 J and changing VCo3 accordingly, the FM detection level becomes the highest while the narrowband BPF4 apparently sweeps the IF band according to the digital data from rQJ to r255J. 256 The count value of counter 9 is latched, and the latch data is
Output as M detection digital data.

FIG. 4 shows another embodiment of the FM detection circuit according to the present invention, in which 15 indicates the output of the level detection circuit 5 by A/
A/D conversion circuit 16 is a CPU that performs D conversion;
The same parts as those in the figures are given the same reference numerals.

In the above configuration, the content of the work performed by the CPU 6 according to a predetermined program will be explained with reference to the flowchart of FIG.

In the first step 31, the CPU 16
16, the counter and register inside the controller 16 are reset, and then the process proceeds to step S2, where the counter is driven from the count value "0", and the count value is output to the D/A converter circuit 10 in step S3.

The output from the D/A conversion circuit 10 is added to the tuning voltage by the addition circuit 11, and as described above (VCo3 is added to the tuning voltage by the addition circuit 11).
Oscillates according to the voltage from 1, and IF from narrow band BPF4
The signal is output, and the level detection circuit 5 outputs a level detection signal of the IF signal.

The level detection signal is converted into a digital signal by an A/D conversion circuit 17. Therefore, the CPU 16 proceeds to S4 after step S3, inputs the digital signal D7, and
In the following step S5, the digital signal data D7 is stored in the register of the CPU 16 as set data D0. Next, proceeding to step S6, the counter is incremented by +1, and then, the count value of the counter is output to the D/A conversion circuit 10 in step S7. This allows VC
The oscillation frequency of o3 changes, and the detected level from the level detection circuit 5 at this time is converted into A/D by the A/D conversion circuit 15.
Therefore, in step S8, the A/D converted data D,1 is inputted to the CPU 16.
9, the level detection data D input in step S8
, 1 is compared with the level detection data D0 stored in the register in step S5, and then in step S10, if the former detection data D, , is larger, the data D7 is newly stored in the register as reset data D6. and updates the contents of the register.

Next, in step 311, it is determined whether the count value of the counter is r255J, and if it is not r255J, the process returns to step S6. Also, if it is r255J, step S
Set data D0 branched to 10 and stored in the register
After outputting the data D0 as digital data of the FM detection signal, the process returns to step 31.

In addition, in each of the above embodiments, the 256 counter 9 and the CP
The sweep speed of digital data output from UI 6 is
Set sufficiently fast compared to the displacement of the FMIF signal from mixer 2.

〔effect〕

As described above, according to the present invention, an FM detection signal with a good S/N ratio can be obtained as a digital signal.

[Brief explanation of drawings]

Fig. 1 is a circuit block diagram showing an embodiment of the FM detection circuit according to the present invention, Fig. 2 is a tie chart showing the waveforms of each part in Fig. 1, and Fig. 3 is a diagram of the counter output for the FM signal. FIG. 4 is a circuit block diagram showing another embodiment of the FM detection circuit according to the present invention. FIG. 5 is a flowchart showing the work performed by the CPU in FIG. 4. 3... VCo, 4... Narrowband band pass filter,
5... Level detection circuit, 6... Sample/hold circuit, 7... Switch circuit, 8... Comparison circuit, 9...
...256 counter, 10...D/A conversion circuit, 11
...addition circuit, 12...OR circuit, 13.14...
・Latch circuit, 15...A/D conversion circuit, 16...
CPU. Cub〉Toy Todoroki FMIF4 Customer Care Level Saki I Phlegm 1 @ Figure 3 Figure 4 Figure Figure

Claims (1)

[Claims] Sweep output is performed sequentially from the first digital data to the second digital data, and when the second digital data is reached, the first digital data is output again.
digital data output means for sweeping out digital data from the digital data; local oscillator control means for adding the digital data from the digital data output means and tuning data and outputting the added data as a control signal for the local oscillator; a narrowband bandpass filter that passes an FM intermediate frequency signal obtained by mixing a local oscillator signal and an FM signal; a detection means that detects the output of the bandpass filter; and a first digital data output means. detection means for detecting the highest level of the detection signal from the detection means and detecting the digital data corresponding to the highest level when sweeping out the digital data from the first digital data to the second digital data; An FM detection circuit characterized in that it outputs an FM detection signal converted into a digital signal as an output of the FM detection circuit.