JPH10185969A - Spectrum analyzer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a spectrum analyzer capable of obtaining an indication with small linear error against the frequency of sweep signal and good SN ratio. SOLUTION: The oscillation frequency of a sweep signal generator 13 is controlled by a phase-lock loop PLL1, and reference signal changing with exact frequency pitch is given to the phase lock loop PLL1 to linearly vary the oscillation frequency of he sweep signal generator 13 and decrease the linear error. At the same time, a sample hold circuit 28 is provided to the phase-lock loop PLL1 and detected signal is AD converted and taken in the state controlled in a hold mode and frequency spectrum value is taken in the state with little noise.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spectrum analyzer used for measuring, for example, frequency components contained in various signals.

[0002]

2. Description of the Related Art FIG. 9 shows a schematic configuration of a conventional spectrum analyzer. The signal under test SX to be subjected to frequency analysis is input to the input terminal 11. This measured signal S
X is input to the frequency mixer 12. Frequency mixer 12
Is supplied with a frequency sweep signal from the sweep signal generator 13. This frequency sweep signal is frequency-swept with a bandwidth to be subjected to frequency analysis from the fundamental frequency of the signal under test SX, for example. 14 is a control circuit for controlling the frequency sweep operation of the sweep signal generator 13, and 15 is a ramp voltage generator.

The frequency mixer 12 outputs a signal having a difference FS−FX between the frequency FX of the signal under test SX and the frequency FS of the frequency sweep signal of the sweep signal generator 13 or a signal having a frequency of the sum FS + FX. The band pass filter 16 generally extracts a signal having a difference frequency FS-FX. The frequency FS-FX of this difference is a constant frequency FI1 = FS-FX
The signal FIF1 having a constant frequency is amplified as necessary by the band-pass filter 16, and is converted into a signal having a lower frequency by the second-stage frequency mixer 17 and the third-stage frequency mixer 20. The detected output is detected by the detector 22, the detected output is sampled and held by the sample and hold circuit 23, AD-converted by the AD converter 24, and the AD-converted output is taken into the digital processing type display 25, and the display 25 shows FIG. (Frequency spectrum) included in the signal under measurement SX as shown in FIG. In FIG. 9, reference numeral 18 denotes a second local oscillator;
Is a band pass filter, 20 is a third frequency mixer, 21
Indicates a third local oscillator, respectively.

[0004]

The sweep signal generator 13 which operates as a first local oscillator changes the frequency of the frequency sweep signal linearly with respect to a linear change in the control voltage supplied from the ramp voltage generator 15. It has to change.
However, generally, a deviation Δf occurs with respect to a linear change in the lamp voltage. FIG. 10 shows this state. A straight line A shown in FIG. 10 shows an ideal characteristic in which a linearly changing voltage change of the lamp voltage is replaced with a frequency change of the frequency sweep signal. Curve B shown in FIG.
3 shows a frequency change of the frequency sweep signal of FIG. Even if the curve B is matched with the straight line A at the lower limit frequency FL and the upper limit frequency FH, a deviation of Δf occurs in the middle part. This deviation Δf causes a reading error of Δf at the display position of the frequency spectrum displayed on the display 25 as shown by a dotted line in FIG. That is, when the deviation Δf is shifted to a higher frequency as shown in FIG.
As shown by a dotted line in FIG. 1, the display is shifted to the lower side by Δf. Therefore, in the display example shown in FIG. 11, the position shown by the solid line is the correct display position.

As described above, the conventional spectrum analyzer has a drawback in that an error occurs in the display position of the frequency spectrum, and the error in the display position causes an error in reading the frequency of the frequency spectrum. An object of the present invention is to provide a spectrum analyzer that can accurately determine a frequency measurement value of a frequency spectrum.

[0006]

According to the present invention, a sweep signal generator operating as a first local oscillator is constituted by a voltage-controlled oscillator, and the sweep signal generator constituted by the voltage-controlled oscillator is oscillated by a phase-locked loop. In addition to controlling the frequency, a sample-and-hold circuit is provided between a phase comparator and a sweep signal generator forming a phase lock loop.

A phase lock loop receives a reference signal whose frequency changes accurately, and the frequency of this reference signal is set to 1
The sample and hold circuit is sampled and held every time the step is changed, and the value of the frequency spectrum is A / D converted and taken in while the sample and hold circuit is in the hold state. According to the configuration of the present invention, the oscillation frequency of the sweep signal generator changes exactly one step at a time following the change in the frequency of the reference signal, and an accurate sweep frequency can be obtained over the entire frequency sweep range.

Further, according to the present invention, the sweep signal generator is configured to maintain the oscillation state by the hold voltage of the sample and hold circuit at the timing of measuring the frequency spectrum. Therefore, the oscillation frequency of the sweep signal generator is controlled by a phase lock loop. This is more stable than the state in which it is performed, thereby providing an advantage that the S / N ratio (to FM modulation noise ratio) at the time of frequency spectrum measurement can be improved.

[0009]

FIG. 1 shows an embodiment of the present invention. Parts corresponding to those in FIG. 9 are denoted by the same reference numerals. In the present invention, the sweep signal generator 13 operating as the first local oscillator is constituted by a voltage-controlled oscillator, and the oscillation frequency of the sweep signal generator 13 constituted by the voltage-controlled oscillator is controlled by a phase lock loop PLL1, Further, a reference signal FR that changes at predetermined frequency intervals is supplied to the phase lock loop PLL1, and the oscillation frequency of the sweep signal generator controlled by the phase lock loop PLL1 is changed by following the change in the frequency of the reference signal FR. It is configured.

The phase lock loop PLL 1 is composed of a voltage controlled oscillator composed of a sweep signal generator 13, a frequency divider 26 and a phase comparator 27, as is well known. According to the present invention, the configuration in which the sample-and-hold circuit 28 is provided on the output side of the phase comparator 27 and the reference signal FR which changes at a predetermined frequency interval are provided in the phase lock loop PLL1.
Is provided with a reference signal generator 30 that supplies the reference signal.

In this example, the reference signal generator 30 is constituted by a phase lock loop. The reference signal generator 30 changes the frequency of the reference signal FR output from the frequency divider 32 at a predetermined frequency pitch by changing the frequency division ratio 1 / Q of the frequency divider 32. That is, in this example, the third local oscillator 21 (a crystal oscillator is generally used) is used as the phase comparator 33 constituting the reference signal generator 30.
Supplies a signal with a stable frequency, and uses the signal with the stable frequency as a reference signal to divide the frequency of the divider 32 by 1 /
By changing Q, a reference signal FR that changes at a predetermined frequency pitch is obtained.

Assuming that the oscillation frequency of the third local oscillator 21 is, for example, 10 MHz and the frequency division ratio of the frequency divider 32 is 1/20, the voltage controlled oscillator 31 oscillates at 200 MHz.
If the oscillation frequency of the voltage controlled oscillator 31 is 200 MHz, a signal of 10 MHz is input from the frequency divider 32 to the phase comparator 33. Therefore, the third local oscillator 2 is provided in the phase comparator 33.
A signal having the same frequency as 1 is input, and the oscillation frequency of the voltage controlled oscillator 31 is controlled so that the phase difference is the same. By configuring the third local oscillator 21 with, for example, a crystal oscillator, its oscillation frequency is stabilized. As a result, the oscillation frequency of the voltage controlled oscillator 31 is also stably maintained at 200 MHz. The oscillation signal of the voltage controlled oscillator 31 is divided by a frequency divider 34.
For example, the reference signal FR is obtained by dividing the frequency to 1/20,
This reference signal FR is supplied to the phase comparator 27 of the phase lock loop PLL1. Accordingly, the reference signal FR having a frequency of 200/20 MHz is input to the phase comparator 27 of the phase lock loop PLL1.

Here, the frequency division ratio 1 / Q of the frequency divider 32 is set to 1/2.
When it is changed to 1, the oscillation frequency of the voltage controlled oscillator 31 changes to 210 MHz. That is, the oscillation frequency F31 of the voltage controlled oscillator 31 is controlled to a frequency satisfying F31 × 1 / Q = 10 MHz. Therefore, the dividing ratio 1 / Q is set to 1/2.
The oscillation frequency F of the voltage-controlled oscillator 31 is changed by sequentially changing the oscillation frequency to 0, 1/21, 1/22, 1/23.
31 is 200MHz, 210MHz, 220MHz, 230M
It changes at 10 MHz intervals like Hz ...

As a result, the frequency of the reference signal FR output from the frequency divider 34 is 10.0 MHz, 10.5 MHz, 11.0 MHz, 11. 5M
Hz, 12.0 MHz..., At intervals of 0.5 MHz. The controller 29 controls the division ratio 1 / Q of the divider 32, the division ratio 1 / M of the divider 34, and the mode switching of the sample and hold circuit 28.

The phase comparator 27 of the phase lock loop PLL 1 supplies 10.0 MHz, 10.5 MHz, 11.0 MHz, 11.5 MHz.
By inputting a reference signal that changes at a pitch of 0.5 MHz, such as MHz, 12.0 MHz,..., The frequency of the signal input from the frequency divider 26 of the phase lock loop PLL 1 to the phase comparator 27 is also 10.0 MHz. , 10.5 MHz, 11.0 MH
.., 11.5 MHz, 12.0 MHz... at a pitch of 0.5 MHz. This is shown in FIG.

Here, the frequency division ratio 1 / N of the frequency divider 26 constituting the phase lock loop PLL1 is, for example, 1/40.
Assuming that it is set to 0, the reference signal generator 30
When the frequency of the reference signal FR supplied to the phase lock loop PLL1 from the
Will oscillate 10.0 MHz × 400 = 4.0 GHz. Hereinafter, similarly, the oscillation frequency of the sweep signal generator 13 for each reference frequency is 10.5 MHz × 400 = 4.2 GHz 11.0 MHz × 400 = 4.4 GHz 11.5 MHz × 400 = 4.6 GHz 12.0 MHz The oscillation frequency of the sweep signal generator 13 also changes at a pitch of 0.2 GHz, as in the case of × 400 = 4.8 GHz.

The frequency of the reference signal FR output from the reference signal generator 30 is accurate because it is based on a highly accurate signal from the third local oscillator 21 like a crystal oscillator. In addition, the changing pitch is exactly 0.5 MHz in this example.
Change by one. Therefore, the oscillation frequency of the sweep signal generator 13 is controlled following the precisely defined reference signal FR, so that the oscillation frequency of the sweep signal generator 13 is also accurately defined. Therefore, by sweeping the oscillation frequency of the sweep signal generator 13 at a pitch of 0.2 GHz over a required bandwidth, the sweep frequency can be changed linearly.

Next, the operation of the sample and hold circuit 28 provided in the phase lock loop PLL 1 and the sample and hold circuit 23 provided on the output side of the detector 22 will be described. While the sample and hold circuit 28 performs the sampling operation, the phase lock loop PLL1 forms a loop,
The sweep signal generator 13 is controlled to oscillate at a frequency N times the frequency of the reference signal FR supplied from the reference signal generator 30. Therefore, the phase lock loop PLL1
The sample-and-hold circuit 28 provided for the reference signal generator 3
0 changes the frequency by one step, and the phase lock loop PLL1 responds to the change in the frequency until the oscillation frequency of the sweep signal generator 13 becomes stable.
1, maintained in a sampling state as shown in FIG. 3B,
When the phase lock loop PLL1 is stabilized, the operation enters the hold mode.

On the other hand, the sample and hold circuit 23 samples the detection output of the detector 22 after the sample and hold circuit 28 provided in the phase lock loop PLL1 enters the hold mode, and enters the hold mode. A
After the sample and hold circuit 23 enters the hold state, the D converter 24 performs AD conversion on the voltage during the hold. After the AD converter 24 performs the AD conversion operation, the display 25 takes in the AD conversion output into, for example, an image memory.
Each AD conversion value taken into the image memory is repeatedly read out using the idle time and displayed on the cathode ray tube display. Curve A shown in FIG. 4 shows an example of the display.

Each point P1, P2, P3 of the curve A shown in FIG.
.. Indicate detection output values at each frequency sampled and captured. As described above, the configuration is such that the second sample-hold circuit 23 performs the sampling operation while the sample-hold circuit 28 provided in the phase lock loop PLL1 is maintained in the hold mode. The detection output of the detector 22 to be sampled can sample a detection signal in a stable state.

The reason will be described below. The oscillation frequency of the sweep signal generator 13 is controlled by the phase lock loop PLL1. In a state where the phase lock loop PLL1 is performing the control operation, the oscillation frequency of the sweep signal generator 13 is controlled by the control loop, so that the frequency is not maintained at one point but changes repeatedly. This fluctuation largely fluctuates as the value of N of the frequency division ratio 1 / N of the frequency divider 26 increases. On the other hand, when the sample and hold circuit 28 enters the hold mode, a constant hold voltage (DC voltage) is input to the voltage control terminal of the sweep signal generator 13.
As a result, the oscillation frequency is maintained at a constant frequency corresponding to the hold voltage, noise (FM modulation noise) generated in the detection output of the detector 22 is reduced, and the SN ratio can be significantly improved. A curve B shown in FIG. 4 shows a display example when sampling is performed by the sample and hold circuit 23 in a state where the phase lock loop PLL1 is operated. FIG.
In the curve B shown in (1), the detection output of the detector 22 contains a large amount of FM modulation noise, so that the level does not sufficiently decrease even in a portion where the level should be low. For this reason, there is a disadvantage that the amount of the frequency spectrum cannot be measured accurately.

FIG. 5 shows another embodiment of the present invention. In this embodiment, a reference signal generator 30 is connected to a voltage-controlled oscillator 31.
, A frequency divider 34, and a DA converter 35 that supplies a voltage signal that changes stepwise to the voltage controlled oscillator 31. The D / A converter 35 is supplied with a digital signal whose value changes by an equal amount from the control circuit 25.
Therefore, the oscillation frequency of the voltage controlled oscillator 31 changes according to the digital value given to the DA converter 35, and can be changed so as to increase by 0.5 MHz, for example, as described with reference to FIG. The oscillation signal of the voltage controlled oscillator 31 is frequency-divided by the frequency divider 34 to, for example, 1/20, and the frequency-divided output is input to the phase comparator 27 constituting the phase lock loop PLL1. The controller 29 can be constituted by a microcomputer, for example. Therefore, the reference signal generator 30 can generate a reference signal whose frequency changes by an arbitrary step amount (frequency change amount) from the microcomputer. Therefore, also in this embodiment, the frequency change of the frequency sweep signal of the sweep signal generator 13 can be accurately defined. In this case, the oscillation frequency of the sweep signal generator 13 also depends on the phase lock loop PL.
It is controlled by L1 and changes following the frequency of the reference signal FR output from the reference signal generator 30.

FIG. 6 shows still another embodiment of the present invention.
In this embodiment, the reference signal generator 30 is connected to the third local oscillator 2
1 and a frequency divider 34. In this case, the frequency division ratio 1 / M of the frequency divider 34 is controlled and changed by the controller 29, and the frequency division ratio 1 / M of the frequency divider 34 is changed. The case where the frequency of a signal is changed is shown.

FIG. 7 shows still another embodiment of the present invention.
In this embodiment, the phase lock loop PL shown in FIG.
This is a configuration in which a ramp voltage generator 41 and an analog addition circuit 42 are added to the configuration of L1. in this case,
Phase lock loop PLL1 from reference signal generator 30
The step .DELTA.F of the frequency of the reference signal FR to be given is more coarsely taken than in the embodiment of FIG. In the embodiment of FIG. 1, assuming that the frequency sweep band is sampled and held at a resolution of, for example, 1000 points and AD changes, in the embodiment of FIG. 7, the sample and hold is performed at a resolution of 400 points and the value of each sampled and held value is obtained. A case is shown in which the frequency is swept by a lamp voltage.

FIG. 8 is a waveform chart of each part. The staircase waveform shown in FIG. 8A indicates a frequency change of the reference signal FR supplied from the reference signal generator 30 to the phase lock loop PLL1. This frequency change corresponds to the sample and hold voltage sampled and held by the sample and hold circuit 28 and the sweep signal frequency of the sweep signal generator 13 as shown.

The lamp voltage shown in FIG. 8B indicates a lamp voltage waveform output from the lamp voltage generator 41. The ramp voltage generator 41 takes a pause for a short period of time at the beginning of the rise of the ramp voltage. During the pause, the phase lock loop PLL1 controls the sample and hold circuit 28 to the sampling mode, closes the control loop, and generates a sweep signal. The control operation is performed so that the oscillation frequency of the frequency divider 13 becomes N times the frequency of the signal given from the reference signal generator 30 (N is the frequency division number of the frequency divider 26). FIG. 8C shows the waveform of the control signal supplied to the sample hold circuit 28.

The ramp voltage starts rising with the oscillation frequency of the sweep signal generator 13 controlled to a specified frequency. Accordingly, with the rise of the ramp voltage, the oscillation frequency of the sweep signal generator 13 starts the frequency sweep. At the same time, the AD converter 24 performs the AD conversion with the clock shown in FIG.
Perform a conversion operation. The AD conversion operation is performed except for the rest period of the lamp voltage.

According to the embodiment shown in FIG. 7, the sweep frequency is changed for each sample and hold point by the reference signal generator 30.
, The sweep frequency can be changed linearly over the entire frequency sweep band. In addition, since the number of times of the sample hold is smaller than that of the embodiment shown in FIG. 1, the time required for the frequency sweep can be shorter than that of the embodiment shown in FIG. Therefore, the effect that the frequency analysis result can be taken in at a high speed is obtained.

[0029]

As described above, according to the present invention, the oscillation frequency of the sweep signal generator 13 is controlled by the phase lock loop PLL1.
1 is provided with a reference signal whose frequency is correctly defined from the reference signal generator 30 so that the oscillation frequency of the sweep signal generator 13 is sequentially frequency-swept.
The oscillation frequency of No. 3 changes linearly in each part of the frequency sweep band. As a result, the frequency of the frequency spectrum displayed on the display 25 can be displayed correctly,
The advantage is that a spectrum analyzer with a small frequency reading error can be provided.

Further, when the AD converter 24 AD-converts the detection output of the detector 22 and takes it in, the phase-locked loop PLL1 controls the sample-and-hold circuit 28 to a hold state and performs AD conversion. In a state in which the value of the frequency spectrum is converted and taken in, the sweep signal generator 13 maintains the oscillation state with the sampled and held DC voltage, so that the oscillation frequency is stably maintained without fluctuation. Therefore, there is provided a spectrum analyzer which can reduce the level of FM modulation noise and can display a signal having a good SN ratio, that is, a large difference in frequency spectrum can be displayed (generally referred to as having a wide dynamic range). The benefits can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention.

FIG. 2 is a waveform chart for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a waveform diagram similar to FIG. 2;

FIG. 4 is a view showing a display example of a frequency spectrum obtained in the embodiment of FIG. 1;

FIG. 5 is a block diagram for explaining a modified embodiment of the present invention.

FIG. 6 is a block diagram for explaining another modified embodiment of the present invention.

FIG. 7 is a block diagram for explaining still another modified embodiment of the present invention.

FIG. 8 is a waveform chart for explaining the operation of the embodiment shown in FIG. 7;

FIG. 9 is a block diagram for explaining a conventional technique.

FIG. 10 is a graph for explaining inconvenience of the conventional technique.

FIG. 11 is a diagram showing a display example of a frequency spectrum for explaining inconvenience of the conventional technique.

[Explanation of symbols]

 Reference Signs List 11 input terminal SX signal under measurement 12 frequency mixer 13 sweep signal generator 16 band pass filter PLL1 phase lock loop 26 frequency divider 27 phase comparator 28 sample and hold circuit 29 controller 30 reference signal generator

Claims (6)

[Claims] 1. A. First Embodiment Constituted by a voltage controlled oscillator,
B. a sweep signal generator for providing a frequency sweep signal to a frequency mixer to which a signal under test is input; B. a phase lock loop for controlling the oscillation frequency of the sweep signal generator; B. a reference signal generator for providing a reference signal whose frequency changes at predetermined intervals to the phase lock loop; Each time the reference signal generator changes the frequency by one step, a sample-and-hold circuit that samples and holds the phase comparison output of the phase comparator that forms the phase lock loop, and applies the hold voltage to the sweep signal generator. A spectrum analyzer characterized by comprising: 2. The spectrum analyzer according to claim 1, wherein the reference signal generator is constituted by a phase lock loop, and the frequency division ratio of a variable frequency divider provided in the phase lock loop is changed to perform the sweeping. A spectrum analyzer wherein the frequency of a reference signal applied to a phase lock loop for controlling an oscillation frequency of a signal generator is changed step by step. 3. The spectrum analyzer according to claim 1, wherein said reference signal generator is a D / A converter and said D / A converter.
A voltage-controlled oscillator whose oscillation frequency is controlled by the DA conversion output voltage of the A-converter, changing the value of the digital signal given to the DA converter by a predetermined value, and changing the oscillation frequency of the voltage-controlled oscillator by a predetermined value. A spectrum analyzer characterized in that it is configured to change at a frequency pitch. 4. The spectrum analyzer according to claim 1, wherein the reference signal generator comprises a fixed oscillator having a stable oscillation frequency and a variable frequency divider, and the frequency division ratio of the variable frequency divider is changed. A spectrum analyzer, wherein the frequency of a reference signal applied to the phase lock loop is changed step by step. 5. The spectrum analyzer according to claim 1, wherein an analog adder is provided between the sample and hold circuit provided in the phase lock loop and a frequency sweep signal generator, and the analog adder is used to control the sample and hold circuit. The ramp voltage is added to the hold voltage, the sample / hold circuit is controlled to the sampling mode when the ramp voltage is zero, and the oscillation frequency of the sweep signal generator is changed from the reference signal generator in that state. While controlling to the frequency specified by the frequency of the given reference signal, and through the control state, the sample and hold circuit is switched to the hold mode to start the rise of the lamp voltage, and until the lamp voltage reaches a predetermined voltage. During the period, the AD converter is operated in the AD conversion at a predetermined repetition cycle. Then, when the ramp voltage reaches a predetermined voltage, the sample hold circuit is switched back to the sample mode, and the frequency of the reference signal generated by the reference signal generator is changed to the next step. A frequency sweep of a predetermined frequency range by repeatedly changing the oscillation frequency of the sweep signal generator to a frequency defined by the frequency of the next step. 6. A spectrum analyzer according to claim 1, wherein a signal having a sum or difference frequency obtained at an output side of said frequency mixer is extracted, and said signal is extracted by said band-pass filter. A detector for detecting a signal; a second sample-and-hold circuit for sampling a detection output of the detector and controlling the sample-hold circuit in the hold state while the sample-hold circuit inserted in the phase-lock loop is controlled to the hold state; A in which the second sample-and-hold circuit AD-converts the hold voltage while the second sample-hold circuit is controlled to the hold state.
A spectrum analyzer comprising: a D converter.