JPH0369197B2 - - Google Patents

Info

Publication number
JPH0369197B2
JPH0369197B2 JP60186919A JP18691985A JPH0369197B2 JP H0369197 B2 JPH0369197 B2 JP H0369197B2 JP 60186919 A JP60186919 A JP 60186919A JP 18691985 A JP18691985 A JP 18691985A JP H0369197 B2 JPH0369197 B2 JP H0369197B2
Authority
JP
Japan
Prior art keywords
substrate
multilayer
conductor
weight
firing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60186919A
Other languages
Japanese (ja)
Other versions
JPS6247196A (en
Inventor
Koichi Kumagai
Shinji Shimazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP18691985A priority Critical patent/JPS6247196A/en
Publication of JPS6247196A publication Critical patent/JPS6247196A/en
Publication of JPH0369197B2 publication Critical patent/JPH0369197B2/ja
Granted legal-status Critical Current

Links

Description

【発明の詳細な説明】[Detailed description of the invention]

産業上の利用分野 本発明は、セラミツク多層基板、特に低温焼成
可能なセラミツク多層基板に関するものである。 従来の技術 近年、電子回路には、厚膜印刷法により簡便に
回路形成できる熱放散性の優れたセラミツク基板
を使用した電子回路が使用されている。そして、
より小型高性能化を実現する為に多層電子回路基
板が使用され始めている。 多層回路基板を製造する方法は一般的には次に
述べる(a),(b),(c)の三種類がある。 (a) セラミツク焼結体上での印刷多層法 (b) グリーンシート上での印刷多層法 (c) グリーンシート積層多層法 (a)のセラミツク焼結体上での印刷多層法による
多層基板の製造方法を説明すると、第1図にその
プロセスを示すように、まず基板となるセラミツ
ク焼結体上に第1導体層を印刷・乾燥・焼成し
(ステツプ1〜3)、次に第1絶縁層を印刷・乾
燥・焼成し(ステツプ4〜6)、その上に第2絶
縁層を印刷・乾燥し(ステツプ7,8)、第2導
体層を印刷・乾燥し(ステツプ9,10)、第2絶
縁層ごと一括焼成(ステツプ11)する。この際、
第1及び第2絶縁層はヴイアホールと呼ばれる微
小孔が形成されるように印刷し、その微小孔中に
第2導体層に用いられる材料が充填されるように
第2導体層を印刷する事により第1導体層と第2
導体層とが接続される。次に第2導体層上に第3
絶縁層を印刷・乾燥・焼成し、第2絶縁層以降と
同手順で層数を重ねていく(ステツプ1〜11)。 (b)のグリーンシート上での印刷多層法による多
層基板の製造方法は、第2図にそのプロセスを示
すように、まず焼成後基板となるセラミツクのグ
リーンシート上に第1導体層を印刷・乾燥し(ス
テツプ12,13)、次にその上に第1絶縁層を印
刷・乾燥し(ステツプ14,15)、引き続き第2導
体層、第2絶縁層の印刷・乾燥を行ない(ステツ
プ16〜19)、以降同手順で層数を繰り返し(ステ
ツプ12〜19)、グリーンシートと導体層と絶縁層
とを一括焼成する(ステツプ20)。 (c)のグリーンシート積層多層法による多層基板
の製造方法は、第3図にそのプロセスを示すよう
に、まず複数枚のセラミツクのグリーンシートそ
れぞれに異なるパターンの微小孔を形成し(ステ
ツプ22〜24)、それぞれ異なるパターンの導体層
を印刷・乾燥する(ステツプ25〜30)。次に導体
パターンの異なるグリーンシート同士を所望枚数
積層し(ステツプ31)、適度な圧力と適度な温度
のもとで圧着し(ステツプ32)、所望の外形寸法
に切断してから焼成する(ステツプ33,34)。各
導体層間の導通はグリーンシートの微小孔に充填
された導体により行なわれる。 (b),(c)の製造方法においては共に基板焼成の後
に最上層の厚膜形成を行なう(ステツプ21,35)。 (a),(b),(c)三種類の製造方法を比較すると、(a)
は比較的簡単な技術で多層化が可能であるが、実
質的な層数限界は4〜6層でありそれ以上の層数
は表面の凹凸が激しくなり実用に耐えない。(b)は
グリーンシートと印刷した絶縁層と導体層とを一
度に焼成する事によりプロセスの合理化を行なう
事ができる。しかし(b)も(a)同様に、層数を増すと
表面の凹凸が大きくなるのでやはり限界層数は4
〜6層である。(c)は理論的に層数は無限に可能で
あり、現実的にも30〜40層程度の多層基板が報告
されている。しかし、その製造にはきわめて高度
な技術を要し、プロセス的課題も多い。 以上の(a),(b),(c)三種類の製造方法のうち、本
発明は(c)のグリーンシート積層多層法に関するも
のである。第3図を参照にしてより詳細に従来技
術を述べる。 (従来技術の第一例)まず、アルミナパウダー
と有機物の混合体を所定の厚みに成形したグリー
ンシート複数枚に対し、ヴイアホールとなる微小
孔をそれぞれに異なるパターンで形成し(ステツ
プ22〜24)、それぞれ異なるパターンの導体層を
印刷・乾燥する(ステツプ25〜30)。導体材料に
は主にW,Moが使用される。ヴイアホールへの
導体材料の充填は導体の印刷工程と同時に行なう
(ステツプ25〜27)か、もしくは印刷工程の前に
ヴイアホール単独に導体材料を充填する。導体の
乾燥後に各々異なる導体パターンを形成したグリ
ーンシートを所定枚数積層し(ステツプ31)、適
度な温度下で加圧一体化する(ステツプ32)。次
に、所望の外形寸法に切断し(ステツプ33)、約
1600℃の還元性雰囲気中で焼成し(ステツプ34)、
多層基板となる。焼成された基板は充分洗浄さ
れ、以降最上層の厚膜形成工程(ステツプ35)へ
と進む。 (従来技術の第二例)特公昭59−22399号公報
に開示される「多層セラミツク基板」にあるよう
に、まず、ガラス材料とアルミナ材料による複合
組成物と有機物の混合体を所定の厚みに成形した
グリーンシート複数枚に対し、ヴイアホールとな
る微小孔をそれぞれに異なるパターンで形成し
(ステツプ22〜24)、それぞれ異なるパターンの導
体層を印刷・乾燥する(ステツプ25〜30)。導体
材料にはAg,Au,Pd,Pt等の単体あるいはこ
れらの合金が使用される。ヴイアホールへの導体
材料の充填は導体の印刷工程と同時に行なう(ス
テツプ25〜27)か、もしくは印刷工程の前にヴイ
アホール単独に導体材料を充填する。導体の乾燥
後に各々異なる導体パターンを形成したグリーン
シートを所定枚数積層し(ステツプ31)、適度な
温度下で加圧一体化する(ステツプ32)。次に、
所望の外形寸法に切断し(ステツプ33)、700℃〜
1400℃の空気中で焼成し(ステツプ34)多層基板
となる。焼成された基板は充分洗浄され、以降最
上層の厚膜形成工程(ステツプ35)へと進む。 発明が解決しようとする問題点 しかしながら上記のような従来技術の第一例で
は、焼成温度が高く還元性雰囲気を使用する為に
設備費用が高く、取扱いも不便であつた。また、
グリーンシート材料にアルミナを使用しており焼
成温度が高い為、導体材料にはW,Mo等の高融
点金属しか使用出来ず、結果として導体の抵抗値
が高くなるという問題点を有していた。 また従来技術の第二例では、上記第一例の問題
点は解決できるがガラス材料とアルミナ材料によ
る複合組成物の数に焼成収縮率の制御がアルミナ
単独材料より難かしいという欠点を有しており歩
留りが低いという問題点があつた。ちなみに上記
第一例による多層基板の焼成収縮率のばらつきは
±0.5%〜±1.0%であり、上記第二例による多層
基板の焼成収縮率は±1.0%〜±2.5%あつた。 本発明は上記問題点に鑑み、導体材料にAg,
Au,Pd,Pt等の単体あるいはこれらの合金であ
る抵抗値の低い低融点金属を使用し、焼成温度は
低く空気中焼成を可能にして設備費用を低減し、
取り扱いも容易にする事を目的とし、かつ焼成収
縮率のばらつきが±1.0%未満である空気中低温
焼成可能なセラミツク多層基板を提供するもので
ある。 問題点を解決するための手段 上記問題点を解決するために本発明のセラミツ
ク多層基板は、酸化物に換算して、 SiO2 5〜55重量% B2O3 1〜30重量%、 Li2O,Na2O,K2Oのうち少なくとも1種
0.01〜10重量%、 MgO,CaO,ZnO,BaOのうち少くとも1種
0.05〜25重量% の組成からなる基本組成物に、同じく酸化物に換
算して、 Al2O3,ZrO2,TiO2のうち少なくとも1種
15〜65重量% の組成の添加物を含む誘電体組成物により絶縁層
を形成するものである。 作 用 本発明のセラミツク多層基板は、約870℃〜980
℃の低温で焼結可能な誘電体組成物により絶縁層
が形成されており、しかも電子回路形成用のセラ
ミツク基板としての特性を充分発揮する。 本発明では、低融点金属であるAg,Au,Pd,
Pt等の単体あるいはこれらの合金の使用が可能
であり、これら金属は空気中でも酸化しにくい為
還元性の焼成雰囲気は不必要であり、Au,Agは
抵抗値がW,Moよりも低い。従つて、空気中低
温焼成により設備費も小さく済み、取り扱いも簡
便になる。 さらに、本発明のセラミツク多層基板は焼成収
縮率のばらつきが±1.0未満である為、歩留りが
高く量産性が良好である。 本発明の組成物における限定理由は次の通りで
ある。 SiO2は基板を構成する基本組成物であつてガ
ラス形成の主材料である。SiO2が5%未満では
焼成温度が高くなり、Ag,Au,Pt,Pdの低融
点金属を内部導体として使用出来なくなり、焼成
収縮率のばらつきが大きくなる。またSiO2が55
%を超えると曲げ強さが小さくなり過ぎ、さらに
焼成収縮率のばらつきが大きくなり、基板として
の実用性に耐えない。 B2O3もまたは基板構成の基本組成物であり、
B2O3が1%未満では吸水性を帯び曲げ強さも低
い。またB2O3が30%を超えると焼結時にセラミ
ツクの変形が著しくなる。 MgO,CaO,ZnO,BaOは基板の焼結性向上
及び熱膨脹係数の制御、さらには誘電正接を良好
にする目的添加される。MgO,CaO,ZnO,
BaOのうち少なくとも1種が0.05%未満では焼結
性が不充分であり、25%を超えると誘電正接が大
きくなり好ましくない。熱膨脹係数は基板の用途
により種々制御されるが、通常の厚膜混成集積回
路として用いる場合、特に厚膜導体ペースト及び
厚膜抵抗ペーストにより回路形成を行なう場合は
アルミナの熱膨脹係数6.0〜6.5×10-6/℃に一致
させるのが好ましく、またICのシリコンチツプ
を直接基板に実装する場合はシリコンの熱膨脹係
数4×10-6/℃に一致させるのが好ましい。熱膨
脹係数だけで基板の良否判断は難かしいが、両者
の値と比較して大きく離れた値を持つ基板は実用
に耐えない。 K2O,Na2O,Li2Oは基板の焼結性向上及び吸
水性の防止,さらには基板の変形を抑える目的で
添加する。K2O,Na2O,Li2Oのうち少なくとも
1種が0.01%未満では基板の変形が著しくなり、
大きく基板が反る。K2O,Na2O,Li2Oのうち少
なくとも1種が10%を超えると焼結が不充分とな
り吸水性を帯びる。 Al2O3,ZrO2,TiO2は基板のフイラーとして
使われ、主に曲げ強さの向上と焼成収縮率のばら
つきの抑制の為に添加される。 Al2O3,ZrO2,TiO2のうち少なくとも1種が
15%未満では曲げ強さが小さ過ぎ焼成収縮率のば
らつきも大きく実用に耐えない。またAl2O3
ZrO2,TiO2のうち少なくとも1種が65%を超え
ると焼結温度が高くなりかつ焼結が不充分で吸水
性を帯び、また曲げ強さも小さくなる。 実施例 以下本発明の多層基板用誘電体組成物の実施例
について説明する。 まずガラスの調整に当つては、後掲の第1表に
示した組成になるように基本組成物の各原料を秤
量してバツチを調整し、このバツチを1400〜1500
℃で1〜3時間加熱して溶融し、例えばロールア
ウト法等によりガラズ板を成形する。次いでこの
ガラス板をアルミナボールなどで平均粒径0.5〜
5μmの粉末とし、同粒径程度の添加物を加える事
により本発明の誘電体組成物が製造される。な
お、この際用いられる原料粉末は明確化のため酸
化物の換算表記したが、鉱物・酸化物・炭酸塩・
水酸化物などの形でも通常の方法により使用され
るのは勿論である。 次に、このようにして得られた誘電体組成物を
使用したグリーンシート積層多層法によるセラミ
ツク多層基板の製造方法の一例を述べる。 まず上記組成物100重量部に対して、ポリビニ
ルブチラール10重量部、ジブチルフタレートを6
重量部、グリセリンモノオレエート0.4重量部、
1−1−1トリクロルエタンを20重量部、イソプ
ロピルアルコールを39重量部加え、24時間ボール
ミル混合を行ないスラリを造つた。このスラリで
ポリエステルフイルム上にドクターブレード法に
より厚み0.1mmのグリーンシートを製造し、充分
なエージングを行ない、ヴイアホールとなる微小
孔を機械的な加工により形成した。次いでこのヴ
イアホールにメタルマスクを用いた印刷法により
導体材料を充填した。使用した導体材料はAuで
融点は1062℃であつた。 次に、同じ導体材料により導体層をグリーンシ
ートに印刷・乾燥した。ヴイアホールパターン,
導体印刷パターンが各々異なるグリーンシート複
数枚を、80℃の温度下で200Kg/cm2の圧力で密着
させ加圧一体化した。次に外形切断の後に最大温
度870〜1340℃最大温度保持時間60分にて焼成し
た。焼成された多層基板は、純水で超音波洗浄後
表裏の最上層厚膜を形成して、電子回路としての
機能が発揮される基板として完成した。 上記製造法により出来た基板としての特性を誘
電体組成物の組成別に第1表に示す。特性は、上
記の電子回路としての機能が発揮される基板につ
いて曲げ強さ、吸水率、誘電正接を測定し、結果
を第1表に示した。また、同表の焼結温度はそれ
ぞれの組成物について予じめ示差熱分析よりおお
よその焼結温度を推定しておき、吸水率0.0%で
あり、なおかつ曲げ強さが最大になる焼結温度を
選択した。反り変形の有無については、基板焼結
後、外観形状を目視で観察して、基板表面の凹凸
及び反りうねり、また大きな変形があるものに関
して実用に耐えないとした。
INDUSTRIAL APPLICATION FIELD The present invention relates to a ceramic multilayer substrate, particularly a ceramic multilayer substrate that can be fired at a low temperature. BACKGROUND OF THE INVENTION In recent years, electronic circuits using ceramic substrates with excellent heat dissipation properties and which can be easily formed by thick film printing have been used. and,
Multilayer electronic circuit boards are beginning to be used to achieve smaller size and higher performance. There are generally three types of methods for manufacturing multilayer circuit boards: (a), (b), and (c) described below. (a) Printing multilayer method on ceramic sintered body (b) Printing multilayer method on green sheet (c) Green sheet lamination multilayer method Multilayer substrate by printing multilayer method on ceramic sintered body in (a) To explain the manufacturing method, as shown in Figure 1, first a first conductor layer is printed, dried, and fired on a ceramic sintered body that will become a substrate (steps 1 to 3), and then a first insulating layer is printed, dried, and fired (steps 1 to 3). printing, drying, and firing the layer (steps 4 to 6), printing and drying the second insulating layer on top of it (steps 7 and 8), printing and drying the second conductive layer (steps 9 and 10), The second insulating layer is fired all at once (step 11). On this occasion,
The first and second insulating layers are printed so that micro holes called via holes are formed, and the second conductor layer is printed so that the material used for the second conductor layer is filled into the micro holes. The first conductor layer and the second conductor layer
The conductor layer is connected. Next, a third layer is placed on the second conductor layer.
The insulating layer is printed, dried, and fired, and the layers are stacked using the same procedure as for the second insulating layer and subsequent layers (steps 1 to 11). As shown in Figure 2, the manufacturing method of a multilayer board using the printing multilayer method on a green sheet (b) is as follows: First, the first conductor layer is printed on a ceramic green sheet that will become the substrate after firing. Dry (steps 12 and 13), then print and dry the first insulating layer thereon (steps 14 and 15), and then print and dry the second conductor layer and second insulating layer (steps 16 to 15). 19) After that, the same procedure is repeated for the number of layers (steps 12 to 19), and the green sheet, conductor layer, and insulating layer are fired all at once (step 20). In the method for manufacturing a multilayer board using the green sheet lamination multilayer method (c), as shown in FIG. 24) Print and dry conductor layers with different patterns (steps 25 to 30). Next, a desired number of green sheets with different conductor patterns are laminated (step 31), crimped under moderate pressure and temperature (step 32), cut to desired external dimensions, and fired (step 31). 33, 34). Electrical conduction between each conductor layer is achieved by conductors filled in micropores in the green sheet. In both manufacturing methods (b) and (c), the thick film of the top layer is formed after baking the substrate (steps 21 and 35). Comparing the three manufacturing methods (a), (b), and (c), (a)
Although it is possible to form multiple layers using a relatively simple technique, the practical limit on the number of layers is 4 to 6 layers, and a larger number of layers would result in severe surface irregularities and would not be practical. In (b), the process can be streamlined by firing the green sheet, printed insulating layer, and conductive layer at the same time. However, in (b) as well as (a), as the number of layers increases, the surface unevenness increases, so the limit number of layers is still 4.
~6 layers. The number of layers in (c) is theoretically possible to be infinite, and in reality, multilayer substrates with about 30 to 40 layers have been reported. However, manufacturing them requires extremely advanced technology and there are many process issues. Among the above three manufacturing methods (a), (b), and (c), the present invention relates to the green sheet lamination multilayer method (c). The prior art will be described in more detail with reference to FIG. (First example of conventional technology) First, micropores that will become via holes are formed in different patterns on multiple green sheets made of a mixture of alumina powder and organic matter molded to a predetermined thickness (steps 22 to 24). , print and dry conductor layers with different patterns (steps 25 to 30). W and Mo are mainly used as conductor materials. Filling the via holes with conductive material may be performed simultaneously with the conductor printing process (steps 25 to 27), or the via holes may be filled with the conductive material alone prior to the printing process. After the conductors are dried, a predetermined number of green sheets each having a different conductor pattern are laminated (step 31), and the sheets are pressed together at an appropriate temperature (step 32). Next, cut to the desired external dimensions (step 33), and approximately
Calcinate in a reducing atmosphere at 1600℃ (step 34),
It becomes a multilayer board. The fired substrate is thoroughly cleaned and then proceeds to the step of forming a thick film for the uppermost layer (step 35). (Second example of prior art) As described in the "Multilayer Ceramic Substrate" disclosed in Japanese Patent Publication No. 59-22399, first, a composite composition of glass material and alumina material and a mixture of organic matter are made to a predetermined thickness. Different patterns of microholes are formed in each of the formed green sheets (steps 22 to 24), and conductor layers with different patterns are printed and dried (steps 25 to 30). Single elements such as Ag, Au, Pd, and Pt, or alloys thereof, are used as conductor materials. Filling the via holes with conductive material may be performed simultaneously with the conductor printing process (steps 25 to 27), or the via holes may be filled with the conductive material alone prior to the printing process. After the conductors are dried, a predetermined number of green sheets each having a different conductor pattern are laminated (step 31), and the sheets are pressed together at an appropriate temperature (step 32). next,
Cut to desired external dimensions (step 33) and heat to 700℃~
It is fired in air at 1400°C (step 34) to become a multilayer substrate. The fired substrate is thoroughly cleaned and then proceeds to the step of forming a thick film for the uppermost layer (step 35). Problems to be Solved by the Invention However, in the first example of the prior art as described above, the firing temperature was high and a reducing atmosphere was used, resulting in high equipment costs and inconvenience in handling. Also,
Since alumina is used as the green sheet material and the firing temperature is high, only high melting point metals such as W and Mo can be used as the conductor material, resulting in a problem of high conductor resistance. . In addition, in the second example of the prior art, although the problems of the first example can be solved, it has the disadvantage that controlling the firing shrinkage rate is more difficult than with alumina alone due to the number of composite compositions made of glass material and alumina material, and the yield rate is lower. There was a problem that the value was low. Incidentally, the variation in the firing shrinkage rate of the multilayer substrate according to the first example was ±0.5% to ±1.0%, and the firing shrinkage rate of the multilayer substrate according to the second example was ±1.0% to ±2.5%. In view of the above problems, the present invention uses Ag as a conductor material.
We use low melting point metals with low resistance such as Au, Pd, Pt, etc. or their alloys, and the firing temperature is low, allowing firing in air to reduce equipment costs.
The object of the present invention is to provide a ceramic multilayer substrate which is easy to handle and can be fired at a low temperature in air and has a variation in firing shrinkage of less than ±1.0%. Means for Solving the Problems In order to solve the above problems, the ceramic multilayer substrate of the present invention contains SiO 2 5-55% by weight, B 2 O 3 1-30% by weight, Li 2 in terms of oxides. At least one of O, Na 2 O, K 2 O
0.01-10% by weight, at least one of MgO, CaO, ZnO, BaO
The basic composition has a composition of 0.05 to 25% by weight, and also contains at least one of Al 2 O 3 , ZrO 2 , and TiO 2 in terms of oxides.
The insulating layer is formed from a dielectric composition containing 15 to 65% by weight of additives. Function The ceramic multilayer substrate of the present invention has a temperature of approximately 870°C to 980°C.
The insulating layer is formed of a dielectric composition that can be sintered at a low temperature of .degree. C., and exhibits sufficient characteristics as a ceramic substrate for forming electronic circuits. In the present invention, low melting point metals such as Ag, Au, Pd,
It is possible to use a single element such as Pt or an alloy thereof, and since these metals are difficult to oxidize even in the air, a reducing firing atmosphere is unnecessary, and Au and Ag have lower resistance values than W and Mo. Therefore, low-temperature firing in air reduces equipment costs and facilitates handling. Furthermore, since the ceramic multilayer substrate of the present invention has a variation in firing shrinkage rate of less than ±1.0, the yield is high and mass production is good. The reasons for the limitations in the composition of the present invention are as follows. SiO 2 is the basic composition constituting the substrate and the main material for forming glass. If the SiO 2 content is less than 5%, the firing temperature will be high, making it impossible to use low melting point metals such as Ag, Au, Pt, and Pd as internal conductors, and the variation in firing shrinkage rate will increase. Also, SiO 2 is 55
If it exceeds %, the bending strength becomes too small, and the firing shrinkage rate also varies greatly, making it impractical as a substrate. B 2 O 3 is also the basic composition of the substrate configuration,
If B 2 O 3 is less than 1%, it becomes water-absorbent and has low bending strength. Moreover, if B 2 O 3 exceeds 30%, the ceramic will be significantly deformed during sintering. MgO, CaO, ZnO, and BaO are added to improve the sinterability of the substrate, control the coefficient of thermal expansion, and improve the dielectric loss tangent. MgO, CaO, ZnO,
If at least one type of BaO is less than 0.05%, the sinterability is insufficient, and if it exceeds 25%, the dielectric loss tangent becomes large, which is not preferable. The coefficient of thermal expansion is controlled in various ways depending on the use of the substrate, but when used as a normal thick film hybrid integrated circuit, especially when forming a circuit using thick film conductor paste and thick film resistor paste, the coefficient of thermal expansion of alumina is 6.0 to 6.5 × 10. -6 /°C, and when the silicon chip of the IC is directly mounted on the substrate, it is preferable to match the coefficient of thermal expansion of silicon, 4×10 -6 /°C. It is difficult to judge the quality of a substrate based on the coefficient of thermal expansion alone, but a substrate with a value that is significantly different from both values cannot be put to practical use. K 2 O, Na 2 O, and Li 2 O are added to improve the sinterability of the substrate, prevent water absorption, and suppress deformation of the substrate. If at least one of K 2 O, Na 2 O, and Li 2 O is less than 0.01%, the substrate deforms significantly.
The board warps significantly. If at least one of K 2 O, Na 2 O, and Li 2 O exceeds 10%, sintering will be insufficient and water absorption will occur. Al 2 O 3 , ZrO 2 , and TiO 2 are used as fillers for substrates, and are added mainly to improve bending strength and suppress variations in firing shrinkage rate. At least one of Al 2 O 3 , ZrO 2 , TiO 2
If it is less than 15%, the bending strength is too small and the firing shrinkage rate varies too much to be of practical use. Also, Al 2 O 3 ,
If at least one of ZrO 2 and TiO 2 exceeds 65%, the sintering temperature will be high and the sintering will be insufficient, resulting in water absorption, and the bending strength will also decrease. Examples Examples of the dielectric composition for multilayer substrates of the present invention will be described below. First, when preparing the glass, weigh each raw material of the basic composition and adjust the batch so that it has the composition shown in Table 1 below.
It is melted by heating for 1 to 3 hours at a temperature of 0.degree. C., and a glass plate is formed by, for example, a roll-out method. Next, this glass plate is crushed with an alumina ball etc. to an average particle size of 0.5~
The dielectric composition of the present invention is produced by forming the powder into a powder of 5 μm and adding additives having approximately the same particle size. Note that the raw material powder used in this case is expressed in terms of oxides for clarity, but minerals, oxides, carbonates,
Of course, it can also be used in the form of hydroxide or the like by conventional methods. Next, an example of a method for manufacturing a ceramic multilayer substrate by a green sheet lamination multilayer method using the dielectric composition thus obtained will be described. First, 10 parts by weight of polyvinyl butyral and 6 parts by weight of dibutyl phthalate were added to 100 parts by weight of the above composition.
parts by weight, 0.4 parts by weight of glycerin monooleate,
20 parts by weight of 1-1-1 trichloroethane and 39 parts by weight of isopropyl alcohol were added and mixed in a ball mill for 24 hours to prepare a slurry. Using this slurry, a green sheet with a thickness of 0.1 mm was produced on a polyester film by the doctor blade method, and after sufficient aging, micropores that would become via holes were formed by mechanical processing. Next, this via hole was filled with a conductive material by a printing method using a metal mask. The conductor material used was Au, and its melting point was 1062°C. Next, a conductive layer was printed on a green sheet using the same conductive material and dried. via hole pattern,
Multiple green sheets, each with a different printed conductor pattern, were brought together under pressure of 200 kg/cm 2 at a temperature of 80°C. Next, after cutting the outer shape, it was fired at a maximum temperature of 870 to 1340°C for a maximum temperature holding time of 60 minutes. After the fired multilayer substrate was ultrasonically cleaned with pure water, a thick film was formed on the top layer on the front and back to complete the substrate, which can function as an electronic circuit. Table 1 shows the characteristics of the substrates produced by the above manufacturing method according to the composition of the dielectric composition. As for the characteristics, the bending strength, water absorption rate, and dielectric loss tangent were measured for the substrate that functions as an electronic circuit, and the results are shown in Table 1. In addition, the sintering temperature in the same table is determined by estimating the approximate sintering temperature for each composition in advance from differential thermal analysis, and the sintering temperature at which the water absorption rate is 0.0% and the bending strength is maximum. selected. Regarding the presence or absence of warpage deformation, the external shape was visually observed after the substrate was sintered, and those with irregularities and warp undulations on the surface of the substrate, as well as large deformations, were determined to be unsuitable for practical use.

【表】【table】

【表】 * 比較例
参考として第2表に従来の材料である96%
Al2O3の特性を示す。
[Table] * Comparative example For reference, Table 2 shows 96% of conventional materials.
Shows the properties of Al 2 O 3 .

【表】 第1表,第2表、及び以上述べたように、本発
明による組成物は870〜980℃と低温で焼成でき、
しかも電子回路形成用のセラミツク基板としての
特性を充分発揮しており、その特度は従来の材料
である96%Al2O3に比較し、より優れている。 発明の効果 以上の説明より明らかなように、本発明の材料
を使用することにより低融点Ag,Au,Pd,Pt
等の単体あるいはこれらの合金の使用が可能とな
り、これら金属は空気中でも酸化しない為還元性
雰囲気は不必要であり、またAu,Agは抵抗値が
W,Moよりも小さい。従つて空気中低温焼成に
より設備費用も小さくて済み、取り扱いも簡便に
なる。 さらに、本発明のセラミツク多層基板は焼成収
縮率のばらつきが±1.0%未満である為、歩留り
が高く量産性が良好である。
[Table] As shown in Table 1 and Table 2, and as described above, the composition according to the present invention can be fired at a low temperature of 870 to 980°C,
Moreover, it fully exhibits the characteristics as a ceramic substrate for forming electronic circuits, and its characteristics are superior to that of 96% Al 2 O 3 , which is a conventional material. Effects of the invention As is clear from the above explanation, by using the material of the present invention, low melting point Ag, Au, Pd, Pt
These metals do not oxidize even in the air, so there is no need for a reducing atmosphere, and the resistance values of Au and Ag are smaller than those of W and Mo. Therefore, low-temperature firing in air reduces equipment costs and makes handling easier. Furthermore, since the ceramic multilayer substrate of the present invention has a variation in firing shrinkage rate of less than ±1.0%, it has a high yield and is suitable for mass production.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はセラミツク焼結体上での印刷多層法に
よる多層基板の製造プロセスを示すフローチヤー
ト、第2図はグリーンシート上での印刷多層法に
よる多層基板の製造プロセスを示すフローチヤー
ト、第3図はグリーンシート積層多層法による多
層基板の製造プロセスを示すフローチヤートであ
る。
Figure 1 is a flowchart showing the manufacturing process of a multilayer board by printing multilayer on a ceramic sintered body, Figure 2 is a flowchart showing the manufacturing process of a multilayer board by printing multilayer on a green sheet, and Figure 3 is a flowchart showing the manufacturing process of a multilayer board by printing multilayer on a green sheet. The figure is a flowchart showing the manufacturing process of a multilayer board using the green sheet lamination multilayer method.

Claims (1)

【特許請求の範囲】 1 酸化物に換算して、 SiO2 5〜55重量%、 B2O3 1〜30重量%、 Li2O,Na2O,K2Oのうち少なくとも1種
0.01〜10重量%、 MgO,CaO,ZnO,BaOのうち少なくとも1
種 0.05〜25重量%、 Al2O3,ZrO2,TiO2のうち少なくとも1種
15〜65重量% の組成からなる誘電体組成物により絶縁層を形成
したセラミツク多層基板。
[Claims] 1. In terms of oxide, 5 to 55% by weight of SiO 2 , 1 to 30% by weight of B 2 O 3 , and at least one of Li 2 O, Na 2 O, and K 2 O
0.01-10% by weight, at least one of MgO, CaO, ZnO, BaO
Species 0.05-25% by weight, at least one of Al 2 O 3 , ZrO 2 , TiO 2
A ceramic multilayer substrate in which an insulating layer is formed from a dielectric composition having a composition of 15 to 65% by weight.
JP18691985A 1985-08-26 1985-08-26 Ceramic multilayer substrate Granted JPS6247196A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18691985A JPS6247196A (en) 1985-08-26 1985-08-26 Ceramic multilayer substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18691985A JPS6247196A (en) 1985-08-26 1985-08-26 Ceramic multilayer substrate

Publications (2)

Publication Number Publication Date
JPS6247196A JPS6247196A (en) 1987-02-28
JPH0369197B2 true JPH0369197B2 (en) 1991-10-31

Family

ID=16196991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18691985A Granted JPS6247196A (en) 1985-08-26 1985-08-26 Ceramic multilayer substrate

Country Status (1)

Country Link
JP (1) JPS6247196A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0193436A (en) * 1987-09-30 1989-04-12 Nippon Electric Glass Co Ltd Glass composition for substrate material
JP4988375B2 (en) * 2007-02-22 2012-08-01 日本板硝子株式会社 Glass composition

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50119814A (en) * 1974-03-08 1975-09-19
JPS5563900A (en) * 1978-11-08 1980-05-14 Fujitsu Ltd Multilyaer ceramic circuit board
JPS5711847A (en) * 1978-02-06 1982-01-21 Ibm Nonporous glass-ceramic body
JPS5817695A (en) * 1981-07-24 1983-02-01 株式会社日立製作所 Multilayer circuit board and method of producing same
JPS58151345A (en) * 1982-02-26 1983-09-08 Asahi Glass Co Ltd Glass composition with low dielectric constant
JPS59995A (en) * 1982-06-16 1984-01-06 富士通株式会社 Method of producing copper conductor multilayer structure
JPS59162169A (en) * 1983-03-04 1984-09-13 株式会社日立製作所 Ceramics and multilayer distribution panel
JPS608229A (en) * 1983-06-27 1985-01-17 Agency Of Ind Science & Technol 7-substituted norbornadiene-cyclodextrin clathrate compound and its preparation
JPS60103075A (en) * 1983-11-01 1985-06-07 旭硝子株式会社 Composition for ceramic substrate
JPS60137884A (en) * 1983-12-26 1985-07-22 株式会社日立製作所 Manufacture of ceramic multi-layer wiring circuit substrate
JPS61122159A (en) * 1984-11-16 1986-06-10 太陽誘電株式会社 Insulative ceramic composition
JPS61186248A (en) * 1985-02-13 1986-08-19 Nippon Electric Glass Co Ltd Glass ceramic
JPS61275161A (en) * 1985-05-29 1986-12-05 株式会社ノリタケカンパニーリミテド Low temperature burnt multilayer ceramic substrate

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50119814A (en) * 1974-03-08 1975-09-19
JPS5711847A (en) * 1978-02-06 1982-01-21 Ibm Nonporous glass-ceramic body
JPS5563900A (en) * 1978-11-08 1980-05-14 Fujitsu Ltd Multilyaer ceramic circuit board
JPS5817695A (en) * 1981-07-24 1983-02-01 株式会社日立製作所 Multilayer circuit board and method of producing same
JPS58151345A (en) * 1982-02-26 1983-09-08 Asahi Glass Co Ltd Glass composition with low dielectric constant
JPS59995A (en) * 1982-06-16 1984-01-06 富士通株式会社 Method of producing copper conductor multilayer structure
JPS59162169A (en) * 1983-03-04 1984-09-13 株式会社日立製作所 Ceramics and multilayer distribution panel
JPS608229A (en) * 1983-06-27 1985-01-17 Agency Of Ind Science & Technol 7-substituted norbornadiene-cyclodextrin clathrate compound and its preparation
JPS60103075A (en) * 1983-11-01 1985-06-07 旭硝子株式会社 Composition for ceramic substrate
JPS60137884A (en) * 1983-12-26 1985-07-22 株式会社日立製作所 Manufacture of ceramic multi-layer wiring circuit substrate
JPS61122159A (en) * 1984-11-16 1986-06-10 太陽誘電株式会社 Insulative ceramic composition
JPS61186248A (en) * 1985-02-13 1986-08-19 Nippon Electric Glass Co Ltd Glass ceramic
JPS61275161A (en) * 1985-05-29 1986-12-05 株式会社ノリタケカンパニーリミテド Low temperature burnt multilayer ceramic substrate

Also Published As

Publication number Publication date
JPS6247196A (en) 1987-02-28

Similar Documents

Publication Publication Date Title
JPH0343786B2 (en)
JPH0523519B2 (en)
JPH0992983A (en) Manufacture of ceramic multilayer board
JPH0361359B2 (en)
JPH0971472A (en) Production of glass ceramic substrate
JPH0369197B2 (en)
JP2004022706A (en) Method for manufacturing ceramic multilayered substrate
JPH0369196B2 (en)
JPH0513100B2 (en)
JP3807257B2 (en) Manufacturing method of ceramic parts
JP2004256346A (en) Glass-ceramic composition, glass-ceramic sintered compact, its producing method, wiring board using the sintered compact body, and its mounting structure
JP2699919B2 (en) Multilayer wiring board, method for manufacturing the same, and method for manufacturing sintered silica used therefor
JP3229021B2 (en) Circuit board
JPH02141458A (en) Low-temperature calcined ceramic multilayered base plate and production thereof
JPH0426799B2 (en)
JPS61266349A (en) Dielectric composition
JPS61264603A (en) Dielectric composition
JPH1125754A (en) Manufacture of copper-metallized composition and glass-ceramic substrate
JPS6231904A (en) Dielectric composition
JPH0250638B2 (en)
JPH0444613B2 (en)
JPH0477442B2 (en)
JPH0797703B2 (en) Ceramic multilayer board
JPH0428121B2 (en)
JPS58108792A (en) Multilayer circuit board and method of producing same