JPH0369127A - Manufacture of field-effect transistor - Google Patents

Abstract

PURPOSE:To form a low-resistance source resistance with good uniformity and to obtain a manufacturing method of a compound semiconductor junction- type FET which does not generate a short channel effect by a method wherein a Schottky electrode is formed partly on a third semiconductor layer, one part of the third semiconductor layer is removed to be filled with a low-resistance layer and, after that, an ohmic electrode is formed. CONSTITUTION:A second semiconductor layer 4 composed of AlAs or AlGaAs is formed on a substrate or first thin films GaAs 1 to 3; third semiconductor layers 5, 6 containing GaAs are formed on it; a Schottky electrode 11 is formed partly on them. In addition, one part of the third semiconductor layers 5, 6 is removed selectively down to the interface with the second semiconductor 4; low-resistance GaAs or InAs or a mixed crystal 8 of them is filled selectively; after that, ohmic electrodes 9, 10 are formed. For example, individual layers 2 to 6 as shown in the figure are formed one after another on a GaAs substrate 1; parts to be used as a source and a drain are removed down to the interface with the layer 4 by making use of an SiO2 layer 7 as a mask. Then, an n-type InAs layer 8 is filled; a source electrode, a drain electrode and a gate electrode 9 to 11 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a method for manufacturing a compound semiconductor field effect transistor.

[Conventional technology]

Compound semiconductors, especially gallium arsenide, have a high density of surface units, making it difficult to obtain a good insulating film.
A field effect transistor (hereinafter abbreviated as FBT) having a metal-insulator-semiconductor structure is not used, but a MES-FET using a metal-semiconductor Schottky interface is used. It is known that even in this MES-FET, the performance of the FBT deteriorates due to depletion of carriers in the channel layer and increase in resistance between the source and gate.

One way to prevent this is to use epitaxial growth to form a low concentration n layer and a high concentration n+ layer, and then partially remove the n+ layer so that the gate layer is placed on the n layer and the source and drain electrodes are placed on the n+ layer. By forming on top of the sauce
A method of lowering the resistance between gates is known.

FIG. 2 is a schematic cross-sectional view of an element portion showing an example of such an FET. An n-type GaAs layer 3 as an n-channel layer is provided on a semi-insulating gallium arsenide (GaAs) substrate 1, and a gate electrode 11 is provided on the n-type GaAs layer 3.
A source electrode 9 and a drain electrode 10 are provided on the n''7i18.

In addition, as reported on page 531 of the 46th Annual Conference of the Japan Society of Applied Physics, published in 1985, the source and drain regions are partially removed and the n+ layer is selectively grown, and the source and drain electrodes are grown as an n+ layer. There is a method of lowering the resistance between the source and train by forming it on a type-selective growth layer.

Another method is the 1983 edition of the ``Inisnischy Digest of Technical Papers.''
(”TSSC Coigest of TeChniCa
As reported on page 44 of ``Research Papers'', there is a known method of lowering the resistance between the source and gate by forming a heavily doped n+ layer close to the gate on both sides of the gate region. .

[Problem to be solved by the invention] However, forming a high concentration n+ layer by etching,
In the method of forming the gate layer by partially removing the layer, as the gate length becomes shorter, the reproducibility of the etching depth and etching shape when removing the n+ layer in the gate area deteriorates, and the etching depth and etching shape reproducibility deteriorates. Schottky characteristics deteriorate.

Furthermore, variations within the substrate surface also increase.

Even in the method of selectively growing the source and train portions by etching, as the gate length becomes shorter, the variation in gate threshold value and source resistance increases due to non-uniform etching control.

Furthermore, in FETs in which an n+ layer is formed by ion implantation, etc., as the gate length becomes shorter, the effective gate length becomes shorter due to lateral diffusion of the n+ layer, resulting in fluctuations in gate threshold voltage and lower mutual conductance. , so-called short channel effects such as an increase in train conductance are induced.

An object of the present invention is to solve these conventional problems and provide a method for manufacturing a compound semiconductor junction field effect transistor, which forms a low-resistance source resistance with good uniformity and eliminates the short channel effect. be.

[Means to solve the problem]

In order to achieve the above object, in the method for manufacturing a field effect transistor according to the present invention, the first
a step of forming a second semiconductor layer made of aluminum arsenide or aluminum gallium arsenide on gallium arsenide, forming a third semiconductor layer containing gallium arsenide thereon, and partially forming a Schottky electrode thereon. selectively removing a part of the third semiconductor layer up to the interface with the second semiconductor layer, and selectively filling low-resistance gallium arsenide or indium arsenide, or a mixed crystal thereof. The method includes a step of implanting the ohmic electrode, and a step of forming an ohmic electrode.

[Effect]

The present invention attempts to reduce the source resistance by etching and embedding a low resistance layer. Here, by using selective etching of only gallium arsenide, it is possible to form an etched surface with no rJA dependence on the etching rate. Furthermore, the source resistance can be reduced by burying indium arsenide, gallium arsenide, or a mixed crystal thereof to form a low resistance layer. Aluminum gallium arsenide generally has a high resistance, but by making it a thin film, the resistance can be lowered by tunneling current. Therefore, the non-uniformity of etching and deterioration of Schottky characteristics seen in conventional under-gate etching methods do not occur, and the threshold fluctuation and train resistance increase due to short channel effects often seen in methods using ion implantation do not occur. There is no problem.

[Jikho noodles example]

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIGS. 1(a) to 1(e) are schematic sectional views of an element portion showing an embodiment of the present invention in the order of steps.

First, as shown in FIG. 1(a), a non-doped gallium arsenide layer 2 with a thickness of 5000 Å is formed on a gallium arsenide substrate 1 having a (100) plane by molecular beam epitaxial method.
00 pieces (7) 3 xlolscn-'F-hinkshita n
Type gallium arsenide layer 3.30 undoped aluminum gallium arsenide layer 4 (composition of aluminum is 0.3)
, a non-doped gallium arsenide layer of 75 mm and a non-doped aluminum gallium arsenide layer 6 of 300 mm are sequentially formed.

Next, as shown in FIG. 1(b), using the arsenic dioxide layer 7 as a mask, portions of the non-doped gallium arsenide layer 5 that will become the source and drain are removed by etching to the middle.

Next, the substrate 1 is carried into a molecular beam epitaxial apparatus, the substrate temperature is raised to 700''C, and the non-doped potassium arsenide layer 5 is thermally etched to the interface of aluminum gallium arsenide N4 to be completely removed (the first (C)), at this time, the aluminum gallium arsenide layer 4 is a stopper (5t
(opper) role.

Next, lower the substrate temperature to 550℃ and 2X 10"cj n
A type-doped indium arsenide layer 8 is buried in the etched area (see FIG. 1(1)).

A source electrode 9, a drain electrode 10, and a gate electrode 11 are formed on the selective epitaxial layer formed in this manner, and on the portion not to be etched.

In the manufacturing process of the present invention, the source voltage l#! Since the drain electrode 9 and the drain electrode 10 are formed on the low resistance indium arsenide layer 8, their contact resistance is reduced. Further, at this time, since the etching automatically stops at the aluminum gallium arsenide layer 4, a uniform etched surface is formed. Further, the thickness of the aluminum gallium arsenide layer 4 is set to 30 μm, so that electrons can flow through the aluminum gallium arsenide layer 4 as a tunnel current. Therefore, the manufactured transistor has low resistance ohmic characteristics, and it has become possible to suppress variations in transistor characteristics within the substrate surface.

In the above embodiments, an FET with an i-structure in which the channel is doped has been explained, but an FET with an aluminum gallium arsenide layer doped and a cap (Cap) have been described.
It is also applicable to FETs in which layers are doped.

Further, the film thickness and doping level in the embodiment may be changed to appropriate values.

Also, other etching methods or epitaxial growth methods may be used.

〔Effect of the invention〕

As explained above, according to the method of the present invention, it is possible to form source electrodes and drain electrodes with low source resistance with high yield in the manufacture of gallium arsenide field effect transistors, and productivity can be improved. It becomes possible.

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are schematic sectional views of an element portion showing an embodiment of the present invention in the order of steps, and FIG. 2 is a schematic sectional view of an element portion of a conventional field effect transistor. 1... Gallium arsenide substrate 2... Non-doped gallium arsenide layer 3... N-type gallium arsenide layer 4... Non-doped aluminum gallium arsenide layer 5...
・Non-doped potassium arsenide layer 6...Non-doped aluminum gallium arsenide layer 7...
・Arsenic dioxide layer 8...N-type indium arsenide layer 9...Source electrode 10...Drain electrode 1
1...Gate electrode

Claims (1)

[Claims] (1) Forming a second semiconductor layer made of aluminum arsenide or aluminum gallium arsenide on the first gallium arsenide of the substrate or thin film, and forming a third semiconductor layer containing gallium arsenide thereon; forming a partial Schottky electrode thereon, selectively removing a portion of the third semiconductor layer up to the interface with the second semiconductor layer, and forming a low-resistance gallium arsenide, indium arsenide, or A method for manufacturing a field effect transistor, comprising the steps of selectively embedding those mixed crystals and forming an ohmic electrode.