JPH0368047A - Key access control system - Google Patents

Abstract

PURPOSE:To simplify an interface by providing a first port to send out a request for key access, and a second port to send out a request for data access in a memory controller and accessing the data and key of a main storage by one request. CONSTITUTION:In the memory controller 121, the first port 141 is provided to store the key, which holds contents corresponding to the prescribed amount of data, in the main storage device 111 and to send out the request for key access and the second port 151 is provided to send out the request for data access. When the request to simultaneously instruct the data access and key access is inputted from a processor 131 to the controller 121 and the two access can be executed together, a priority control means 161 applies the start permission of the request to the ports 141 and 151.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , Configuration and operation of the embodiments■, Summary of the embodiments■1 Modifications of the invention Effects of the invention [Summary] In a computer system having a key corresponding to each page, this data is stored in parallel with the data in the main memory. Regarding a key access control method in which a key is accessed, for the purpose of simplifying the interface and reducing the number of signal lines, the present invention includes at least one main storage device, and a storage control device that permits access to the main storage device; A processing device that issues a request instructing access, a key for holding the contents corresponding to a predetermined amount of data, and a key that accesses this key stored in the main storage device. In the access control scheme, the storage controller has at least one first port that sends a request to access a key, and at least one first port that sends a request to access data stored in main storage. When a request instructing data access and key access is input from the processing device to the second port at the same time, and both of these two accesses are possible, the request is sent to the first port and the second port. and priority control means for granting permission to start.

(Industrial Application Field) The present invention relates to a key access control method in which the keys are accessed in parallel with data in the main memory in a computer system having a key corresponding to each page. .

[Conventional technology]

Generally, in computer systems that use virtual memory,
Each of the main storage device and auxiliary storage device is divided into blocks of a predetermined capacity (for example, 4 bytes) called pages, and storage space in units of pages is allocated to application programs of each processing device. 0
For example, when a processing device accesses the data of a certain page, it directly accesses the data for pages in main memory, and accesses the data for pages not in main memory by accessing less frequently used pages in main memory. After storing the page in the auxiliary storage device, the page is transferred to the main storage device and the data is accessed. By performing page-by-page replacement in this manner, each processing device can access data at high speed without being aware of the hardware that stores the data.

By the way, the above-mentioned main storage device is shared by a plurality of processing devices in a computer system, and it is necessary to protect the contents corresponding to each processing device (or application program). As a method for protecting this content, there is a method of associating a key with each page and referring to and updating the key when accessing the page.

FIG. 7 shows an example of the format of the key described above.

In the figure, rACCJ indicates an access bit consisting of a plurality of bits, and a value unique to the application program using that page is written.

Further, "F" indicates a fetch protection bit, that is, a read protection bit, "R" indicates a reference bit, that is, a reference focus, and rC, 1 indicates a change bit, that is, a change bit.

When read protection bit F is set (1"), it indicates that reading of data in the corresponding page is prohibited. When reference bit R is set, data in this page is prohibited. has been accessed at least once.

Further, when the change bit C is set, it indicates that the data in this page has been changed at least once, that is, data has been written.

For example, in a computer system in which multiple processing units and one or more main storage devices are connected via a storage control device, each main storage device has an area for storing data and an area for storing keys. be prepared for. Alternatively, a key-dedicated main storage device is provided separately from the main storage device that stores data.

When each processing unit of such a computer system accesses data in the main memory, the key is accessed prior to accessing the data. After accessing the key and setting the reference bit R, a fetch request is sent to the appropriate main memory.

Also, after accessing the key and setting the reference bit R and change bit C, a store request is sent to the corresponding main storage device. Note that access bits A and CC are checked only when the page to be accessed is changed.

[Problem to be solved by the invention]

By the way, in the conventional method described above, it is necessary to issue an independent request to set the key reference bit R1 change bit C for each data fetch or store access, and the processing device There is a problem in that the interface between the storage controller and the storage controller becomes complicated.

For example, the operating system (O3) controlled by each processing unit needs to prepare a dedicated request for sending the reference focus (R2 change bin) C, in addition to requests for fetch and store access. Complex control is required to use each request properly.

In addition, the storage control device that receives each such request performs priority control according to each request and creates a startup signal for the corresponding main storage device, and generates a startup signal dedicated for key access. As a result, there was a problem in that the number of signal lines within the storage control device increased.

An actual storage control device is composed of a plurality of LSIs, and it is desired to reduce the number of signal lines due to limitations on the number of input/output bins.

The present invention was created in view of these points, and an object of the present invention is to provide a key access control method that can simplify the interface and reduce the number of signal lines.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the key access control method of the present invention.

In the figure, the key access control method of the present invention includes at least one main storage device 111 and this main storage device 111.
Storage control device 121 that performs permission to start access to
and a processing device 131 that issues a request instructing access, and is provided with a key for holding the contents corresponding to a predetermined amount of data, and for this key stored in the main storage device 111. Make access.

The storage control device 121 also includes at least one first port 141 that sends a request to access a key, and at least one first port 141 that sends a request to access data stored in the main storage device 111. When a request instructing simultaneous data access and key access is input from the processing device 131 to the first port 141 and the second port 151 when both of these two accesses are possible. A priority control means 161 is provided for granting permission to start the request.

As a whole, the main storage device 111 is configured to access data and keys in the main storage device 111 in response to a single request input from the processing device 131 .

[For production]

At least one main storage device 111 stores data and a key corresponding to a predetermined amount of this data and for protecting the contents of the data.

When the processing device 131 outputs a request instructing data access and key access at the same time, the priority control means 161 performs priority control to determine whether each access is possible or not based on this request. When both accesses are possible, the priority control means 161 grants start permission to the first port 141 and the second port 151.

The first port 141 that received permission to start sends a request to access the key to the corresponding main storage 111, and the second port 151 that received permission to start sends a request to the corresponding main storage 111. A request for accessing data is sent to the device 151.

In the present invention, by performing data access and key access in one request, the processing device 13
1 and the storage control device 121.

In addition, in response to this request, if both accesses to data and keys are possible, a common start permission is output, thereby making it possible to share signals related to start permission for data access and key access. can.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a computer system in an embodiment to which the key access control method of the present invention is applied. Further, FIG. 5 shows the configuration of a storage control device according to an embodiment.

1. The correspondence between the embodiments of the present invention and FIG. 1 will now be shown.

The main storage device 111 is a main storage device i (MSU) 211.
Corresponds to 213, 215, 217.

The storage control device 121 is a storage control device (MCU) 221
corresponds to

The processing device 131 includes a central processing unit (CPU) 231.2
33. It corresponds to the input/output control device (IOP) 241.

The first port 141 is the port 555, 556° 557
．． It corresponds to 558.

The second port 151 is a port 551, 552, 553
．． It corresponds to 554.

The priority control means 161 corresponds to the priority control section 541.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

■ In Fig. 2, 211, 213, 215, and 217 are the main storage unit (MSU), and 221 is the storage control unit (MCU).
), 231 and 233 are central processing units (CPLI),
241 each indicates an input/output control device (IOP).

Other components are connected to the storage control device 221, and requests output from each processing device are sent to the storage control device 221.
21 to the corresponding main storage device.

The input/output control device 241 includes an auxiliary storage device and other input/output devices (keyboard, display, etc.) that are not shown.
Assume that it is connected.

FIG. 3 shows the main storage device 211 of the computer system described above.
The state of interleaving at ~217 is shown. The same figure (a
), (b), (C), (d) are the main storage device 21
1 to 217, respectively. Further, the bit length of data read and written by each access is 8 bytes.

Each main storage device has a data area (DATA) that stores data that is read and written through normal access, and a key area (KEY) that stores the key corresponding to any page (which may be another main storage device). Contains.

Each data area is interleaved into a plurality of banks, and the relationship between each bank and address is shown in the figure. That is, each bank of the main memory device 211 has an address 32 n
(n=o, 1...), and each address 8n corresponds to a different bank.

Similarly, each bank of the main memory 213 has an address 32n.
+8, each bank of the main memory 215 has an address 32n.
+16, each bank of main memory 217 has address 32
They correspond to n+24, respectively.

Therefore, when accessing consecutive addresses (addresses every 8 bytes since access is possible in units of 8 bytes), these consecutive addresses correspond to each adjacent main memory device, and the corresponding main memory Even when the device returns to the same main memory after completing one cycle, it corresponds to adjacent banks, so there is no contention for access to the same bank, and access efficiency can be improved.

Further, addresses for key areas are also allocated to each of the key areas of the main storage devices 211 to 217. The key area of the main storage device 211 is the address 4n (
n=0.1. ), the key area of the main memory 213 is located at address 4n+1 for the key area, and the key area of the main memory 213 is
The key area of the main memory 217 is at the key area address 4n+2, and the key area of the main memory 217 is at the key area address 4n+3.
corresponds to each.

FIG. 4 shows the correspondence between the addresses handled by the central processing unit 231 and the like and the addresses in each of the main storage devices described above.

It is assumed that the bit length of the address handled by each processing device is 32.

Since the data input/output unit is 8 bytes (one address corresponds to 1 byte of data), the lower 4th bit (3rd bit) and 5th bit (4th bit) are used. Then, the corresponding main memory is allocated. Specifically, if the 3rd and 4th bits are OO, they are stored in the main memory 211, if they are 01°, they are stored in the main memory 213, and if they are 10, they are stored in the main memory 211.
5 and “11” correspond to the main storage device 217, respectively.

Furthermore, if the unit of a page is 4 bytes, the address within the page is represented by the lower 12 bits, and the allocation of the main memory that stores the key corresponding to each page is done using the 12th and 13th bits. conduct.

FIG. 5 shows the detailed configuration of the storage control device 221. Note that the configuration in the figure shows a configuration that focuses on a functional part that sends requests input from each processing device to the corresponding main storage device.

In FIG. 5, 511 is a selector, 521° 522
．． 523,524. '525,526,527.528
, 561, 563, 565 are registers, 531, 53
2,533,534,535゜536.537,538
indicates the bus busy detection section, 541 indicates the priority control section, 551, 552, 553, 554, 555, 556.
, 557° and 558 indicate ports, respectively.

Further, FIG. 6 shows the format of a request output from each processing device such as the central processing unit 231.

In the figure, "v" is a valid pit and indicates whether or not this request is valid.

In addition, the rADR3J converts the 32-bit address to rop
cJ indicates an operation code.

Further, rR, /C are flag bits indicating whether to set reference bit R or change bit C;
/C bit "1" corresponds to a set instruction.

A request in such a format is sent to the central processing unit 2.
31,233. It is output from any of the input/output control devices 241 and input to the storage control device 221. A request output from the central processing unit 231 is stored in the register 561 and input to the selector 511. The request output from the central processing unit 233 is sent to the register 5.
63 and manually input to the selector 511.

A request output from the input/output control device 241 is stored in the register 565 and input to the selector 511.

The selector 511 selects and outputs one of the input requests and supplies it to the corresponding registers 521-524 and registers 525-528.

Each of the four registers 521-524 corresponds to a respective data area of the main storage devices 211-217.

For example, if a request output from the selector 511 instructs access to a page area of the main storage device 211, this request (may be only a part of the address necessary for conflict control) is stored in the register 521. .

Similarly, if the request instructs access to a page area of another main storage device, the request is stored in any of the corresponding registers 522-524.

Furthermore, each of the four registers 525 to 528 corresponds to a key area of each of the main storage devices 211 to 217. R in the request output from selector 511
/C bit is °°1″, reference bit R1
Since it is necessary to set at least one of the change bits C, the request (!1 (It may be a part of the address necessary for control).

By the way, as shown in FIG. 4, the main storage devices 211 to 217 corresponding to the data to be accessed are
．． The main memory devices 211 to 217 corresponding to the keys are allocated by the 4th bit, while the main memory devices 211 to 217 corresponding to the keys are allocated by the 12th bit of the address.
．． It is allocated by 13 bits. Therefore, the main memory in which the data to be accessed is stored does not correspond to the main memory in which the key containing the reference bit R2 change bit C to be set upon this access is stored. Therefore, registers 521 to 52
The storage operation to 4 and the storage operation to registers 525-528 are performed separately.

The requests stored in registers 521 to 524 are input to bus busy detection units 531 to 534, respectively.
A check is made to see if the bus line connected to the page area of the corresponding main memory device 211-217 is not in use.

Further, the requests stored in the registers 525 to 528 are input to the bus busy detection units 535 to 538, respectively, to check that the bus lines connected to the key areas of the corresponding main storage devices 211 to 217 are not in use. It will be done.

Furthermore, each output of the bus busy detection units 531 to 538 is input to a priority control unit 541, and competition control of requests between each processing device is performed.

The priority control unit 541 controls data access specified by the request and key access (
A common start permission signal is output only when both the steps (setting of reference bit R1 change bit C) can be performed at the same time. The output start permission signals are input to corresponding ports 551 to 554 and corresponding ports 555 to 558, respectively.

Each of the four ports 551 to 554 is connected to the main storage device 2.
It corresponds to each page area from 11 to 217,
The port that receives this start permission signal sends a request for data access supplied via another route, which will be described later, to the corresponding main storage device. In addition, four ports 555~
Each of 558 corresponds to a key area of the main storage devices 211 to 217, and sends a request for key access supplied via a separate route to the corresponding main storage device.

By the way, requests input from each processing unit such as the central processing unit 231 are processed by a plurality of registers 56.
It is supplied to ports 551-554 or ports 555-558 via any one of ports 1-565.

The plurality of registers 561 are for synchronizing with each bus busy detection unit and the priority control unit 541, and are used to synchronize the start permission signal from the priority control unit 541 to each port and the register 561 at the last stage.
The timing of supplying requests from to each port is consistent. The same applies to the other registers 563 and 565.

In addition, requests supplied to ports 551 to 558 are
Requests supplied from each processing device (see FIG. 6 for the format) are converted into a data access request and a key access request and then supplied. For example, a request in the format shown in FIG. 6 without the R/C bit is supplied to ports 551-554. The port that received the start permission signal sends out this request, and the main storage device that received this request performs operations such as fetch and store on the addressed data according to the operation code. In addition, when specifying addresses in the main memory, 32
Since all bits of the bit address are unnecessary (because the port, that is, the main memory is specified by supplying the start permission signal, and only the addressing in the main memory needs to be specified), only the necessary bits are needed. Extract and use it.

Also, requests supplied to ports 555 to 558 are
Based on the requests supplied from each processing device, the format is converted into a request for key access. R/
If the C bit is 1", that is, setting the key's reference bit R1 change bit C is instructed, and the operation code indicates a fetch, a request to set the reference bit R is created and the port 5
Enter numbers 55-558.

On the other hand, if the R/C bit is 1" and the operation code indicates a store, a request is made to set both the reference bit R and the modified bit C, and Enter.

The port that received the start permission signal sends the above-mentioned key access request to the corresponding main memory, and the main memory that received this request is addressed according to the operation code in the request. The reference bit R or both the reference bit R and the change bit C of the key are set.

(2) Summary of the following: In this way, requests instructing access to both data and keys are sent from the central processing units 231 and 233 and the human output control unit 241 to the storage control unit 221. Based on this request, the storage control device 221 uses the priority control unit 54 to determine whether each access is possible simultaneously.
1, and if possible, the port corresponding to the data access destination among ports 551 to 554, and port 55
A start permission signal is supplied to the port corresponding to the access destination of the key among ports 5 to 558. One port that receives this start permission signal sends a request for data access to the corresponding main storage device, and the other port sends a request for key access to the corresponding main storage device.

Therefore, compared to the case where a dedicated request for key access is prepared and data and keys are accessed separately, the number of requests input/output between each processing unit and the storage control unit 221 can be reduced, and the number of requests input/output between each processing unit and the storage control unit 221 can be reduced. It becomes possible to simplify the interface between devices.

Further, by using a common start permission signal for two types of access, data and key, it is possible to share signal lines, so the number of signal lines can be reduced.

Note that in the embodiment of the present invention described above, each of the main storage devices 221 to 227 is provided with a page area and a key area. It is also possible to provide separate main storage devices for the key area and the key area.

In addition, in the embodiment, requests for data access and requests for key access are simultaneously sent to the same main storage device or different main storage devices. If the same bus is used, it is impossible to output these two accesses at the same time, so the timing of sending the requests is staggered.

Furthermore, in ``correspondence between examples and FIG. 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, data access and key access are performed in one request, thereby reducing the types of requests that are input/output between the processing device and the storage control device. The interface between them can be simplified.

In addition, in response to this request, by outputting a common start permission when both accesses to data and keys are possible, signals related to start permission for data access and key access are shared, and storage control is performed. The number of signal lines within the device can be reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the key access control method of the present invention, Fig. 2 is a configuration diagram of a computer system according to an embodiment to which the key access control method of the present invention is applied, and Fig. 3 is an interleaving diagram of an embodiment. An explanatory diagram, FIG. 4 is an explanatory diagram of addresses in one embodiment, and FIG. 5 is a configuration diagram of a storage control device in one embodiment.
FIG. 6 is an explanatory diagram of requests in one embodiment, and FIG. 7 is an explanatory diagram of keys. In the figure, 111 is a main storage device, 121 is a storage control device, 131 is a processing device, 141 is a first port, 151 is a second port, 161 is a priority control means, 211, 213, 215, and 217 are main memories. Equipment (MSU
), 221 is a storage control unit (MCU), 231.233 is a central processing bag W (CPU), 241 is an input/output control unit (■○P), 511 is a selector, 521.522, 523, 524, 525, 526 .5
27.528, 561, 563, 565 are registers (R
), 531.532,533,534,535,536.5
37, 538 is a bus busy detection unit, 541 is a priority control unit, 551.552, 553, 554, 555, 556.5
57 and 558 are ports. Book, departure'' same ○Z stem cry 2nd floor / 7th story 1st mother kichi 1 sin pa

Claims (1)

[Claims] (1) At least one main storage device (111), a storage control device (121) that allows access to the main storage device (111), and a processing device (131) that issues a request instructing the access. In the key access control method, a key for holding contents corresponding to a predetermined amount of data is provided, and the key stored in the main storage device (111) is accessed. The storage control device (121) has at least one first port (141) that sends a request to access the key, and a first port (141) that sends a request to access the data stored in the main storage device (111). When at least one second port (151) for sending out a request is input from the processing device (131) to simultaneously instruct access to the data and access to the key, and both of these two accesses are possible. the first port (141) and the second port (151).
), and a priority control means (161) for granting permission to start a request to the processing device (131), so that data and keys in the main storage device (111) are accessed by one request input from the processing device (131). A key access control method characterized by being configured as follows.