JPH0365910B2 - - Google Patents
Info
- Publication number
- JPH0365910B2 JPH0365910B2 JP59273466A JP27346684A JPH0365910B2 JP H0365910 B2 JPH0365910 B2 JP H0365910B2 JP 59273466 A JP59273466 A JP 59273466A JP 27346684 A JP27346684 A JP 27346684A JP H0365910 B2 JPH0365910 B2 JP H0365910B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- resin
- thickness
- board
- prepreg
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229920005989 resin Polymers 0.000 claims description 14
- 239000011347 resin Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 7
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 claims description 6
- 239000000203 mixture Substances 0.000 claims description 6
- 229920003192 poly(bis maleimide) Polymers 0.000 claims description 6
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 238000009499 grossing Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 238000013007 heat curing Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 19
- 239000011342 resin composition Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 5
- 239000011889 copper foil Substances 0.000 description 5
- 239000002904 solvent Substances 0.000 description 5
- 238000003475 lamination Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- 239000000843 powder Substances 0.000 description 2
- 238000003825 pressing Methods 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- 229930185605 Bisphenol Natural products 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- IISBACLAFKSPIT-UHFFFAOYSA-N bisphenol A Chemical compound C=1C=C(O)C=CC=1C(C)(C)C1=CC=C(O)C=C1 IISBACLAFKSPIT-UHFFFAOYSA-N 0.000 description 1
- 238000009835 boiling Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000004850 liquid epoxy resins (LERs) Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001000 micrograph Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
- H05K3/4676—Single layer compositions
Landscapes
- Laminated Bodies (AREA)
- Casting Or Compression Moulding Of Plastics Or The Like (AREA)
- Moulding By Coating Moulds (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
本発明は改良された多層印刷配線板の製造方法
に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to an improved method of manufacturing multilayer printed wiring boards.
従来、多層印刷配線板(以下多層板という)の
製造方法としては、銅張積層板をエツチング加工
した内層回路板とプリプレグを重ね合せ、積層プ
レスによつて加熱加圧し一体化形成し、その後両
面印刷板と同様に穴をあけ、パネルメツキを行
い、次いで外層回路を形成し多層板を得るという
製造方法が一般的である。 Conventionally, the manufacturing method for multilayer printed wiring boards (hereinafter referred to as multilayer boards) involves stacking an etched inner layer circuit board of a copper-clad laminate and a prepreg, heating and pressing them using a lamination press to form an integrated structure, and then pressing both sides together. A common manufacturing method is to drill holes in the same way as printing plates, plate the panels, and then form outer layer circuits to obtain a multilayer board.
近年、コンピユーター等の情報処理機器は多量
の情報を高速で処理するのに、大規模集積回路素
子(LSI)とが超大規模集積回路素子(VLSI)
を多層板に高密度実装することが要求されるよう
になつてきた。 In recent years, information processing devices such as computers process large amounts of information at high speed, and large-scale integrated circuit devices (LSI) have been replaced by very large-scale integrated circuit devices (VLSI).
There is a growing demand for high-density mounting of devices on multilayer boards.
これらの回路素子間の信号を高速伝達するには
多層板が一定の電子特性を備えなければならな
い。 In order to transmit signals between these circuit elements at high speed, the multilayer board must have certain electronic properties.
重要な電気特性として、特性インピーダンス
(ZO)があり、この特性を一定に保つには、多層
板の信号層と電源・アース層間の絶縁層の厚みを
一定にする必要がある。 An important electrical property is the characteristic impedance (ZO), and in order to keep this property constant, it is necessary to keep the thickness of the insulating layer between the signal layer and the power/ground layer of the multilayer board constant.
この問題に対処する方法として、従来はプリプ
レグの樹脂含有量の調整、プリプレグの樹脂のフ
ロー調整等の手法が用いられている。 Conventionally, methods such as adjusting the resin content of the prepreg and adjusting the flow of the resin in the prepreg have been used to deal with this problem.
しかしながら本質的に内層回路の回路密度は
夫々異なることおよび回路埋め込み性を完全にす
るためプリプレグには適度のフローが要求される
ことから、上記の従来手法には自ずから限界があ
る。 However, since the circuit densities of the inner layer circuits essentially differ from each other and the prepreg is required to have a moderate flow in order to completely embed the circuit, the above-mentioned conventional method has its own limitations.
更に電力供給損失を小さくするため、回路銅箔
は厚いものが要求される傾向にあり、従来の手法
では全く対応できないところ迄来ていることも事
実である。 Furthermore, in order to reduce power supply loss, there is a tendency for thicker circuit copper foils to be required, and it is also true that conventional methods have reached a point where this cannot be achieved at all.
本発明の目的はかかる従来の問題点を解決する
多層板の製造方法を提供することにある。 An object of the present invention is to provide a method for manufacturing a multilayer board that solves the problems of the prior art.
即ち多層板を製造するに当り、内層を構成する
回路板の表面の回路部と基板面の銅箔厚みに基ず
く段差を熱硬化性樹脂を主成分とする組成物にて
埋め込み、表面平滑処理を行つた後、該組成物を
加熱硬化せしめてBステージ状態と成し、然る後
絶縁層と成すべきプリプレグを処理面上に積層
し、加熱加圧成形を行うことにより内層回路間の
絶縁層の厚みが均一な多層印刷配線板を得る方法
に関するものである。 That is, when manufacturing a multilayer board, the circuit part on the surface of the circuit board constituting the inner layer and the level difference based on the thickness of the copper foil on the board surface are filled with a composition whose main component is a thermosetting resin, and the surface is smoothed. After that, the composition is heated and cured to form a B-stage state, and then a prepreg to be formed as an insulating layer is laminated on the treated surface, and heat and pressure molding is performed to create insulation between inner layer circuits. The present invention relates to a method for obtaining a multilayer printed wiring board with uniform layer thickness.
以下本発明の詳細について述べる。 The details of the present invention will be described below.
本発明に用いられる回路板は、ガラス−エポキ
シ樹脂回路板、ガラス−ポリアミノビスマレイミ
ド樹脂回路板が主なものであるが、他の回路板で
あつても適用可能である。 The circuit boards used in the present invention are mainly glass-epoxy resin circuit boards and glass-polyaminobismaleimide resin circuit boards, but other circuit boards are also applicable.
しかしながら本発明の適用対象は高度の性能を
要求される多層板であり、ガラス−ポリアミノビ
スマレイミド樹脂回路板が主たる対象になる。 However, the present invention is applied to multilayer boards that require high performance, and glass-polyamino bismaleimide resin circuit boards are the main targets.
また本発明に用いられる熱硬化性樹脂組成物は
その形態についてはワニス状、ペースト状いずれ
であつても良いが、埋め込み後の厚み減少を少な
くするという意味で溶媒は極力少いことが好まし
く、埋め込み樹脂組成物のBステージ化の調整の
ためには除去し易い溶媒が好ましい。 Further, the thermosetting resin composition used in the present invention may be in the form of either varnish or paste, but it is preferable to use as little solvent as possible in order to reduce the decrease in thickness after embedding. In order to control the B-staging of the embedding resin composition, a solvent that is easy to remove is preferred.
耐スメアー性、層間接着力、ドリル加工性、耐
熱性等の多層板として要求される性能を確保する
上ではプリプレグを構成する樹脂組成物が好まし
い。 The resin composition constituting the prepreg is preferred in order to ensure the performance required for a multilayer board, such as smear resistance, interlayer adhesion, drill workability, and heat resistance.
イミド系基板、イミド系プリプレグを用いる多
層板においては、液状エポキシ樹脂またはポリア
ミノビスマレイミド樹脂に対しては貧溶媒であ
り、且つエポキシ系樹脂に良溶媒である溶媒にポ
リアミノビスマレイミド樹脂を均一分散せしめた
樹脂ペーストが特に上述の如き制約を克服する意
味で特に好ましい。 In multilayer boards using imide-based substrates and imide-based prepregs, polyamino bismaleimide resin is uniformly dispersed in a solvent that is a poor solvent for liquid epoxy resin or polyamino bismaleimide resin and a good solvent for epoxy resin. A resin paste is particularly preferred in that it overcomes the above-mentioned limitations.
これらワニスまたはペーストは内層回路板上に
施されるが、この方法としてはロールコーター、
ドクターナイフコーター、スクリーン印刷アプリ
ケーター、ホイラー等による方法があるが、塗布
厚みの調整が容易なスクリーン印刷が好ましい結
果を与える。 These varnishes or pastes are applied onto the inner layer circuit board using a roll coater,
There are methods using a doctor knife coater, screen printing applicator, wheeler, etc., but screen printing, which allows easy adjustment of the coating thickness, gives preferable results.
勿論この場合回路全面へのいわゆるベタ印刷で
ある。 Of course, in this case, so-called solid printing is performed on the entire surface of the circuit.
次いでこれら樹脂組成物により回路間に埋め込
まれた回路板は、該樹脂組成物がBステージ状態
になる迄加熱される。 Next, the circuit board embedded between the circuits with these resin compositions is heated until the resin compositions are in a B-stage state.
Bステージ化後、裏面回路も同様な方法で処理
し両面の回路が樹脂により平滑化された回路板を
得る
なおこの場合の樹脂厚みは回路上が零であつて
回路間が回路間と同一迄埋め込まれたものが理想
的であるが、従来の段差が減少すれば厚塗りであ
つても薄塗りであつても絶縁層厚み精度への寄与
はそれなりにある。 After the B-stage, the circuits on the back side are treated in the same way to obtain a circuit board in which the circuits on both sides are smoothed with resin.In this case, the resin thickness is zero on the circuit and the thickness between the circuits is the same as that between the circuits. Ideally, it would be buried, but if the conventional level difference is reduced, whether it is thickly coated or thinly coated, it will make a certain contribution to the accuracy of the insulating layer thickness.
かくして得られる複数枚の回路板を用い、その
層間にプリプレグを挿入して多層板を積層成形に
より得る点は従来と全く同様である。 It is exactly the same as the conventional method in that a plurality of circuit boards thus obtained are used, a prepreg is inserted between the layers, and a multilayer board is obtained by lamination molding.
以下実施例を示す。 Examples are shown below.
実施例 1
ビスフエノール型エポキシ樹脂(シエル社製エ
ピコート#828)30重量部にポリアミノビスマレ
イミド樹脂粉末70重量部を分散せしめ粉体の均一
分散を図るために3本インクロールを3回通過せ
しめ、ペースト状組成物を得た。Example 1 70 parts by weight of polyamino bismaleimide resin powder was dispersed in 30 parts by weight of bisphenol type epoxy resin (Epicoat #828 manufactured by Ciel Co., Ltd.) and passed through three ink rolls three times to ensure uniform dispersion of the powder. A paste composition was obtained.
次に回路の形成された35μ銅箔ガラスポリイミ
ド両面回路板の片面にアプリケータを用いて40μ
になる様にコートを施した。 Next, use an applicator to apply 40μ to one side of the 35μ copper foil glass polyimide double-sided circuit board with the circuit formed.
I applied a coat to make it look like this.
次いで130℃で0.5時間硬化せしめた後裏面回路
も同様な方法で処理し150℃、0.5時間乾燥機で硬
化せしめた。 After curing at 130°C for 0.5 hours, the back circuit was treated in the same manner and cured in a dryer at 150°C for 0.5 hours.
得られた回路板は、その表面を粗さ計で測定し
たところ±2.5μの粗度であつた。 The surface of the obtained circuit board was measured with a roughness meter and had a roughness of ±2.5μ.
なお比較として未処理回路についても同一な測
定を実施したところ基板面と回路面上では30μの
段差が認められた。 For comparison, when the same measurement was performed on an untreated circuit, a 30μ difference in level was observed between the board surface and the circuit surface.
従つて片面で30μの段差が5μの段差に減少した
ことになる。 Therefore, the step difference on one side was reduced from 30μ to 5μ.
次いで該処理回路板を2枚と35μの外層銅箔2
枚の各層間に積層後厚み100μになるようなポリ
アミノビスマレイミドエポキシ樹脂−ガラス布プ
リプレグ2枚づつを積層し、170℃、2時間、40
Kg/cm2の圧力で積層成形を行つた。 Next, two of the treated circuit boards and 35μ outer layer copper foil 2
Two sheets of polyamino bismaleimide epoxy resin-glass fabric prepreg with a thickness of 100 μm after lamination were laminated between each layer, and heated at 170℃ for 2 hours for 40 minutes.
Lamination molding was carried out at a pressure of Kg/cm 2 .
得られた多層板につき、これを切断し、3層〜
4層間の回路厚みを10ケ所にわたり顕微鏡写真に
より測定した。 The obtained multilayer board is cut into 3 to 3 layers.
The circuit thickness between the four layers was measured at 10 locations using micrographs.
その結果回路間絶縁層厚みは210±10μであり、
厚みバラツキは±5%以内に抑え込むことができ
た。 As a result, the thickness of the insulating layer between the circuits was 210±10μ,
The thickness variation could be suppressed to within ±5%.
更に耐スメアー性、層間接着力、穴あけ性、煮
沸後ハンダ耐熱性について定められた試験法によ
り測定を行つたところ、従来品に比較し何等孫色
のない多層板であつた。 Furthermore, when the smear resistance, interlayer adhesion strength, perforation property, and post-boiling solder heat resistance were measured using established test methods, the multilayer board was found to have no inferiority compared to conventional products.
比較例 1
実施例1で用いた同一の内層回路板を用い、回
路面を処理することなしに実施例1と全く同様な
方法で多層板を作製し、回路間厚みを測定した。Comparative Example 1 Using the same inner layer circuit board used in Example 1, a multilayer board was produced in exactly the same manner as in Example 1 without processing the circuit surface, and the inter-circuit thickness was measured.
その結果回路間厚みは193±35μであり、厚み
バラツキは20%であつた。 As a result, the thickness between the circuits was 193±35μ, and the thickness variation was 20%.
以下本発明の方法により得られた作用効果は以
下の如くである。 The effects obtained by the method of the present invention are as follows.
1 樹脂組成物による埋め込み法であるため、回
路間を完全に埋め込むことができた。1 Since the embedding method uses a resin composition, it was possible to completely embed the circuits.
2 回路板が板内で異なるものであつても平滑化
が図れる。2. Smoothness can be achieved even if the circuit boards are different within the board.
3 予め平滑化処理が施されているため、従来の
如くプリプレグ中の樹脂による埋め込みを考慮
する必要がなく、プリプレグの役割が層間接着
のみとなり、樹脂含有量の少ないフローの少な
いプリプレグを用いることができる。3. Because the smoothing process has been applied in advance, there is no need to consider embedding with resin in the prepreg as in the past, and the role of the prepreg is only interlayer adhesion, making it possible to use prepreg with a low resin content and low flow. can.
従つて極めて厚み精度の調整が簡単になる。 Therefore, adjustment of thickness accuracy becomes extremely easy.
4 回路厚みによる影響を受けず銅箔厚みを増大
できる。4. Copper foil thickness can be increased without being affected by circuit thickness.
5 回路基板、プリプレグと同一組成の樹脂組成
物を適用すれば従来と同一性能の多層板が得ら
れる。5. If a resin composition having the same composition as that of the circuit board and prepreg is applied, a multilayer board with the same performance as the conventional one can be obtained.
Claims (1)
路板表面の回路と基板面の段差間に、ポリアミノ
ビスマレイミド樹脂とエポキシ樹脂を主成分とす
る組成物を埋め込み表面平滑処理を施した後、加
熱硬化せしめて該組成物をBステージ状態とな
し、しかる後絶縁層と成すべきプリプレグを処理
面上に積層しこれを熱圧着することを特徴とする
多層印刷配線板の製造方法。1. In a method for manufacturing a multilayer printed wiring board, a composition containing a polyamino bismaleimide resin and an epoxy resin as main components is embedded between the circuit on the surface of the inner layer circuit board and the step between the substrate surface, and after surface smoothing treatment, heat curing is performed. A method for manufacturing a multilayer printed wiring board, which comprises at least bringing the composition into a B-stage state, and then laminating a prepreg to be formed into an insulating layer on the treated surface and thermocompression bonding.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59273466A JPS61154096A (en) | 1984-12-26 | 1984-12-26 | Manufacture of multilayer printed wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59273466A JPS61154096A (en) | 1984-12-26 | 1984-12-26 | Manufacture of multilayer printed wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61154096A JPS61154096A (en) | 1986-07-12 |
JPH0365910B2 true JPH0365910B2 (en) | 1991-10-15 |
Family
ID=17528313
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59273466A Granted JPS61154096A (en) | 1984-12-26 | 1984-12-26 | Manufacture of multilayer printed wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61154096A (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62147798A (en) * | 1985-12-23 | 1987-07-01 | 東芝ケミカル株式会社 | Multilayer printed circuit board |
JPS6324695A (en) * | 1986-07-17 | 1988-02-02 | 東芝ケミカル株式会社 | Manufacture of multilayer interconnection board |
JPS6484698A (en) * | 1987-09-26 | 1989-03-29 | Matsushita Electric Works Ltd | Manufacture of multilayer circuit board |
JPH01143294A (en) * | 1987-11-27 | 1989-06-05 | Hitachi Chem Co Ltd | Manufacture of multilayer printed wiring board |
JP2646711B2 (en) * | 1988-11-01 | 1997-08-27 | 日本電気株式会社 | Method for manufacturing multilayer printed wiring board |
JP2682093B2 (en) * | 1988-12-27 | 1997-11-26 | 日本電気株式会社 | Method for manufacturing multilayer printed wiring board |
JPH0458591A (en) * | 1990-06-28 | 1992-02-25 | Shin Kobe Electric Mach Co Ltd | Manufacture of multi-layer printed wiring board |
JPH07123185B2 (en) * | 1992-09-25 | 1995-12-25 | 松下電工株式会社 | Circuit board |
KR100209259B1 (en) * | 1996-04-25 | 1999-07-15 | 이해규 | Ic card and method for manufacture of the same |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53132772A (en) * | 1977-04-22 | 1978-11-18 | Tokyo Shibaura Electric Co | Multilayer printed circuit board |
JPS55120649A (en) * | 1979-03-12 | 1980-09-17 | Hitachi Chem Co Ltd | Resin composition used for prepreg for multiply lamination |
JPS56148895A (en) * | 1980-04-21 | 1981-11-18 | Fujitsu Ltd | Both-side printed circuit board and multilayer board |
JPS56159229A (en) * | 1980-05-14 | 1981-12-08 | Mitsubishi Gas Chem Co Inc | Production of multilayer board |
JPS57145397A (en) * | 1981-03-04 | 1982-09-08 | Hitachi Ltd | Method of producing multilayer printed circuit board |
JPS59121995A (en) * | 1982-12-28 | 1984-07-14 | 日本電気株式会社 | Method of producing multilayer printed circuit board |
JPS59149095A (en) * | 1983-02-15 | 1984-08-25 | 三菱瓦斯化学株式会社 | Method of producing multilayer board |
JPS6062194A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
-
1984
- 1984-12-26 JP JP59273466A patent/JPS61154096A/en active Granted
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53132772A (en) * | 1977-04-22 | 1978-11-18 | Tokyo Shibaura Electric Co | Multilayer printed circuit board |
JPS55120649A (en) * | 1979-03-12 | 1980-09-17 | Hitachi Chem Co Ltd | Resin composition used for prepreg for multiply lamination |
JPS56148895A (en) * | 1980-04-21 | 1981-11-18 | Fujitsu Ltd | Both-side printed circuit board and multilayer board |
JPS56159229A (en) * | 1980-05-14 | 1981-12-08 | Mitsubishi Gas Chem Co Inc | Production of multilayer board |
JPS57145397A (en) * | 1981-03-04 | 1982-09-08 | Hitachi Ltd | Method of producing multilayer printed circuit board |
JPS59121995A (en) * | 1982-12-28 | 1984-07-14 | 日本電気株式会社 | Method of producing multilayer printed circuit board |
JPS59149095A (en) * | 1983-02-15 | 1984-08-25 | 三菱瓦斯化学株式会社 | Method of producing multilayer board |
JPS6062194A (en) * | 1983-09-14 | 1985-04-10 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPS61154096A (en) | 1986-07-12 |
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