JP3100689B2 - Method of forming recess for mounting electronic components on printed wiring board - Google Patents

Method of forming recess for mounting electronic components on printed wiring board

Info

Publication number
JP3100689B2
JP3100689B2 JP03221888A JP22188891A JP3100689B2 JP 3100689 B2 JP3100689 B2 JP 3100689B2 JP 03221888 A JP03221888 A JP 03221888A JP 22188891 A JP22188891 A JP 22188891A JP 3100689 B2 JP3100689 B2 JP 3100689B2
Authority
JP
Japan
Prior art keywords
adhesive
wiring board
printed wiring
layer
concave portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP03221888A
Other languages
Japanese (ja)
Other versions
JPH0563339A (en
Inventor
嘉保 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP03221888A priority Critical patent/JP3100689B2/en
Publication of JPH0563339A publication Critical patent/JPH0563339A/en
Application granted granted Critical
Publication of JP3100689B2 publication Critical patent/JP3100689B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明はプリント配線板の電子部
品搭載用凹部の形成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a concave portion for mounting an electronic component on a printed wiring board.

【0002】[0002]

【従来の技術】従来、ICチップは一般にデュアルイン
ラインパッケージ等のパッケージに収容されてプリント
配線板に搭載されていた。パッケージのプリント配線板
上への搭載方法としてはパッケージに設けられた多数の
リード(ピン)をプリント配線板のスルーホールに挿
入、半田付けする方法、あるいはフラットパッケージの
ようにリードをプリント配線板のスルーホールに挿入せ
ずに導体パターンのパッド部に直接半田付けする方法等
がある。そして、機器の小型化を図るための薄型化や実
装密度の向上のため、プリント配線板に凹部を形成して
そのなかにICチップやICパッケージに内蔵されたI
Cの作動条件を設定するコンデンサ、抵抗等の外付用の
チップ部品を配置する方法も行われている。
2. Description of the Related Art Conventionally, an IC chip has generally been housed in a package such as a dual in-line package and mounted on a printed wiring board. A package can be mounted on a printed wiring board by inserting a large number of leads (pins) provided in the package into through holes in the printed wiring board and soldering, or by connecting the leads to the printed wiring board like a flat package. There is a method of directly soldering to the pad portion of the conductor pattern without inserting it into the through hole. Then, in order to reduce the thickness of the device and improve the packaging density, a concave portion is formed in the printed wiring board, and the IC chip or IC package containing the concave portion is formed therein.
A method of arranging external chip components such as a capacitor and a resistor for setting the operating condition of C has also been performed.

【0003】従来、ICチップ等の電子部品搭載用の凹
部は図4に示す手順で形成されていた。すなわち、基材
21の両面に銅箔22が積層された基板23にまずスル
ーホール用の穴24をあけ(図4(b))、次に所定の
箇所を座ぐって(抉って)凹部25を形成するとともに
ホーニング処理を行った後(図4(c))、少なくとも
無電解メッキを含むメッキ処理及びパターン形成を行う
(図4(d))。
Conventionally, recesses for mounting electronic components such as IC chips have been formed by the procedure shown in FIG. That is, a hole 24 for a through hole is first made in a substrate 23 in which a copper foil 22 is laminated on both sides of a base material 21 (FIG. 4B), and then a concave portion 25 is formed by sitting (gouging) at a predetermined position. After forming and honing (FIG. 4C), a plating process including at least electroless plating and pattern formation are performed (FIG. 4D).

【0004】[0004]

【発明が解決しようとする課題】ところが、従来の方法
では無電解メッキ処理が施される凹部25の表面はホー
ニング処理による凹凸のみが存在するため、凹部25に
形成されるメッキ層26と基材21との密着性が劣り、
凹部25に電子部品を搭載する際にメッキ層26が基材
21から剥離する場合があり、プリント配線板の信頼性
が低いという問題がある。凹部25の表面にアディティ
ブプリント配線板用の無電解メッキ用接着剤を塗布して
接着層を形成するとともに、その表面を粗化してメッキ
層26との密着性を高めることも考えられるが、凹部2
5が形成された後に凹部25の表面にのみ所定の厚さで
接着剤を塗布する作業は非常に困難であり、製造ライン
で実施すると作業能率を大幅に低下させることになる。
However, in the conventional method, only the unevenness due to the honing process is present on the surface of the concave portion 25 on which the electroless plating process is performed. Poor adhesion to 21
When the electronic component is mounted in the concave portion 25, the plating layer 26 may peel off from the base material 21, and there is a problem that the reliability of the printed wiring board is low. It is conceivable to apply an adhesive for electroless plating for an additive printed wiring board on the surface of the concave portion 25 to form an adhesive layer, and to roughen the surface to improve the adhesion to the plating layer 26. 2
It is very difficult to apply the adhesive with a predetermined thickness only to the surface of the concave portion 25 after the formation of the step 5, and if it is performed on a production line, the operation efficiency will be greatly reduced.

【0005】本発明は前記の問題点に鑑みてなされたも
のであって、その目的は電子部品が搭載される凹部内に
形成されるメッキ層との密着性が良好で電子部品を搭載
した状態におけるメッキ層の剥離を確実に防止でき、プ
リント配線板の信頼性を高めることができるプリント配
線板の電子部品搭載用凹部の形成方法を提供することに
ある。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to improve the adhesion to a plating layer formed in a concave portion in which an electronic component is mounted and to provide a state in which the electronic component is mounted. It is an object of the present invention to provide a method for forming a concave portion for mounting an electronic component on a printed wiring board, which can reliably prevent the plating layer from peeling off and improve the reliability of the printed wiring board.

【0006】[0006]

【課題を解決するための手段】前記の目的を達成するた
め本発明においては、基材表面の少なくとも凹部が形成
される部分に無電解メッキ用接着剤を塗布して接着層を
形成した後、凹部を形成すべき所定の箇所を除いた部分
に少なくともその表面部分に前記接着剤が塗布された絶
縁材層を形成し、次に前記接着層及び絶縁材層の表面を
粗化した後、無電解メッキを行うようにした。
In order to achieve the above object, in the present invention, an adhesive layer is formed by applying an electroless plating adhesive to at least a portion of a substrate surface where a concave portion is to be formed. An insulating material layer coated with the adhesive is formed on at least the surface portion except for a predetermined portion where a concave portion is to be formed, and then the surfaces of the adhesive layer and the insulating material layer are roughened. Electroplating was performed.

【0007】[0007]

【作用】基材表面の少なくとも凹部が形成される部分に
接着剤が塗布されて接着層が形成された後、凹部を形成
すべき所定の箇所を除いた部分に絶縁材層が形成され
る。絶縁材層は全体が接着剤で形成されるか、プリプレ
グを積層するとともにその表面部分に前記接着剤が塗布
されて形成される。次に前記接着層及び絶縁材層の表面
が粗化された後、無電解メッキが行われる。メッキ層は
基材表面に直接形成されるのではなく、アンカー効果の
大きな表面が粗化された接着層上に形成されるため密着
性が向上する。
After an adhesive is applied to at least a portion of the base material surface where a concave portion is to be formed to form an adhesive layer, an insulating material layer is formed in a portion other than a predetermined portion where a concave portion is to be formed. The insulating material layer is formed entirely of an adhesive or formed by laminating a prepreg and applying the adhesive to a surface portion thereof. Next, after the surfaces of the adhesive layer and the insulating material layer are roughened, electroless plating is performed. The plating layer is not formed directly on the surface of the base material, but is formed on the roughened adhesive layer with a surface having a large anchor effect, so that the adhesion is improved.

【0008】[0008]

【実施例】以下、本発明を具体化した一実施例を図1〜
図3に従って説明する。ビスフェノールA型エポキシ樹
脂(油化シェル製、商品名:E−1001)40重量部
と、フェノールノボラック型エポキシ樹脂(油化シェル
製、商品名:E−154)60重量部と、イミダゾール
型硬化剤(四国化成製、商品名:2PHZ)5重量部
と、エポキシ樹脂微粒子(東レ製、商品名:トレパール
EP−B、平均粒径0.5μm)10重量部と、エポキ
シ樹脂微粒子(東レ製、商品名:トレパールEP−B、
平均粒径5.5μm)25重量部と、ブチルセロソルブ
アセテート75重量部とを三本ローラーで攪拌、混合し
てアディティブプリント配線板用接着剤(以下、単に接
着剤と呼ぶ)を調整した。
DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will now be described with reference to FIGS.
This will be described with reference to FIG. 40 parts by weight of a bisphenol A type epoxy resin (manufactured by Yuka Shell, trade name: E-1001), 60 parts by weight of a phenol novolak type epoxy resin (manufactured by Yuka Shell, trade name: E-154), and an imidazole type curing agent 5 parts by weight (manufactured by Shikoku Chemicals, trade name: 2PHZ), 10 parts by weight of epoxy resin fine particles (manufactured by Toray, trade name: Trepearl EP-B, average particle size: 0.5 μm), and epoxy resin fine particles (manufactured by Toray, product: Name: Trepal EP-B,
25 parts by weight of an average particle size (5.5 μm) and 75 parts by weight of butyl cellosolve acetate were stirred and mixed with a three-roller to prepare an adhesive for an additive printed wiring board (hereinafter, simply referred to as an adhesive).

【0009】基材1の両面にロールコーターで前記接着
剤を30μmの厚さに塗布して第1の接着層2aを形成
した(図1)。次に前記第1の接着層2aが形成された
基材1の凹部3を形成すべき所定の箇所を除いた部分
に、スクリーン印刷により前記接着剤を塗布して絶縁材
層としての第2の接着層2bを形成した(図2
(a))。接着剤の塗布は2回に分けて行い、1回で1
00μmの厚さに塗布し、2回の塗布により200μm
の厚さとした。次に両接着層2a,2bを加熱乾燥硬化
した後、クロム酸水溶液(800g/l)に70℃で1
0分間浸漬して接着層2a,2bの表面を粗化した。次
いでスルーホール用の穴あけ加工を行った(図2
(b))後、所定箇所にメッキレジスト層4を形成し
(図3(a))、通常の条件で無電解銅メッキを行い、
メッキレジスト層4で覆われていない部分に銅メッキ層
5を形成した(図3(b))。
The adhesive was applied to both surfaces of the substrate 1 with a roll coater to a thickness of 30 μm to form a first adhesive layer 2a (FIG. 1). Then, the adhesive is applied by screen printing to a portion of the base material 1 on which the first adhesive layer 2a is formed except for a predetermined portion where the concave portion 3 is to be formed, and a second material as an insulating material layer is applied. An adhesive layer 2b was formed (FIG. 2
(A)). The application of the adhesive is divided into two steps, and one
Coated to a thickness of 00 μm, 200 μm by two coatings
And the thickness. Next, both adhesive layers 2a and 2b are heated and dried and cured, and then immersed in a chromic acid aqueous solution (800 g / l) at 70 ° C. for 1 hour.
The surfaces of the adhesive layers 2a and 2b were roughened by immersion for 0 minutes. Next, drilling for through holes was performed (FIG. 2).
(B)) After that, a plating resist layer 4 is formed at a predetermined position (FIG. 3A), and electroless copper plating is performed under normal conditions.
A copper plating layer 5 was formed on a portion not covered with the plating resist layer 4 (FIG. 3B).

【0010】凹部3の表面は全部が接着層2a,2bに
より形成されており、クロム酸水溶液による粗化処理に
よりアンカー効果の大きな状態となり、銅メッキ層5と
の密着性が良好な状態となる。凹部3に形成された銅メ
ッキ層5の密着強度は凹部3以外の箇所に形成された銅
メッキ層5の密着強度と同じで、ピール強度の値は1.
7kg/cmであった。そして、凹部3に電子部品を搭
載しても銅メッキ層5の剥離が生じることは無かった。
The entire surface of the concave portion 3 is formed by the adhesive layers 2a and 2b. The roughening treatment with the chromic acid aqueous solution provides a large anchor effect, and the adhesiveness with the copper plating layer 5 is good. . The adhesion strength of the copper plating layer 5 formed in the recess 3 is the same as the adhesion strength of the copper plating layer 5 formed in a portion other than the recess 3, and the peel strength is 1.
It was 7 kg / cm. Then, even when an electronic component was mounted in the recess 3, the copper plating layer 5 did not peel off.

【0011】なお、本発明は前記実施例に限定されるも
のではなく、例えば、絶縁材層を構成する第2の接着層
2bを液状の接着剤を塗布して形成する代わりに、前記
接着剤をドライフィルム化して所定の厚さのシートを形
成するとともに、凹部3となるべき部分を打ち抜いたも
のを第1の接着層2aの上にラミネートしてもよい。
又、絶縁材層全体を接着剤で構成する代わりに、ガラス
クロスにエポキシ樹脂を含浸させて所定の厚さに形成す
るとともに凹部3となる孔を打ち抜きで形成した半硬化
状態のプリプレグを第1の接着層2aの上に積層し、そ
の表面に前記接着剤を30μmの厚さに塗布して接着層
を形成した後、加熱乾燥硬化処理するようにしてもよ
い。又、接着剤として前記以外のアディティブプリント
配線板用接着剤を使用したり、第1の接着層2aを基材
1の全面に塗布する代わりに凹部3を形成する箇所にの
み塗布してもよい。
The present invention is not limited to the above embodiment. For example, instead of forming the second adhesive layer 2b constituting the insulating material layer by applying a liquid adhesive, the present invention is not limited thereto. May be formed into a dry film to form a sheet having a predetermined thickness, and a sheet obtained by punching out a portion to be the concave portion 3 may be laminated on the first adhesive layer 2a.
Also, instead of forming the entire insulating material layer with an adhesive, a semi-cured prepreg formed by impregnating a glass cloth with an epoxy resin to have a predetermined thickness and punching a hole serving as a concave portion 3 is a first prepreg. The adhesive may be laminated on the adhesive layer 2a, and the surface of the adhesive may be coated with the adhesive to a thickness of 30 μm to form an adhesive layer. Further, an adhesive for an additive printed wiring board other than the above may be used as the adhesive, or the first adhesive layer 2a may be applied only to the portion where the concave portion 3 is to be formed instead of applying to the entire surface of the substrate 1. .

【0012】[0012]

【発明の効果】以上詳述したように本発明によれば、凹
部の少なくとも底面が接着層で形成されて粗化された状
態で無電解メッキが施されるため、メッキ層との密着性
が良好となり、電子部品を搭載した際におけるメッキ層
の剥離が確実に防止され、プリント配線板の信頼性が向
上する。
As described above in detail, according to the present invention, at least the bottom surface of the concave portion is formed of an adhesive layer and roughened, and electroless plating is performed. As a result, the peeling of the plating layer when the electronic component is mounted is reliably prevented, and the reliability of the printed wiring board is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の基材及びその全面に第1の接着層が形
成された状態を示す概略断面図である。
FIG. 1 is a schematic cross-sectional view showing a substrate of the present invention and a state where a first adhesive layer is formed on the entire surface thereof.

【図2】(a)は第2の接着層が形成された状態を示す
概略断面図、(b)は接着層表面の粗化及び基材に穴あ
けされた状態を示す概略断面図である。
2A is a schematic sectional view showing a state in which a second adhesive layer is formed, and FIG. 2B is a schematic sectional view showing a state in which the surface of the adhesive layer is roughened and a hole is formed in a base material.

【図3】(a)はメッキレジスト層が形成された状態を
示す概略断面図、(b)は無電解メッキが施された状態
を示す概略断面図である。
3A is a schematic cross-sectional view showing a state where a plating resist layer is formed, and FIG. 3B is a schematic cross-sectional view showing a state where electroless plating is performed.

【図4】従来の凹部を形成する手順を示す概略断面図で
ある。
FIG. 4 is a schematic sectional view showing a procedure for forming a conventional concave portion.

【符号の説明】[Explanation of symbols]

1…基材、2a…第1の接着層、2b…絶縁材層として
の第2の接着層、3…凹部、4…メッキレジスト層、5
…銅メッキ層。
DESCRIPTION OF SYMBOLS 1 ... Base material, 2a ... First adhesive layer, 2b ... Second adhesive layer as insulating material layer, 3 ... Concave part, 4 ... Plating resist layer, 5
... copper plating layer.

フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 3/10 - 3/38 Continuation of the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 3/10-3/38

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 基材(1)表面の少なくとも凹部が形成
される部分に無電解メッキ用接着剤を塗布して接着層
(2a)を形成した後、凹部(3)を形成すべき所定の
箇所を除いた部分に少なくともその表面部分に前記接着
剤が塗布された絶縁材層(2b)を形成し、次に前記接
着層(2a)及び絶縁材層(2b)の表面を粗化した
後、無電解メッキを行うアディティブプリント配線板の
電子部品搭載用凹部の形成方法。
An adhesive for electroless plating is applied to at least a portion of a surface of a substrate (1) where a recess is to be formed to form an adhesive layer (2a), and then a predetermined portion to form a recess (3) is formed. An insulating material layer (2b) coated with the adhesive is formed on at least the surface of the portion except for the portion, and then the surfaces of the adhesive layer (2a) and the insulating material layer (2b) are roughened. Forming a concave portion for mounting an electronic component on an additive printed wiring board by electroless plating.
JP03221888A 1991-09-02 1991-09-02 Method of forming recess for mounting electronic components on printed wiring board Expired - Fee Related JP3100689B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP03221888A JP3100689B2 (en) 1991-09-02 1991-09-02 Method of forming recess for mounting electronic components on printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP03221888A JP3100689B2 (en) 1991-09-02 1991-09-02 Method of forming recess for mounting electronic components on printed wiring board

Publications (2)

Publication Number Publication Date
JPH0563339A JPH0563339A (en) 1993-03-12
JP3100689B2 true JP3100689B2 (en) 2000-10-16

Family

ID=16773751

Family Applications (1)

Application Number Title Priority Date Filing Date
JP03221888A Expired - Fee Related JP3100689B2 (en) 1991-09-02 1991-09-02 Method of forming recess for mounting electronic components on printed wiring board

Country Status (1)

Country Link
JP (1) JP3100689B2 (en)

Also Published As

Publication number Publication date
JPH0563339A (en) 1993-03-12

Similar Documents

Publication Publication Date Title
US5243142A (en) Printed wiring board and process for producing the same
JPH11340367A (en) Multilayer wiring board and its manufacture
JP2002271033A (en) Printed wiring board and manufacturing method therefor
JP4863546B2 (en) Capacitor-embedded printed wiring board and manufacturing method of capacitor-embedded printed wiring board
JP2002100870A (en) Printed wiring board and manufacturing method thereof
JP3728068B2 (en) Multilayer wiring board
JPH06260756A (en) Manufacture of printed wiring board
JPH1187865A (en) Printed circuit board and its manufacture
JPS61154096A (en) Manufacture of multilayer printed wiring board
JP3100689B2 (en) Method of forming recess for mounting electronic components on printed wiring board
JPH06314883A (en) Multilayer printed wiring board and manufacture thereof
JP2002118367A (en) Printed wiring board and manufacturing method thereof
JP4863561B2 (en) Method for manufacturing printed wiring board
JP3728059B2 (en) Multilayer wiring board
JPH05327228A (en) Multilayer printed board provided with buried electronic circuit component
JP2826206B2 (en) Printed wiring board
JPH11289163A (en) Manufacture of multilayer printed wiring board
JP3469214B2 (en) Build-up multilayer printed wiring board
JPH10200264A (en) Multilayer printed wiring board and manufacture thereof
JP2002271025A (en) Printed wiring board and manufacturing method therefor
JP3469146B2 (en) Build-up multilayer printed wiring board
JP2000022330A (en) Multilayer interconnection board and its manufacture
JP3065766B2 (en) Manufacturing method of multilayer printed wiring board
JP2004040138A (en) Build up multilayer printed circuit board
JPH05267840A (en) Forming method for adhesive layer of additive printed circuit board

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070818

Year of fee payment: 7

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080818

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080818

Year of fee payment: 8

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090818

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090818

Year of fee payment: 9

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100818

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100818

Year of fee payment: 10

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110818

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees