JPH0364902B2 - - Google Patents

Info

Publication number
JPH0364902B2
JPH0364902B2 JP5370585A JP5370585A JPH0364902B2 JP H0364902 B2 JPH0364902 B2 JP H0364902B2 JP 5370585 A JP5370585 A JP 5370585A JP 5370585 A JP5370585 A JP 5370585A JP H0364902 B2 JPH0364902 B2 JP H0364902B2
Authority
JP
Japan
Prior art keywords
address
buffer register
register
vector
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP5370585A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61211774A (ja
Inventor
Masaki Kitajima
Shoji Nakatani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5370585A priority Critical patent/JPS61211774A/ja
Publication of JPS61211774A publication Critical patent/JPS61211774A/ja
Publication of JPH0364902B2 publication Critical patent/JPH0364902B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)
JP5370585A 1985-03-18 1985-03-18 ベクトル処理装置 Granted JPS61211774A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5370585A JPS61211774A (ja) 1985-03-18 1985-03-18 ベクトル処理装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5370585A JPS61211774A (ja) 1985-03-18 1985-03-18 ベクトル処理装置

Publications (2)

Publication Number Publication Date
JPS61211774A JPS61211774A (ja) 1986-09-19
JPH0364902B2 true JPH0364902B2 (https=) 1991-10-08

Family

ID=12950243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5370585A Granted JPS61211774A (ja) 1985-03-18 1985-03-18 ベクトル処理装置

Country Status (1)

Country Link
JP (1) JPS61211774A (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3659252B2 (ja) 2003-03-28 2005-06-15 セイコーエプソン株式会社 ベクトルデータのアドレス参照方法およびベクトルプロセッサ

Also Published As

Publication number Publication date
JPS61211774A (ja) 1986-09-19

Similar Documents

Publication Publication Date Title
US6115761A (en) First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment
US4884192A (en) Information processor capable of data transfer among plural digital data processing units by using an active transmission line having locally controlled storage of data
JPS6244303B2 (https=)
JP3797570B2 (ja) セマフォ命令用のセマフォ・バッファを用いた装置と方法
US5237702A (en) System for prefetching vector data based on the status of the vector registers
US6615296B2 (en) Efficient implementation of first-in-first-out memories for multi-processor systems
JPH0340868B2 (https=)
EP0267974B1 (en) Control interface for transferring data between a data processing unit and input/output devices
JPH0364902B2 (https=)
IE61306B1 (en) Method and device to execute two instruction sequences in an order determined in advance
US4816992A (en) Method of operating a data processing system in response to an interrupt
US5161217A (en) Buffered address stack register with parallel input registers and overflow protection
JP3467188B2 (ja) 多重化バスの順序保証システム
JP2988048B2 (ja) 辞書情報常駐アクセス装置
JPS59123974A (ja) ベクトルデ−タ記憶制御方式
JPH0232648B2 (https=)
JP2716563B2 (ja) データ書込み制御方式
JPH1185605A (ja) 記憶制御装置
KR0171771B1 (ko) 컴퓨터 시스템에 있어서 어드레스 버스 잠금 제어장치
JPS6373458A (ja) 共有メモリアクセス装置
JPS635432A (ja) マイクロプロセツサ
JPS61100852A (ja) デ−タ転送方式
JPH01307870A (ja) ベクトル処理装置の制御方式
JPH0375906B2 (https=)
JPS6034147B2 (ja) デ−タ転送における多段先行制御方式