JPH0364000A - Software error mount evaluating method for dynamic ram - Google Patents
Software error mount evaluating method for dynamic ramInfo
- Publication number
- JPH0364000A JPH0364000A JP1200631A JP20063189A JPH0364000A JP H0364000 A JPH0364000 A JP H0364000A JP 1200631 A JP1200631 A JP 1200631A JP 20063189 A JP20063189 A JP 20063189A JP H0364000 A JPH0364000 A JP H0364000A
- Authority
- JP
- Japan
- Prior art keywords
- data
- software error
- ras
- dynamic ram
- cycle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title abstract description 3
- 238000011156 evaluation Methods 0.000 claims abstract description 13
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はダイナミックＲＡＭの高速領域でのソフトエ
ラー実装評価方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a soft error implementation evaluation method in a high-speed area of dynamic RAM.
〔従来の技術」
第２図は従来のダイナミックＲＡＭのソフトエラーテス
トシーケンス図、第３図はサイクルタイムに対するソフ
トエラー率の関係を示すグラフである。[Prior Art] FIG. 2 is a soft error test sequence diagram of a conventional dynamic RAM, and FIG. 3 is a graph showing the relationship between soft error rate and cycle time.
次に動作について説明する。Next, the operation will be explained.
セル全面にＤａｔａ ｌ Ｗｒｉｔｃ Ｌ／、そのＤａ
ｔａをＲｅａｄする。Ｒｅａｄ Ｌ／たＤａｔａはコン
パレータによって判定する。もしＤａｔａが正しいとき
はＲｅａｄ→Ｄａｔａ判定をｎサイクル繰り返す。次に
反転Ｄａｔａをセル全面にＷｒｉｔｅ Ｌ／、同様に繰
り返す。もしＤａｔａ判定したときにＤａｔａが正しく
ない時はエラービットカウント等を検出してソフトエラ
ーを見極める。Data written on the entire surface of the cell, its Da
Read ta. Read L/Data is determined by a comparator. If Data is correct, Read→Data determination is repeated n cycles. Next, invert Data is written L/ on the entire surface of the cell, and the same process is repeated. If the Data is not correct when the Data is determined, the error bit count, etc. is detected to identify a soft error.
〔発明が解決しようとする課題」
従来のダイナミックＲＡＭのソフトエラー実装評価方法
は以上のように実施されているので、ダイナミックＲＡ
Ｍの書込み・読み出し時にはアドレスのマルチプレック
スによりどうしてもサイクルタイムを短かくできないた
め高速動作でのソフトエラー評価ができないという問題
点があった。[Problem to be solved by the invention] Since the conventional dynamic RAM soft error implementation evaluation method is implemented as described above, the dynamic RAM
When writing and reading M, it is impossible to shorten the cycle time by multiplexing addresses, so there is a problem that soft error evaluation cannot be performed in high-speed operation.
この発明は上記のような問題点を解消するためになされ
たもので、Ｒｅａｄサイクルのかわりに■オンリーリフ
レッシュサイクルを用いることで高速領域でのソフトエ
ラー実装評価を実現することを目的とする。This invention has been made to solve the above-mentioned problems, and aims to realize soft error implementation evaluation in a high-speed area by using a (1) only refresh cycle instead of a read cycle.
この発明に係るダイナミックＲＡＭのソフトエラ−評価
方法は、■ 、 ＣＡＳ 、ロウアドレス、コラムアド
レスを制御する必要があるところのＲｅａｄサイクルを
行なうかわりに■ 、ロウアドレスだけ制御すればよい
■オンリーリフレッシュサイクルを用いることにしたも
のである。The dynamic RAM soft error evaluation method according to the present invention has the following features: ■ Instead of performing a Read cycle, which requires controlling the CAS, row address, and column address, ■ Only the row address needs to be controlled ■ Only refresh cycle This is what I decided to use.
〔作用Ｊ
この発明におけるテストシーケンスでは、入力制御の多
いＲｅａｄサイクルのかわりに入力制御の少ない■オン
リーリフレッシュサイクルを使って高速領域でのソフト
エラー実装評価を実現できる。[Function J] In the test sequence of the present invention, soft error implementation evaluation in a high-speed region can be realized by using the (1) only refresh cycle with less input control instead of the read cycle with more input control.
〔実施例ｊ
以下、この発明に係るダイナミックＲＡＭのソフトエラ
ー実装評価方法の一実施例を図について説明する。第１
図は、ソフトエラーテストシーケンス図である。[Embodiment j] Hereinafter, an embodiment of a soft error implementation evaluation method for a dynamic RAM according to the present invention will be described with reference to the drawings. 1st
The figure is a soft error test sequence diagram.
次ｌζこの発明でのダイナミックＲＡＭにおけるテスト
シーケンスについて説明する。Next, a test sequence in the dynamic RAM according to the present invention will be explained.
セル全頁にＤａｔａをＷｒｉｔｅ シ、そのＤａｔａを
■オンリーリフレッシュする。もしソフトエラーでデー
タ反転してもそれは反転データとして保持されるためＤ
ａｔａ判定したいときにＲｅａｄする。次に裏のデータ
ＤａｔａをＷｒｉｔｅシ同様のシーケンスを繰り返す。Write data to all pages of cells, and refresh the data only. Even if data is inverted due to a soft error, it will be retained as inverted data, so D
Read when you want to judge ata. Next, write the data on the other side and repeat the same sequence.
以上のように、この発明によればＲｅａｄサイクルを■
オンリーリフレッシュサイクルにしたので、入力制御信
号が少なくてすみ、高速領域のソフトエラー実装評価が
できる。As described above, according to the present invention, the Read cycle can be
Since it uses only refresh cycles, fewer input control signals are required, making it possible to evaluate soft error implementation in high-speed areas.
＠１図はこの発明の一実施例によるダイナミックＲＡＭ
のソフトエラー実装評価方法のテストシーケンス図、第
２図は従来のダイナミックＲＡＭのソフトエラー実装方
法のテストシーケンス図、第３図はサイクルタイムに対
するソフトエラー率の関係を示すグラフである。@1 Figure shows a dynamic RAM according to an embodiment of this invention.
FIG. 2 is a test sequence diagram of a conventional dynamic RAM soft error implementation evaluation method, and FIG. 3 is a graph showing the relationship between soft error rate and cycle time.
Claims (1)
イクルの回数を減らし、その分■オンリーリフレッシュ
サイクルを増やすことで高速でのソフトエラー評価を可
能にすることを特徴とするダイナミツクＲＡＭのソフト
エラー実装評価方法。A soft error implementation evaluation method for a dynamic RAM characterized by reducing the number of read cycles as a test sequence for soft error evaluation and increasing the number of only refresh cycles accordingly, thereby enabling high-speed soft error evaluation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200631A JPH0364000A (en) | 1989-08-02 | 1989-08-02 | Software error mount evaluating method for dynamic ram |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1200631A JPH0364000A (en) | 1989-08-02 | 1989-08-02 | Software error mount evaluating method for dynamic ram |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0364000A true JPH0364000A (en) | 1991-03-19 |
Family
ID=16427594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1200631A Pending JPH0364000A (en) | 1989-08-02 | 1989-08-02 | Software error mount evaluating method for dynamic ram |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0364000A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06251598A (en) * | 1993-03-01 | 1994-09-09 | American Teleph & Telegr Co <Att> | Method and equipment for testing memory fault |
-
1989
- 1989-08-02 JP JP1200631A patent/JPH0364000A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06251598A (en) * | 1993-03-01 | 1994-09-09 | American Teleph & Telegr Co <Att> | Method and equipment for testing memory fault |
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