JPH0363748A - Bus control system - Google Patents

Abstract

PURPOSE:To enable processing to a response signal showing the execution of DMA operation regardless of the property of an MPU by once stopping an access to a DMA controller when the signal showing the execution of the DMA operation is received and controlling the interface of a common bus so as to restart the access afterwards. CONSTITUTION:Means 12 and 13 are provided to desave a bus interface control circuit 13 of an MPU part 10 when the signal showing the execution of the DMA operation is received and to enable the bus interface control circuit 13 gain afterwards. Thus, since it is not necessary to interrupt the operation of the MPU part 10, the MPU part 10 can be also used even without function to interrupt the cycle of the MPU part 10 by an external input signal and to execute the interrupted cycle again afterwards. Further, even when a DMA controller is under the DMA operation in the access that the MPU part 10 reads the vector of the DMA controller, it is enough to output the signal showing the DMA controller under the DMA operation and a circuit for outputting the special vector is not required.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a bus control system in a microcomputer device.

(Prior Art) Conventionally, this type of device has been disclosed in Japanese Patent Laid-Open No. 170857/1985, and will be described below with reference to the drawings.

FIG. 5 is a block diagram showing an example of the configuration of a conventional microcomputer device. Conventional microcomputer devices are equipped with a circuit that eliminates the bus idle time of the DMA controller during data transfer cycles between storage devices, thereby shortening the time during which the DMA controller exclusively uses the bus. . According to this conventional microcomputer device, the bus control section 20
Therefore, 1) since the MA controller 2 does not stop the MPUP4O10 to perform a data transfer cycle, it is possible to operate independently of the operation of the MPUP4O10MA controller 2. For example, MPU
If a dedicated bus (not shown) is connected to the P4O10 storage device, the DMA controller 2 can connect to the common bus 100.
Even when using MPUP4O10, the storage device can be accessed via the MPUP4O10 bus. Therefore, during the bus idle time of the DMA controller 2, the MP
If the right to use the UP4O10 bus is granted, M
DM in which PL1 section 10 is in bus idle cycle
A case may occur in which the A controller 2 is accessed.

Therefore, in this conventional device, for the MPU section IO,
Emit a signal 140 indicating that the DMA controller 2 is in operation,
It is decided to respond to 10 MPUs. As a result, for example, 10 parts of MPo may be added to MC6 manufactured by Motorola, USA.
In the case of using a BTR 8020', it is possible to interrupt the cycle of 10 MPo units by connecting signal 140 to the B'ETR input of the MC68020.
20° starts running the bus error handling software and executes the RTE command at the end of the process, ErETR
The cycle interrupted by the input (here, access to the DMA controller 2) is re-executed. In this way, the MPU io
The unit repeatedly accesses the DMA controller 2.

In addition, in response to an interrupt request from the DMA controller 2, if the DMA controller 2 is in operation when the MPo 10 performs a vector read access of the DMA controller 2, the signal 140 is not enabled, but instead The DMA controller 2 places an interrupt vector indicating that DMA operation is in progress on the data on the bus, and the MPLI 10
By providing a circuit responsive to the 10-part cycle, termination of the MPo 10-part cycle is possible. In this case, without clearing the interrupt request from DMA controller 2, the RTE
When the instruction is executed, the "MC68020" re-executes the access to read the vector.

(Problems to be Solved by the Invention) However, the above conventional device has the following problems.

(1) M does not have the function of being able to interrupt a cycle by an external input signal and then re-executing the interrupted cycle.
The PU section (for example, "180386" manufactured by Intel Corporation) cannot process this signal even if a response signal indicating that DMA operation is in progress is returned, so it cannot be used in the above-mentioned device. As a result, it is impossible to eliminate the bus idle time of the DMA controller 2 and shorten the bus exclusive time.

(2) Since the input device is generally controlled by an interrupt method, a circuit that issues an interrupt vector indicating that the DMA controller is in DMA operation is an essential component. This circuit requires one circuit (one driver IC, several gates) for each DMA controller, and when a large number of DMA controllers are provided, the amount of circuitry of the DMA controller increases.

(3) Software assistance is required to restart an interrupted cycle. However, this process is a wasteful process from the software perspective since it involves recovering hardware conflicts using software. Also,
The interruption of a cycle due to the B'ETR input is generally used as a means of notifying the occurrence of a failure such as a memory error, and the BTR''R input due to the generation of signal 140 is not due to the occurrence of a failure, so it is used as a means of notifying the occurrence of a failure such as a memory error. Software processing algorithms become complex.

The present invention is intended to solve these problems.
Regardless of the characteristics of U, it is possible to process a response signal indicating that DMA operation is in progress, and the DMA controller
It is an object of the present invention to provide a bus control method that does not require a circuit that issues an interrupt vector indicating that an MA is in operation, and does not require recovery processing by software.

(Means for Solving the Problems) In order to solve the above problems, the present invention is configured by connecting at least a microprocessor, a DMA controller, an input/output control device, and a storage device to a common bus, and A microcomputer device having a DMAC bus right control unit that monitors the state of the right to use the bus of a common bus and a bus right control unit that determines the right to use the bus, the microcomputer device having a DMAC bus right control unit that monitors the state of the right to use the bus of a common bus, the microcomputer device having a DMAC bus right control unit that monitors the status of the right to use the bus of a common bus, and in which a microprocessor or a DMA controller that is executing a DMA cycle is accessed. In a bus control system that responds to the microprocessor with a signal indicating that the DMA is in operation when
When a signal indicating that the microprocessor is in operation is received, the DMA is sent out onto the common bus while the microprocessor continues to operate.
After terminating access to the controller, the DMA
The present invention is characterized by providing means for controlling the common bus interface of the microprocessor so as to resume access to the controller.

(Operation) According to the present invention having such a configuration, when a signal indicating that DMA operation is in progress is received, access to the DMA controller sent out on the common bus is once terminated while the microprocessor continues to operate. let After that, DMA
Controlling the microprocessor's common bus interface to resume access to the controller. Therefore, regardless of the characteristics of the MPU, it is possible to process a response signal indicating that DMA operation is in progress, and there is no need for a circuit that generates an interrupt indicating that the DMA controller is in DMA operation, and recovery can be performed by software. A bus control method that does not require processing can be provided.

(Example) Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. An MPUII that controls the entire MPUP4O10 system of this embodiment shown in the figure, an address gouda 12 that decodes addresses from this MPUII, and a common bus 100.
A bus interface control circuit 13 that controls the interface to the MPU II, an address buffer 14 that temporarily stores the address of the MPUII, and a buffer 1 that temporarily stores the data.
and a bus control circuit consisting of 5.

Next, the procedure for accessing the DMA controller 2 by MPUP4O10PUII will be explained.

(1) First, the MPU 11 outputs an address for selecting the DMA controller 2. As a result, the decoder 12 outputs the decoded address signal 202 to the bus interface control circuit 13. At the same time, a signal 201 indicating address validity is also sent from the MPUII to the bus interface control circuit 13.

(2) The bus interface control circuit 13 outputs a bus use request signal 110 requesting the right to use the bus to the bus right control section 20.

(3) In response to this bus use request signal 110, the bus right control section 20 outputs a confirmation signal 120 to the bus interface control circuit 13 indicating that no other device occupies the common bus 100.

(4) In response to this confirmation signal 120, the bus interface control circuit 13 confirms that the signal 130 is in an invalid state and makes the signal 130 valid. At the same time, a signal 203 is generated to output address buffer 14 and data buffer 1.
5 is set to enable state. As a result, MPU1.1
The address and data (during a write cycle) are sent to the common bus 100.

Thereafter, the bus interface control circuit 13 waits for a response signal 140 or 141 to be issued from the DMA controller 2. Here, signal 140 is a signal indicating that DMA operation is in progress, and signal 141 is a normal response signal (D
! Since IIA is not in operation, this indicates that the DMA controller 2 has normally accepted the access from MPU II). When receiving signal 141, bus interface control circuit 13 disables signals 130 and 203.

As a result, the address/data information of the MPU 11 disappears from the common bus 100. At the same time, a signal 204 indicating a normal response is output to the MPU II. Upon receiving this, the MPU II terminates access to the DMA controller 2.

On the other hand, when receiving signal 140, bus interface control circuit 13 invalidates signals 130 and 203 in the same manner as described above. However, since the response is not normal, the signal 104
does not occur. Therefore, the MPU II is also performing access to the DMA controller 2. Therefore, since the signals 201 and 202 are still valid, the bus interface control circuit 13 again performs the above (1) to (5).
) to resend the address data to the common bus 100. The above steps are repeated until signal 141 is received.

This eliminates the need for signal 140 to interrupt the MPU II cycle. Also, recovery processing by software is not required. Furthermore, DMA controller 2
Even if the DMA controller 2 is in operation when MPtll reads the vector of the DMA controller 2 in response to an interrupt request from the DMA controller 2, the DMA controller 2 only needs to send out the signal 140. because,
This is because MPU10 repeats access to read the vector many times until it receives the signal 141. Therefore, there is no need to provide a circuit within the DMA controller 2 for issuing an interrupt vector indicating that the DMA controller 2 is performing a DMA operation.

Next, FIG. 2 shows the configuration of the bus interface control circuit 13 shown in FIG. 1. In the same figure, 51.65 is an AND gate, and 54.55.56.57.58.60 is a NAND gate.
Gate, 61.62 is NOR gate, 52.53.58
．． 66.67, 68 are D-type flip-flops, 63.6
4 is a JK type rough flip-flop. The signal 202 is
L' lebel, signals 120, 140, 141
, 201 are at "H" level.

Further, the output Q of the D-type flip-flop 58 and the output Q of the JK-type flip-flops 63 and 64 are at the "HII level," and the output Q of the D-type flip-flop 68 is at the L11 level.

First, the operation of this circuit in steps (1) to (5) above will be explained.

When the MPU II starts accessing the DMA controller 2, the signal 201 goes to "L" level and the signal 202 goes to "Hl" level.
J level. This turns on the AND gate 51, the outputs Q of the D-type flip-flops 52 and 53 go to the "H゛°° level, and the signal 110 goes to L11. After that,
The bus control unit 20 sets the signal 120 to "L" level.

Then, when the signal 130 reaches the "H11 level", the NA
The NυAND gate 65 is turned on, the output Q of the D-type flip-flop 58 becomes "'H°" level, and the signal 203
, 130 are at the "L'" level. From then on, this state continues until the signal 140 or 141 reaches the "L°° level."

Next, the operation of this circuit when the signal 140 or the signal 141 becomes "L" level will be explained.

FIG. 3 is an operation time chart when the signal 141 becomes "L'" level. When the signal 141 goes low, the J input of the JK type rough flip-flop 63 goes high, causing the signal 204 to go to the ``LIT'' level. At the same time, AND gate 65.51 turns off and D
The output Q of the type flip-flop 52 is at the 11 L IT level. As a result, signals 130, 203 are HII
level. On the other hand, the signal 2 which has become “L I+ level”
When the MPU II receives 04, the DMA controller 2
In order to terminate the access, the signal 201 goes to the "H" level and the signal 202 goes to the "L°°" level. This allows J
The input to the K-type rough flip-flop 63 becomes H°" level, and the signal 204 becomes H" level. Note that the address for selecting the DMA controller 2 that was output to the common bus disappears when the signal 203 reaches the "HII" level, so the signal 141 goes "H" after the signal 203 reaches the "HII" level. level.

FIG. 4 is an operation time chart when the signal 140 is at the "L" level. When the signal 140 goes to the L11 level, the J input of the JK type rough flip-flop 64 goes to the "H" level. As a result, the output Q of the JK-type rough flip-flop 64 goes to the "L" level, turns off the AND gate 65.51, and the D-type flip-flop 52
The output Q of becomes "L" level.

Therefore, the signals 130 and 203 become "H° level."

After that, the J input of the JK type rough flip-flop 64 is changed to “°
The signal converted to H” level is sent to the D-type clip flop 66.
, 67, and 68, the input to the JK type rough flip-flop 64 is set to "H level. At this time, the signal 20
3 is at the °H level, so the J input of the JK type rough flip-flop 64 is at the L11 level.

Therefore, the output Q of the JK type rough flip-flop 64 is "'
On the other hand, unlike the case where the signal 141 becomes the "L" level, the signal 204 remains at the "H" level. Therefore, the MPU II continues to access the DMA controller 2. Therefore, signal 20
1 is at the "L 1% level" and the signal 202 is at the "H" level, so when the output Q of the JK type rough flip-flop 64 reaches the "H" level, the above steps (1) to (
Repeat the operation in 5). This operation is repeated while the signal 140 goes low as a response signal.

(Effects of the Invention) As described above, according to the present invention, means is provided for disabling the bus interface control circuit of the MPU section when a signal indicating that DMA operation is in progress is received, and then enabling the bus interface control circuit again. Therefore, MP
Since there is no need to interrupt the operation of the L1 section, it is possible to use an MPU section that does not have a function of interrupting the cycle of the MPU section using an external input signal and then re-executing the interrupted cycle. Also, in the access where the MPU unit sells 2 vectors of the DMA controller, the DMA controller
Even if A is in operation, the DMA controller
It is only necessary to issue a signal indicating that A is in operation, and no special circuit for outputting a vector is required.

Furthermore, even if a signal indicating that a DMA operation is in progress is sent, no recovery processing by software is required.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a logic circuit diagram showing the configuration of a bus interface control circuit in this embodiment, and FIGS. 3 and 4 show the operation of this embodiment. Flowchart, FIG. 5 is a block diagram showing an example of the configuration of a conventional microcomputer device. 10・11◆ 12・13・14・15・00 MPU section, fraudulent PU 1 Address decoder, bus interface control circuit, address buffer, data buffer, ・Common bus. ! ! '! Hiroi no "4 ng pue ~ also 4 n 11 poor pBri ΣS
Figure Figure

Claims (1)

[Scope of Claims] A DMAC bus right configured by connecting at least a microprocessor, a DMA controller, an input/output control device, and a storage device to a common bus, and that monitors the state of bus usage rights of the common bus. A microcomputer device comprising a control unit and a bus right control unit that determines bus usage rights, wherein when the microprocessor accesses the DMA controller during execution of a DMA cycle, the microcomputer device In a bus control system that responds to a processor, when a signal indicating that DMA operation is in progress is received, the operation of the microprocessor is continued, and the access to the DMA controller sent out on the common bus is once terminated. . A bus control method, comprising: controlling an interface of the common bus of the microprocessor so as to resume access to the DMA controller.