JPH0362562A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH0362562A JPH0362562A JP19756789A JP19756789A JPH0362562A JP H0362562 A JPH0362562 A JP H0362562A JP 19756789 A JP19756789 A JP 19756789A JP 19756789 A JP19756789 A JP 19756789A JP H0362562 A JPH0362562 A JP H0362562A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- semiconductor integrated
- integrated circuit
- wiring
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 229910000679 solder Inorganic materials 0.000 abstract description 15
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 230000006378 damage Effects 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000000034 method Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 230000003685 thermal hair damage Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特に基板接続用外
部リードを有する半導体集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device having an external lead for connecting a substrate.
第4図は従来の一例の半導体集積回路装置をプリント基
板に実装した状態を示す斜視図である。FIG. 4 is a perspective view showing an example of a conventional semiconductor integrated circuit device mounted on a printed circuit board.
この種の従来の半導体集積回路装置をプリント基板に実
装する場合は、第4図に示すように、パッケージ本体1
の側面から突出している外部リード2を、プリント基板
5の対応する配線6に、はんだで溶接し、実装を行って
いた。When mounting this type of conventional semiconductor integrated circuit device on a printed circuit board, as shown in FIG.
The external lead 2 protruding from the side surface of the board was welded to the corresponding wiring 6 of the printed circuit board 5 using solder.
上述した従来の半導体集積回路装置は、プリント基板の
配線外部リードとはんだを用いることにより接合させて
いるが、この接合の際に、赤外線やレーザ6等を使って
加熱し、熱伝導により基板端子上にはんだを溶かしてい
るので、はんだが加熱される前に、外部リードの温度が
高温になり、これによって、外部リード近傍のパッケー
ジ本体の封止用樹脂がフラッフしたり、パッケージ本体
内の回路部に熱破壊を起こさせるという欠点がある。ま
た、このような現実を防ぐ為に、接合時の温度の下げた
り、加熱時間を短かくすると、はんだの溶けが悪くなり
、接合の歩留りが低下するという欠点がある。The conventional semiconductor integrated circuit device described above uses solder to join the wiring external leads of the printed circuit board, but during this joining, infrared rays, laser 6, etc. are used to heat the board terminals by heat conduction. Since the solder is melted on the top, the temperature of the external leads becomes high before the solder is heated, which may cause the sealing resin in the package body near the external leads to fluff or damage the circuit inside the package body. The disadvantage is that it causes thermal damage to the parts. Furthermore, if the temperature at the time of bonding is lowered or the heating time is shortened in order to prevent this from happening, there is a drawback that the melting of the solder becomes poor and the yield of bonding decreases.
本発明の目的は、かかる欠点を解消する半導体集積回路
装置を提供することにある。An object of the present invention is to provide a semiconductor integrated circuit device that eliminates such drawbacks.
本発明の半導体集積回路装置は、パッケージ本体の側面
より突出するとともにその先端に切込みあるいはその先
端側に貫通穴が形成される外部リードを有している。The semiconductor integrated circuit device of the present invention has an external lead that protrudes from the side surface of the package body and has a cut at its tip or a through hole formed at its tip.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は、本発明の一実施例を示す半導体集積回路装置
の斜視図である。この半導体集積回路は、同図に示すよ
うに、パッケージ本体1の側面より突出する外部リード
2aの線端部に切込み3が形成されていることである。FIG. 1 is a perspective view of a semiconductor integrated circuit device showing one embodiment of the present invention. In this semiconductor integrated circuit, as shown in the figure, a notch 3 is formed at the end of an external lead 2a protruding from the side surface of a package body 1.
それ以外は従来例と同じである。Other than that, it is the same as the conventional example.
第2図は第1図に示す半導体集積回路装置をプリント基
板に実装した状態を示す部分拡大斜視図である。このよ
うに、外部リード2の先端部に切込み3を設けることに
よって、例えば、第2図に示すように、プリント基板5
に実装した場合、配線6上に予備はんだされたはんだ7
のより大きい面積に赤外線あるいは光ビームを照射する
ことが出来、不必要に外部リード2aを加熱することな
く、はんだ7aをリフローして接合し得る。外部リード
2aの接合面積が切込み3を設けることにより増え、そ
こに溶解したはんだが入り込むことにより、機械的強度
が増し、外部リード2aと配線6とが確実に接合する。FIG. 2 is a partially enlarged perspective view showing the semiconductor integrated circuit device shown in FIG. 1 mounted on a printed circuit board. By providing the notch 3 at the tip of the external lead 2, for example, as shown in FIG.
If the solder 7 is pre-soldered on the wiring 6,
It is possible to irradiate a larger area with infrared rays or a light beam, and the solder 7a can be reflowed and bonded without unnecessarily heating the external leads 2a. The bonding area of the external lead 2a is increased by providing the notch 3, and the melted solder enters there, thereby increasing the mechanical strength, and the external lead 2a and the wiring 6 are reliably bonded.
第3図は他の実施例を示す半導体集積回路装置の斜視図
である。また、前述の実施例の外部リードの切込みの代
りに、例えば第3図に示すように、貫通穴3aを設けて
も同時の効果が得られる。FIG. 3 is a perspective view of a semiconductor integrated circuit device showing another embodiment. Moreover, the same effect can be obtained by providing a through hole 3a, for example, as shown in FIG. 3, in place of the notch in the external lead of the above-described embodiment.
以上、説明した様に本発明は、パッケージ本体より突出
する外部リードの先端部分に切込みもしくは貫通穴を設
けることによって、プリント基板の配線の接合用はんだ
に赤外線レーザ光等の熱源が、外部リードを必要以上に
加熱することなく加熱し、はんだを溶解することが出来
る。As explained above, the present invention allows a heat source such as an infrared laser beam to be applied to the solder for joining wiring on a printed circuit board by providing a cut or a through hole in the tip of the external lead that protrudes from the package body. It is possible to heat and melt solder without heating more than necessary.
従って、外部リード近傍のパッケージ本体のフラットや
、パッケージ本体内の回路部に熱破壊を起すことのない
半導体集積回路装置が得られるという効果がある。Therefore, it is possible to obtain a semiconductor integrated circuit device that does not cause thermal damage to the flatness of the package body near the external leads or to the circuit portion within the package body.
第1図及び第3図は本発明の実施例を示す半導体集積回
路装置の斜視図、第2図は第1図に示す半導体集積回路
装置をプリント基板に実装した状態を示す部分拡大斜視
図、第4図は従来の一例の半導体集積回路をプリント基
板に実装した状態を示す部分拡大斜視図である。
1・・・パッケージ本体、2.2a、2b・・・外部リ
ード、3・・・切込み、3a・・・貫通穴、5・・・プ
リント基板、6・・・配線、7・・・はんだ。1 and 3 are perspective views of a semiconductor integrated circuit device showing an embodiment of the present invention, and FIG. 2 is a partially enlarged perspective view showing the semiconductor integrated circuit device shown in FIG. 1 mounted on a printed circuit board. FIG. 4 is a partially enlarged perspective view showing an example of a conventional semiconductor integrated circuit mounted on a printed circuit board. DESCRIPTION OF SYMBOLS 1... Package body, 2.2a, 2b... External leads, 3... Notch, 3a... Through hole, 5... Printed circuit board, 6... Wiring, 7... Solder.
Claims (1)
切込みあるいはその先端側に貫通穴が形成される外部リ
ードを有することを特徴とする半導体集積回路装置。A semiconductor integrated circuit device characterized by having an external lead that protrudes from a side surface of a package body and has a cut at its tip or a through hole formed at its tip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19756789A JPH0362562A (en) | 1989-07-28 | 1989-07-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19756789A JPH0362562A (en) | 1989-07-28 | 1989-07-28 | Semiconductor integrated circuit device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0362562A true JPH0362562A (en) | 1991-03-18 |
Family
ID=16376651
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19756789A Pending JPH0362562A (en) | 1989-07-28 | 1989-07-28 | Semiconductor integrated circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0362562A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555438A (en) * | 1991-08-26 | 1993-03-05 | Rohm Co Ltd | Lead terminal structure of electronic component |
US5643835A (en) * | 1992-12-18 | 1997-07-01 | Lsi Logic Corporation | Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs |
JP2005283450A (en) * | 2004-03-30 | 2005-10-13 | Nagano Keiki Co Ltd | Pressure sensor and its manufacturing method |
JP2021121042A (en) * | 2020-03-13 | 2021-08-19 | ローム株式会社 | Semiconductor device |
-
1989
- 1989-07-28 JP JP19756789A patent/JPH0362562A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0555438A (en) * | 1991-08-26 | 1993-03-05 | Rohm Co Ltd | Lead terminal structure of electronic component |
US5643835A (en) * | 1992-12-18 | 1997-07-01 | Lsi Logic Corporation | Process for manufacturing and mounting a semiconductor device leadframe having alignment tabs |
JP2005283450A (en) * | 2004-03-30 | 2005-10-13 | Nagano Keiki Co Ltd | Pressure sensor and its manufacturing method |
JP2021121042A (en) * | 2020-03-13 | 2021-08-19 | ローム株式会社 | Semiconductor device |
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