JPH0359465A - Waveform input device - Google Patents

Abstract

PURPOSE:To measure an accurate jitter quantity by finding the time difference between a trigger signal and a clock signal by utilizing the leading edge of a clock signal which is generated for the 2nd time after the generation of the trigger signal. CONSTITUTION:An input signal is passed through a preamplifier 1 and sampled and held 2, and the signal is sampled with the clock signal generated by the clock generator 11 and stored in a fast memory 4 through an A/D converter 3. Further, the input signal is applied to a trigger decision circuit 7 and compared with a trigger voltage as a reference level to generate the trigger signal. Then the trigger signal from the circuit 7 is applied to a time difference decision circuit 10 together with the clock signal and the time difference between the leading edges of the trigger signal and clock signal is measured. Then an MPU 12 stores waveform data, inputted to the memory 4, in a main memory 5 according to the decision result while maintaining correct time relation based upon the trigger signal. Then the data stored on the memory 5 is displayed on a display device 6.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a waveform capture device, and particularly to a waveform capture device for repeatedly capturing signals in a digital oscilloscope or the like.

Regarding conventional digital oscilloscopes, for example, Japanese Patent Application Laid-open No. 59
As described in Japanese Patent No. 34164, an input signal is amplified to a desired value in a preamplifier and then applied to a sample and hold circuit, where it is sampled and held using a sampling clock generated by a clock generator. This hold value is then stored in high speed analog memory.

On the other hand, the signal branched from the preamplifier is applied to a trigger recognition circuit to output a trigger signal. A trigger signal is applied to a presettable counter and, together with a clock signal, controls the high speed analog memory. When transferring the data stored in this analog memory to the waveform memory for display or calculation, the leading edge of the trigger signal and the leading edge of the next sampling clock are used to calculate the time difference between these leading edges. Based on the measured values, the trigger time and sampling time are rearranged to maintain the correct positional relationship.

This allows display with less jitter to be obtained, and by repeating this operation during sampling, it is possible to accurately capture waveforms even for input frequencies exceeding the Nyquist frequency using the equivalent sampling method.

FIG. 7 shows an example of a time difference measuring circuit used in the conventional example. In FIG. 7, 130 is a first flip-flop, 1-31 is a second flip-flop,
132 is an AND gate, 134 is a constant current source, 135 is a first switch, 136 is a second switch, 137 is a capacitor, 138 is a voltage follower, 139 is an A/
D (analog/digital) converter, 140 is MPU
(Microprocessor unit), 141 is a control section.

The operation of this conventional example will be explained with reference to the time chart of FIG. A trigger signal is applied to the CK terminal of the first flip-flop 130, and the second flip-flop 13
A clock signal is given to the CK terminal of 1. Then, the second switch 136 is turned off by canceling the clear signal given from the control section 141 and the capacitor 137 is made ready for charging.Then, the trigger recognition signal is transmitted from the Q terminal of the first flip-flop 130 to the AND gate 132.
Enter. The timing at this time is (150
) to (153).

Next, the output of the AND gate 132 causes the first switch 1
35 is turned on, and the capacitor 137 is charged by the current of the constant current source 134 via the first switch 135. At this time, the constant current value of the constant current source 134 is
The capacitance value of C1 is the conduction time of the first switch 135 is T1
If the voltage appearing across the capacitor 137 is V, then v
-T・1/C (However, the initial charge of capacitor 137 is 0
shall be. ) is given by If C1I is constant, this is ■
indicates that the value is proportional to T. Then, the trigger recognition signal is transferred to the D of the second flip-flop 131.
It is applied to the terminal to make it ready for data input. Therefore, after the trigger is recognized, the leading edge of the first clock signal inverts the output of the second flip-flop 131 and turns off the first switch 135. That is, after the Q output of the first flip-flop 130 is inverted by the trigger signal, the Q output of the second flip-flop 131 is inverted by the clock signal.
The time until the 100 output is inverted is the time T1 for charging the capacitor 137, that is, the time to be corrected to remove jitter. Therefore, the charging voltage V of the capacitor 137 is applied to the A/D converter 139 via the voltage follower 138, and after the first switch 135 is turned off, an output is obtained by digitally converting this value, and this output is sent to the MPU 1.
40 performs appropriate arithmetic processing and outputs the jitter amount.

This situation is shown in (154) to (157) in FIG.

Problems to be Solved by the Invention However, in the conventional time difference measuring circuit described above, the amount of jitter measured fluctuates due to variations in the constituent elements, changes in response time due to temperature changes, etc., and adjustment is required for accurate operation. There was a problem. Also, the seventh
In the circuit shown in the figure, the D input (trigger recognition output) and the CK large input clock signal of the second flip-flop 131 are applied almost simultaneously, and the output of this flip-flop 131 is in an unstable state ( metastable state), and in such cases, there is a problem in that the amount of jitter cannot be accurately obtained.

The present invention solves these conventional problems,
It is an object of the present invention to provide an excellent waveform capture device that can prevent erroneous measurements of the amount of jitter and obtain accurate amounts of jitter.

Means for Solving the Problems In order to achieve the above object, the present invention provides a waveform capture device with information on the time between the leading edge of a trigger signal and the leading edge of the next generated clock signal and one period of the clock signal. The present invention is equipped with a time difference measuring circuit that calculates the time corresponding to the leading edge of the trigger signal and the leading edge of the clock signal immediately before it from the time of 1 minute and the time of 2 cycles of the clock signal.

According to the present invention, the jitter caused by the unstable state of the flip-flop is detected by measuring the time difference between the leading edge of the trigger signal and the next leading edge of the clock signal that occurs thereafter using a time difference measuring circuit. In addition, by measuring the maximum jitter amount and minimum jitter amount each time the trigger jitter amount is measured, and performing appropriate calculations using these three jitter amounts, temperature It is possible to obtain an accurate amount of jitter by canceling out fluctuations in measured values due to the effects of factors such as the above, thereby realizing a waveform capture device with a small amount of jitter.

Embodiment FIG. 1 is a schematic block diagram showing the configuration of an embodiment of the present invention. In Fig. 1, 1 is a preamplifier that amplifies a periodic analog input signal to a desired level, and 2 is a sample hold, which samples and holds the output signal of preamplifier 1 in synchronization with a clock signal. . 3 is A
/D converter, 4 is a high-speed memory which is a first memory that temporarily stores the output data of the A/D converter 3 at high speed according to the address signal and outputs it at low speed; 5 is the output signal of the high-speed memory 4 and others; A main memory is a second memory for storing signals in the device, and 6 is a display device such as a CRT display. Reference numeral 7 denotes a trigger determination circuit which receives a portion of the signal amplified by the preamplifier 1 and determines whether or not the signal exceeds a reference level set by the operator. 8 is an address counter that starts and ends counting in response to a trigger signal, and 9 is a clock frequency divider that divides the frequency of a clock signal and outputs it to the address counter 8.

IO is a time difference measuring circuit that measures the time difference between the trigger signal and the clock signal, and 11 is a clock generator that outputs a sampling clock signal into the device. 12 is M
PU (microprocessor unit), 13 is RAM
(random access memory), 14 is ROM (read only memory), 15 is l10 (input/output control device)
and transmit and receive data signals through the path lines 16, respectively.

Next, the operation of the above embodiment will be explained. In FIG. 1, a clock generator 11 obtains a clock signal with a stable period using a crystal oscillator or the like, and samples and holds this clock signal using a sample hold 2.
, the A/D converter 3, the clock frequency divider 9, and the time difference determination circuit 10. The clock signal frequency-divided by the clock frequency divider 9 to an arbitrary predetermined period is applied to the address counter 8 to generate a predetermined address, which is then applied to the high-speed memory 4. The input signal is applied to a sample hold 2 via a preamplifier 1, sampled by a clock signal generated from a clock generator 11, immediately converted to digital data by an A/D converter 3, and stored in a high speed memory 4. The input signal is also input to preamplifier 1
The voltage is applied to the trigger determination circuit 7, and similarly to the conventional trigger circuit of an oscilloscope, the voltage is compared with an arbitrarily set reference level trigger voltage to generate a trigger signal.

This trigger signal is applied to the address counter 8, and the address counter 8 successively generates the addresses required for the high-speed memory 4 based on predetermined settings.
The data from is loaded into the high-speed memory 4. The address counter 8 simultaneously counts the number of data to be loaded into the high-speed memory 4, and when it reaches a predetermined number, the high-speed memory 4 stops loading data to maintain the waveform data of the input signal, and then sends a loading end signal. is generated and sends an interrupt signal indicating the end of loading to the MPU 12 via the bus 16. Note that the address counter 8 can perform conventional pre-trigger and post-trigger operations.

In addition to the above, instructions (programs) for the MPU 12 to perform a series of arithmetic operations are written in the path 16.
OM14, RAM13 for storing calculated values and information;
A main memory 5 for storing waveform data and calculation data, a display device 6 for displaying waveform data and various information, and an l1015 for connection with an operation panel and external equipment.
etc. or connected. The display device 6 is a conventional CRT.
vector scanning and rask scanning display devices that utilize
Alternatively, it may be a liquid crystal display or a plasma display using a dot matrix. The l1015 includes a keyboard for operating the device, a panel using a rotary encoder, an interface with external equipment, etc., and transmits device settings to the MPU 12. MPU12 is ROM14
Each circuit block is controlled by a program stored in the controller. Note that detailed control lines are omitted in FIG. 1.

The trigger signal from the trigger determination circuit 7 is sent to the time difference determination circuit 1.
0 along with a clock signal and the time difference between the leading edge of the trigger signal and the leading edge of the clock signal is measured. Upon receiving the interrupt signal from the address counter 8 indicating the end of waveform capture, the MPU 12 determines whether the waveform data captured in the high-speed memory 4 is stored in the main memory while maintaining the correct time relationship based on the trigger signal based on the measurement result of the time difference determination circuit 10. memory 5
generating an address signal or an address control signal for each acquisition cycle to transfer the waveform data from the high speed memory 4 to the main memory 5 so that the waveform data is sorted and stored in the main memory 5;
Store. The data stored in the main memory 5 is displayed on the display device 6
displayed by.

Next, details of the time difference determination circuit 10 will be explained with reference to FIG. 2. In Figure 2, 21.22 is the resistance, 2
3.27.28.29.30 is a transistor that controls charging and discharging of the capacitor 24, and 25 is a FET (field effect transistor) that transfers the charge charged to the capacitor 24.
, 26 is a Schottky junction diode for improving the disturbance in the charging flow of the capacitor 24, 31.32.33 is a constant current source, 40.41 is a buffer, 42 is a data selector for obtaining different time difference outputs, 43. 44.45 is NO
R gate, 46 is AND gate, 47.48.49.5
0 is a cascade-connected flip-flop, 51 is a control circuit, 52 is an amplifier, 53 is an A/D converter, 54.55.5
6 is a register, and 57 is an MPU (microprocessor unit) system.

Next, the operation of this time difference determination circuit 10 will be explained. Flip-flops 47-50 are cleared in the initial state. Further, the S terminal of the flip-flop 47 is at L level. At this time, flip-flops 47 to 5
0's Q output is L level, and flip-flop 4
Since the inverted output page 7 is at H level, the transistor 28 is on, the transistor 23 is also on, and the capacitor 2
Both ends of the capacitor 24 are short-circuited, and the charge in the capacitor 24 is discharged. Also, at this time, the outputs of the NOR gates 43 to 45 are all at L level, and regardless of the setting of the data selector 42, the transistor 29 is off and the transistor 30 is on.

When measuring trigger jitter, the data selector 42 is set to be connected to the NOR gate 43, and first the ANDNO
After the gate is enabled, clearing is released and a trigger signal is applied, the Q output of the flip-flop 47 goes to H level, the output goes to L level, and the transistor 28
．． 23 is turned off, and the capacitor 24 can be charged. Then, the output of the NOR gate 43 becomes H level, so the transistor 29 is turned on, the transistor 30 is turned off, and the current set by the constant current source 32 is transferred to the capacitor 2.
4 and start charging. This time is set to 0 as shown in FIG. Further, when the Q output of the flip-flop 47 becomes H level, the Q output of the flip-flop 48 becomes H level by the first leading edge of the clock signal after the generation time of the trigger signal applied to the CK terminal of the flip-flop 48. . Furthermore, this is flip-flop 49
The leading edge of the next clock signal sets the flip-flop 49, and the Q output of the flip-flop 49 becomes H level. Then, this time, NOR gate 43
The output becomes L level, the states of the transistors 29 and 30 are reversed again, current no longer flows through the capacitor 24, and the capacitor 24 retains the charge up to that point. Assuming that this time is it, a voltage Vl proportional to the time to obtained by subtracting (0 from tl) is held across the capacitor 24. At this time, the diode 26 Improves excessive disturbance of charging flow.

Now, the stoppage of charging of the capacitor 24 is transmitted to the control circuit 51, and the holding voltage of the capacitor 24 is sent from the FET 25 to the amplifier 52, and after being amplified by the amplifier 52, the A/
It is immediately converted into digital data (8 bits in this example) by the D converter 53 and stored in the register 54. This series of time charts is shown from (81) in Figure 3 to (
94).

Next, when the measurement of Vl is completed, the operation for calibration is immediately started. That is, the AND gate 46 is disabled to prohibit trigger input, and the data selector 42 is set to N.
Switch to OR gate 45 side, flip-flop 47~
Clear all 50. Next, the S input of the flip-flop 47 is set to H level, and the Q output is set to H level. Then, the clock signal causes flip-flops 48 and 4 to
9 are excited in sequence, and a positive pulse with a time width i20 corresponding to one cycle of the clock signal is generated at the output of the NOR gate 45 as shown in FIG. 4, and a voltage V2 corresponding to this time width j20 is generated. is held in the capacitor 24. This voltage 2 is applied to the FET 25 after the transistor 29 is inverted.
It passes through an amplifier 52, is A/D converted by an A/D converter 53, and is stored in a register 5 as time data for one clock cycle.
5 is stored.

Furthermore, this time, the data selector 42 is changed to the NOR gate 44.
switch to the side, clear all flip-flops 47 to 50, and perform the same operation.

Then, the flip-flops 48 to 50 generate a time width j3o corresponding to two clock cycles, as shown in FIG.
pulses are available at the output of NOR gate 44. Then, a voltage vj corresponding to this output pulse width t30 is obtained in the capacitor 24, A/D converted, and stored in the register 56 as time data for two clock cycles. The above series of time charts are shown from (101) to (116) in Figure 4.
) are shown up to.

Here, v2 is a voltage corresponding to one clock cycle, V3 is a voltage corresponding to two clock cycles, and Vl
is a voltage corresponding to the time between the leading edge of the trigger signal and the leading edge of the next next clock signal, and has a value between v2 and v3.

However, these voltage values change initially and/or over time due to variations in the elements that make up the circuit, temperature changes, changes over time, adjustment errors, etc., and an error voltage proportional to the amount of offset and charging time is generated. Contains.

As explained in the conventional example, the charging voltage V is V=T・Ilo
However, if Ilo is set to K, the error amount of K is α, and the offset amount is β, then the charging voltage V° including the error is V'=T・(K+α)+β. expressed. Therefore, Vl, V2, and v3 may each contain errors, but since VIV2 and ■3 are measured continuously over a very short period of time, α and β are can be considered constant. Therefore, the error can be canceled by reading the voltages V1, V2, and V3 from the registers 54, 55, and 56, respectively, and performing the following calculations by the MPU system 57.

VJ= (V3-Vl)/(V3-V=) where VJ is the time corresponding to the leading edge of the trigger signal per clock period and the leading edge of the immediately preceding clock signal, and the clock period is added to this value. The actual time difference can be found by multiplying by

According to the above embodiment, a series of operations is performed every time the time difference between the trigger signal and the clock signal is measured, so it is stable against changes in ambient temperature without requiring precise adjustment or adding a temperature correction circuit. It is possible to obtain an accurate time difference, thereby realizing a waveform capture device with less jitter. Note that the MPU system 57 in FIG.
A similar effect can be obtained even if it is used also as the MPU 12 shown in FIG. Furthermore, the functions of the registers 54 to 56, the control circuit 51, etc. can also be performed within the MPU system 57. In addition, the same effect can be obtained by adding a new flip-flop between the flip-flop 48 and the flip-flop 49.

FIG. 5 shows the main parts of another embodiment of the invention.

In this embodiment, D/A converters 61 and 62 are added to the A/D converter 53, registers 54, 55, 56, and MPU system 57 of the embodiment shown in FIG. It is connected to the reference terminal of the A/D converter 53. In this embodiment, the aforementioned voltage V2 corresponding to one clock cycle or a slightly higher voltage is transferred from the D/A converter 62 to the reference terminal of the A/D converter 53, and the voltage V3 corresponding to two clock cycles or this voltage is transferred from the D/A converter 62 to the reference terminal of the A/D converter 53. By applying a slightly lower voltage from the D/A converter 61 to the + reference terminal based on the voltage obtained in the previous cycle of a certain measurement cycle, the resolution of the A/D converter 53 can always be maximized. It can be used for. In this embodiment, + and - sense terminals were used, but as shown in FIG. You can get the same effect by converting it. These values can be easily converted and provided by the MPU system 57.

Effects of the Invention As is clear from the above embodiments, the present invention utilizes the leading edge of the clock signal that occurs second from the trigger signal generation time to determine the time difference between the trigger signal and the clock signal, and calculates the time difference between the trigger signal and the clock signal at each measurement time. Since the time difference of one clock cycle and the time difference of two clock cycles are calculated, and the accurate time difference between the trigger signal and the clock signal is calculated from these time differences, a signal with less jitter can be captured. Also, since calibration is performed every time jitter is measured,
It is possible to accurately measure the amount of jitter without adjustment, thereby realizing a digital oscilloscope or the like capable of stable waveform display and waveform measurement with little jitter.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a schematic block diagram of a waveform acquisition device showing an embodiment of the present invention, Fig. 2 is a circuit diagram of a time difference measuring circuit in the same device, and Figs. 3 and 4 are the same. Timing chart in the circuit, FIG. 5 is a circuit diagram of the main part of a time difference measuring circuit in another embodiment of the present invention, FIG. 6 is a circuit diagram of the main part similar to FIG. 5, and FIG. 7 is a conventional waveform capture FIG. 8 is a schematic block diagram of a time difference measuring circuit in the apparatus, and is a timing chart in the circuit shown in FIG. 7. 1... Preamplifier, 2... Sample hold, 3...
... A/D converter, 4... High-speed memory, 5... Memory, 6... Display device, 7... Trigger determination circuit, 8...
...Address counter, 9...Clock divider, 10
...Time difference determination circuit, 11...Clock generator, 1
2...MPU. 13...RAM, 14...ROM, 15...Il
o, 21.22... Resistance, 23.27.28.29.
30...Transistor, 24...Capacitor, 25
...FET126...Schottky diode, 3
1.32.33...constant current source, 40.41.../<
Tsufa, 42...Data selector, 43.44.45
...NOR gate, 46...AND gate, 47.
48.49.50...Flip-flop, 51...
Control circuit, 52...Amplifier, 53...A/D converter, 54.55.56...Register, 57...MPU
system.

Claims (1)

[Claims] a clock generator that generates a clock signal with a predetermined period;
an analog/digital converter that digitally converts a periodic analog input signal using the clock signal; a first memory that stores the digitally converted input signal; and a predetermined number of input signal data transferred from the first memory. a second memory for storing information, a trigger determination circuit for generating a trigger signal by comparing the input signal with a reference level, and a time and clock between the leading edge of the trigger signal and the leading edge of the next clock signal generated next; a time difference measuring circuit that calculates the time corresponding to the leading edge of the trigger signal and the immediately preceding leading edge of the clock signal from the time corresponding to one cycle of the signal and the time corresponding to two cycles of the clock signal; A waveform capturing device comprising means for sequentially capturing an input signal captured in one memory into two memories every plural cycles with reference to the trigger signal.