JPH0358621A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To ascertain a logical voltage level of an output signal without a malfunction by passing an output signal of a 1st stage NOT circuit through an even number of stages of NOT circuits to retard the signal hourly and feeding back it. CONSTITUTION:P-channel MOS transistors(TRs) (PMOST) QP1-QP3 and N- channel MOS TRs (NMOST) QN1-QN3 constitute a 1st stage NOT circuit. Moreover, the 1st stage in 2-stage of NOT circuits is composed of a PMOST QP6 and an NMOST QN5 and the 2nd stage is composed of a PMOST QP6 and an NMOST QN6. Then an input signal A is fed in common to the gates of the PMOST QP1, QP2 and NMOST QN1, QN2 and the output signal of the 1st stage NOT circuit is fed back to the gates of the PMOST QP3 and NMOST QN3 via the 2-stage NOT circuits while being delayed hourly. Thus, even when the level of an input signal is at an intermediate level between high and low logic voltages, the logical voltage level of the output signal is ascertained without the malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to an input bath sofa circuit composed of MOS transistors.

[Traditional techniques]

The recent development of semiconductor integrated circuit devices has been remarkable, and in these integrated circuit devices, the input Hannoff circuit, which takes input signals from the outside into the integrated circuit device, determines the characteristics such as the switching level of the input signal. This is an important circuit section.

FIG. 2 shows an example of the structure of a conventional input buffer circuit of this type. In Fig. 2, T1 is human power ☆: 11, T2'' is output 3: ii, 8゜ is an external input signal input through input terminal T?, and B'LJ output terminal T2.
'' is the output signal of the input Hannover circuit outputted through ``Q1, '' to Q, .' are P-channel type Most-transistors, QI1 to QN4, respectively.
” are N-channel type MOS transistors.

The input buffer circuit shown in FIG. 2 is constructed by connecting four stages of inverting circuits using complementary MOS transistors.

Next, the operation of this manual buffer circuit will be explained. First, the input signal 8 is changed from the logic voltage "I" to the logic voltage "L".
”Explain the case where

Initially, the input signal A゛ is a logic voltage ゛■{'', so
P-channel type MOS transistor Q, is off, and N-channel type MOS transistor QN is on. Therefore, the P-channel type M○S transistor Q,2' is on, the N-channel type MOS transistor QN'' is off, and the P-channel type MOS transistor QP1'
is off, N-channel MOS transistor QN・,
゛ is on and ? ) Channel type MOS transistor Q.゛ is on, N-channel MOS transistor Q.

4' is off, and the output signal B' is a logic voltage "H"'.

Input signal 8' goes from logic voltage 'I-1' to logic voltage 'L'
When the transition begins, the P-channel MOS transistor Q.゛ is on, N-channel MOS transistor QN
1 is off. Therefore, P-channel type MOS transistor Q,2' is turned off, N-channel type MOS transistor Q9' is turned on, and P-channel type MOS transistor Q,2' is turned off.
S transistor Qr3 is turned on, N-channel type MOS transistor QN3 is turned off, and P-channel type MOS
Transistor QP4 is off, N-channel MOS}
Ranjisk Q. " is turned on, and the output signal B becomes the logic voltage "L".

Conversely, the human input signal A゛ changes from the logic voltage "L," to the logic voltage "
When the signal goes to "H", the operation is exactly the opposite of the above.

[Problem to be solved by the invention]

In a human-powered Huffer circuit in which an even number of stages of negative circuits using phase-sleeve MOS transistors are connected, such as the conventional example shown in Fig. 2,
When the input signal A' is at an intermediate level between the logic voltage "■{" and the logic voltage "L", the P-channel MOSI transistor Q,,' to which the input signal A' is applied is
and an N-channel MOS transistor Q. , ' are both turned on, and the output of this first-stage NOT circuit also becomes an intermediate level, and as a result, the final output signal B' is also difficult to settle on either the logic voltage "I" or the logic voltage "L", resulting in malfunction. Cheap.

In addition, the P-channel type MOS transistor QP of the manual stage
1 and N-channel type MOS transistors QNl'' are both turned on, the P-channel type MOS transistors Q,.,' are turned on by the power supply voltage VDI1.
and N-channel MOSI-Randjisk QN,'
A large current will flow through the , which increases the power consumption and the supply voltage. There is a problem in that this leads to a decrease in the voltage and has an adverse effect on other circuits as well.

Therefore, an object of the present invention is to be able to determine the logic voltage level of an output signal without malfunction even if the level of the input signal is at an intermediate level between high and low logic voltages, and to reduce power consumption. An object of the present invention is to provide an input buffer circuit that can stabilize the operation of the entire circuit.

[Means to solve the problem]

The human-powered buffer circuit of the present invention connects the drain of a first P-channel MOS transistor and the source of a second P-channel MOS transistor, and connects the first P-channel MOS transistor to the third D-channel MOS transistor. MOSI-transistors are connected in parallel, the drain of the first N-channel MOS transistor and the source of the second N-channel MOS transistor are connected, and the third N-channel MOS transistor is connected to the first N-channel MOS transistor. The MOS transistors are connected in parallel, the drain of the second P-channel MOS transistor and the drain of the second N-channel MOS transistor are connected, and the first and second P-channel MOS transistors and the first and first Connect the human power terminal to the commonly connected gate 1 of the second N-channel type MOSI-transistor 7, and connect the second P-channel type MOS transistor and the second N-channel type MOS transistor.
The input terminals of the even-stage inverting circuits are connected to the commonly connected domain I domains of the channel-type MOS transistors, and the output terminals of the even-numbered inverting circuits are connected to the third P-channel MOS transistors.
The configuration is such that the transistor and the third N-channel MOS transistor are feedback-connected to the case 1.

[For production]

According to the structure of this invention, the third channel type MO
Since a signal with a phase opposite to the input signal is returned to the SI~ transistor and the third N-channel MOS transistor through an even number of stages of inverting circuits with a time delay, the state transition of the human input signal is performed in the first stage of inverting circuit. The configuration of the first and second P-channel MOS transistors and the first and second N-channel MOS I-transistors according to
The state transitions of the third P-channel MOS transistor and the third N-channel MOS transistor are delayed compared to the m r'A transition.

As a result, when the series circuit of the first and second P-channel type MOS1 transistors changes from OFF to ON due to the state transition of the input signal, the third P-channel type MOS1 transistor changes state before that. It is turned on first. On the other hand, when the series circuit of the first and second N-channel MOS transistors changes state from on to off, the third N-channel MOS transistor
+- Ranjisk is turned off first. For this reason, when the human input signal undergoes a state transition, the operation of the P channel example and the operation of the N channel side of the first stage NOT circuit become unbalanced. The threshold values on the P channel side and the N channel side are both higher than the intermediate level between high and low.

Therefore, when the level of the human input signal is an intermediate rail between high and low logic voltages, the second 1) channel type MOS
A common train of the transistor and the second N-channel MOS transistor is determined to a logic voltage “I1”;
Logical voltage level of output signal? It can be confirmed without any malfunction. Furthermore, since the operation on the P channel side and the operation on the N channel side of the first stage NOT circuit become unbalanced during the state transition of the input signal, the transition time can be shortened, and power consumption can be kept low. As well as being able to
The drop in power supply voltage is also small, and the operation of the entire circuit can be stabilized.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of an input buffer circuit according to an embodiment of the present invention.

This human-powered buffer circuit in Figure 1 consists of 1) channel type M
OS transistor Q. + Q P ,) Q P
S. Q p bQr. Supply voltage V to each source of 4
on, and the N-channel MOS transistor Q. ,,QN. Q N S , Q N +.
．． Each source of Q■ is grounded. In addition, P-channel type MOS+-Ransisk Q. train and P-channel type MOS+ transistor Q, 2 source and P-channel type MOSI transistor? P3 is connected to the drain of N-channel type MO81 transistor QN. the drain of the N-channel MOS transistor QN2 and the source of the N-channel MOS transistor QN:1 of the N-channel MOS transistor QN:l.
・The train of the P-channel type MOS transistor Qr2 is connected to the drain of the N-channel type MOS transistor QN■. The above P-channel MOSI transistor Q. ~Q, 3 and N-channel MOSI-ranjisku Q, +1 ~Q, , 1 constitute a first-stage inverter.

In addition, P-channel type MOS transistors Q, Q, ■ and N-channel type MOS transistor Q +
1 1. The human power terminal '1' is connected to the commonly connected gate of QN■.

In addition, the input terminals of even-numbered stages, for example, two-stage inverters, are connected to the commonly connected drains of the P-channel MOSI transistor QPZ and the N-channel MOSI transistor QN, and the output terminals of these two-stage inverters are P-channel type MOS transistor Q1. , and the gate of an N-channel MOSI transistor QN3.

In the two-stage inverting circuit described in Section 2, the first stage (the second stage from the perspective of the entire input buffer circuit) is a P-channel MOS.
It is composed of transistors Q, 5 and N-channel type MOS transistor Q1l, and the second stage (the third stage when viewed from the whole human-powered buffer circuit) is a P-channel type MOS transistor.
S+-Landisque Q, and N-channel MOSI
- It consists of a transistor QN. A P-channel type MOS+ transistor Q1 . , and the commonly connected gates of the N-channel MOS transistor QN5 are connected, and the commonly connected gates of the P-channel MOS transistor QP5 and the N-channel MOS transistor Q
P channel type MOS on the commonly connected 1/rain of N5
The commonly connected gates of transistors Q, 6 and N-channel type M○S transistor QN6 are connected, and P-channel type MOS transistors Q, . 6 and N-channel type MOSI--the drains of the transistor Qll6 connected together are connected to the P-channel type MOSI transistor Qll6 as described above.
os+, transistors Q1 and 3 and N-channel type MO
S+ is connected in feedback to the gate 1 of transistor QN3.

Note that the output terminal of the two-stage inverter is connected to the human power terminal of the inverter in another stage (which is the fourth stage in terms of the entire input Kahanoff circuit), and the output terminal of the inverter in the other stage. is connected to the output terminal B of the input Hannover circuit.In this case, the other stage of the inverting circuit is a P-channel MOS
It consists of a transistor QP4 and an N-channel MOS transistor Q)14, whose commonly connected gate 1 is connected to a commonly connected gate 1 of a P-channel MOS transistor Q,6 and an N-channel MOS transistor QN6.
The output terminal B is connected to the common drain.

Next, the operation of this human-powered Hanofa circuit will be explained. First, the human input signal A changes from the logic voltage “H” to the logic voltage ゜“I,”
”Explain the case where

Initially, the human input signal A was a logic voltage "H"12? , P-channel MOS transistors Q, Q, , 2 are off, P-channel MOS transistors Q, 3 are on, N-channel MOS transistors QNI, QN
■ is on, N-channel MOSI transistor QN3
is off. Therefore, P channel type MOS+-
Ranjisk Q. ．． S is on, N-channel MOS transistor QN is off, P-channel MOS transistor Q,6 is off, N-channel MOS transistor QH is on, and P-channel MOS transistor Q. is on, N-channel MOSI transistor QN4 is off, and the output signal B is a logic voltage "H".
” is.

When the human input signal 8 starts to transition from the logic voltage "■1'" to the logic voltage "L", the P-channel MOS transistor Q
Pl, QP2 are on, N-channel MOS transistor QNI. QN■ turns off. At this time, P-channel type MOS transistors Q, . ,Q. ．． The feedback signal to the gate of (has the opposite phase to the human input signal 8) is the input signal A
Is the input signal A a logic voltage due to the delay caused by passing through an even number of stages of NOT circuits? “H” to logic voltage “”
Immediately after starting the transition to “L”, the ■) channel is
P-channel type MOS transistors Q■, Q, and 3 operate in parallel, but the N-channel type MOS transistor Q■, Q, and 3 operate in parallel.
OSI-Landisque QN, is off, N-channel type M
Since the OS transistor QNI operates independently, the operation on the P-channel side and the operation on the N-channel side become unbalanced.

Therefore, the P-channel MOS transistor Q,2
The common train of the N-channel MOSI transistor QN2 quickly becomes the logic voltage "H" state, and when the level of the input signal 8 is at the intermediate level between high and low, it is already determined to be the logic voltage "H". . Therefore, the transition time of the output potential of the NOT circuit in each stage is short, and the power supply voltage V
P channel type MOS transistor Q. ~
Q, 6 and N channel type MOSI-ransistor Q■
~The current flowing through QN6 in series can be suppressed.

Then, when the common drain of the P-channel type MOS transistor QP2 and the N-channel type MOS transistor Q8■ becomes the logic voltage "■4", the P-channel type MOS transistor QP2
OS} Runsista Q. ．． , , and N-channel MO
The common 1-rain of S+1 transistor QN5 becomes a logic voltage "I," and ■) channel type MOSI~transistor Q r l. The common train of N-channel type MO81 and transistor Q ++ b is logic voltage “H”.
becomes. Therefore, the P-channel MOS transistor Q. The common drains of the N-channel MOS I-randisk QN4 become the logic voltage "■,", and the output signal B becomes the logic voltage "L".As a result, the P-channel The type MOS+- transistor Q,3 is turned off, and the N-channel type MOSL transistor QN3 is turned on.

Conversely, input signal 8 changes from logic voltage "L" to logic voltage "'I".
1”, the operation is exactly the opposite of the above.

〔Effect of the invention〕

According to the human-powered buffer circuit of the present invention, the first-stage inverting circuit is formed by connecting the first and second P-channel MOS transistors and the first and second N-channel non-channel MOS transistors in series; A third P-channel type MOS + one transistor is connected in parallel to the first P-channel type MOS + one transistor, and
The first N-channel MOSI transistor is connected to the third N-channel MOSI transistor.
Channel type MOSI transistors are connected in parallel, and an input signal is commonly supplied to the gates of the first and second 1) channel type MOS transistors and the first and second N channel type MOS transistors, and The structure is such that the output signal of the first-stage inverter is fed back to the third P-channel MOS transistor and the third N-channel MOS transistor with a time delay through the even-numbered inverter circuits. , the operation of the P channel side of the first-stage negative circuit during the state transition of the human input signal, and the N
The operation on the channel side becomes unbalanced, and the level of the human input signal is high. Even if the logic voltage level of the output signal is at the intermediate level of the low logic voltage, it is possible to determine the logic voltage level of the output signal without malfunction. In addition, at the time of state transition of input signal B, the transition time can be shortened because the operation on the 1) channel side of the first stage NOT circuit and the operation on the N channel side become unbalanced.
Not only can power consumption be kept low, but the drop in power supply voltage is also small, and the operation of the entire circuit can be stabilized.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an input buffer circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing the configuration of an example of a conventional Kaha-Sofa circuit. A...Input signal, B...Output I Δ, 'F,...
Manual terminal, T2...output terminal, Q. ~Q, 6...P
channel type MOS]・ransistor, Q. ~QN6...
・N-channel type MOS transistor TI T2 C'p+10P6 QNI10N6 ---Hitoreki Dante Ilsan7) Rikiko---Pu-Yangmer type MOS transistor---N→
-Yan Graduation Le"MOS l-Langister Diagram 2

Claims (1)

[Claims] connecting the drain of a first P-channel MOS transistor and the source of a second P-channel MOS transistor, and connecting a third P-channel MOS transistor in parallel to the first P-channel MOS transistor; connecting the drain of a first N-channel MOS transistor and the source of a second N-channel MOS transistor, and connecting a third N-channel MOS transistor in parallel to the first N-channel MOS transistor; The drain of the second P-channel MOS transistor and the drain of the second N-channel MOS transistor are connected, and the first and second P-channel MOS transistors and the first and second N-channel An input terminal is connected to the commonly connected gates of the type MOS transistors, and an input terminal of an even stage inverter is connected to the commonly connected drains of the second P-channel type MOS transistor and the second N-channel type MOS transistor. An input buffer circuit characterized in that the output terminals of the even stage inverting circuits are feedback-connected to the gates of the third P-channel MOS transistor and the third N-channel MOS transistor.