JPH04145717A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To prevent fluctuation of a potential of power supply and ground when a transistor(TR) is turned on without deviation in a current peak flowing to each TR by inputting a delay signal via a delay circuit sequentially to each split gate of P and N channel TRs. CONSTITUTION:When a level of an input signal A changes from 0 to 1, a TR N1 is turned on and a TR P1 is turned off. A TR N2 is turned on with a delay signal H and a TR N3 is turned on with a delay signal I. Moreover, since pull-up TRs P4, P5 are turned on by a signal B, TRs P1-P3 are turned off without awaiting signals D, E. When a level of the input signal A changes from 1 to 0, the TR P1 is turned on and the TR N1 is turned off, The TR P2 is turned on by the signal D and the TR P3 is turned on by the delay signal E. Since pull-down TRs N4, N5 are turned on by the signal F, the TRs N1-N3 are turned off without awaiting input signals H, I. Thus, the fluctuation in the potential of power supply and ground due to charge/discharge current is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output buffer circuit in a semiconductor integrated circuit.

[Conventional technology]

Conventionally, this type of output buffer circuit has been constructed by dividing the gate widths of a P-channel transistor and an N-channel transistor, respectively, as shown in FIG. 2, and dividing these divided P-channel transistors PL, P2 . The input signal for the P-channel transistors is commonly input to the gate of P3, and the input signals for the N-channel transistors Nl, N2 . N3
An input signal for the N-channel transistors was commonly input to the gates of the transistors.

[Problem to be solved by the invention]

The conventional output buffer circuit described above has a divided P
Channel transistors PL, P2゜P3 or N-channel transistors Nl, N2゜N3 are turned on at the same time,
When outputting data to output terminal 0, a large charging or discharging current flows, causing a potential drop, causing fluctuations in the power supply and ground potentials, which can cause internal circuits to malfunction and worsen access time. There are drawbacks.

[Means to solve the problem]

The output buffer circuit of the present invention includes a P-channel transistor and an N-channel transistor whose gate widths are divided and whose drains are interconnected, and a transistor which sequentially delays a common input signal to each of the divided gates of the P-channel transistor. a second delay circuit that sequentially delays a common input signal to each of the divided gates of the N-channel transistor;
P that pulls up the signal output from the first delay circuit
It includes a channel transistor and an N-channel transistor that pulls down the signal output from the second delay circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

Input signal A becomes an input to inverters 1 and 3, output B of inverter 1 becomes an input of inverter 2, and output F of inverter 3 becomes an input of inverter 4.

The output C of the inverter 2 is the input of the delay circuit 5 and the P channel transistors PL, P which are divided by dividing the gate width.
2. It becomes the gate input of P channel transistor P1 of P3. The source of the P-channel transistor P1 is connected to a power source, and the drain thereof is connected to an output terminal O. The output G of the inverter 4 is the input of the delay circuit 7 and N-channel transistors Nl, N2 . Of N3, this becomes the gate input of N-channel transistor N1. The source of N-channel transistor N1 is grounded,
The drain is connected to output terminal O.

The output of the delay circuit 5 becomes the input of the next stage delay circuit 6 and the gate input of the P-channel transistor array 2. The source of the P-channel transistor train 2 is connected to the power supply, and the train is connected to the output terminal O. In addition, the output is connected to the drain of the P-channel transistor 4 for pull-up.
The source of the P-channel transistor array 4 is connected to the power supply, and the output B is input to the gate. The output H of the delay circuit 7 becomes the input of the next stage delay circuit 8 and the gate input of the N-channel transistor N2. The source of N-channel transistor N2 is grounded and the train is connected to output terminal O. Further, the output H is connected to the drain of an N-channel transistor N4 for pull-down, the source of the N-channel transistor N4 is grounded, and the output F is input to the gate.

The output E of the delay circuit 6 becomes the gate input of the P-channel transistor array 3. The source of the P-channel transistor array 3 is connected to the power supply, and the drain is connected to the output terminal 0. In addition, the output E is a P-channel transistor P for pull-up.
P-channel transistor P
The source of No. 5 is connected to the power supply, and the output B is input to the gate. The output I of the delay circuit 8 becomes the gate input of the N-channel transistor N3, whose source is grounded and whose drain is connected to the output terminal O. Further, the output (2) is connected to a train of an N-channel transistor N5 for pull-down, the source of the N-channel transistor N5 is grounded, and the output F is input to the gate.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

When the input signal A changes from "0" to "1", the transistor N1 is turned on and the transistor P1 is turned off. The transistor N2 is turned on by the delay signal H from the signal G input to the transistor N1 through the delay circuit 7, and further, the input signal to the transistor N2 becomes a delay signal through the delay circuit 8, turning on the transistor N3. In addition, the pull-up transistor P4. Since P5 is turned on by signal B, transistors P1, P2, . P3
Is it delayed? The input signal that comes out via @5 and 6 turns off without waiting for E.

When the input signal A changes from "1" to '0', the transistor P1 is turned on and the transistor N1 is turned off.Then, the transistor P2 converts the signal C input to the transistor P1 into a delay signal after passing through the delay circuit 5. Further, the input signal of the transistor P2 becomes a delay signal that passes through the delay circuit 6 and turns on the transistor P3.Furthermore, since the pull-down transistors N4 and N5 are turned on by the signal F, the transistors P1, P2, and P3 are turned on by the signal F.
is turned off without waiting for input signals H and I to be output via delay circuits 7 and 8.

Although the embodiment in which the number of transistor divisions is three has been described above, the same effect can be obtained even if the number of divisions is other than three.

〔Effect of the invention〕

As explained above, the present invention divides the gate width of the P-channel transistor and the N-channel transistor,
By inputting a delay signal that has passed through a delay circuit sequentially to each divided gate, each transistor is not turned on at the same time, and the peak of the current flowing through each transistor is shifted, so that the charge flow when the transistor is turned on is reduced. It is possible to suppress fluctuations in the potentials of the power supply and ground caused by the current, and has the effect of preventing malfunction of internal circuits and deterioration of access time. Furthermore, when turning off a transistor, the gates of the divided transistors are simultaneously turned high or low using a pull-up or pull-down transistor to turn off the transistors, which has the effect of preventing through current and quickly reversing the output.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an example of a conventional output buffer circuit. 1.2, 3.4... Inverter, 5, 6, 7.8...
・Delay circuit, PL, P2. P3. P4. P5...P channel transistor, Nl, N2. N3°N4. N5
...N-channel transistor.

Claims (1)

[Claims] a P-channel transistor and an N-channel transistor whose gate widths are divided and whose drains are interconnected; a first delay circuit that sequentially delays a common input signal to each of the divided gates of the P-channel transistor; a second delay circuit that sequentially delays a common input signal to each of the divided gates of the channel transistor; a P-channel transistor that pulls up the signal output from the first delay circuit; and the second delay circuit. An output buffer circuit comprising an N-channel transistor that pulls down a signal output by the circuit.