JPH02125522A - Input buffer circuit - Google Patents

Input buffer circuit

Info

Publication number
JPH02125522A
JPH02125522A JP63279749A JP27974988A JPH02125522A JP H02125522 A JPH02125522 A JP H02125522A JP 63279749 A JP63279749 A JP 63279749A JP 27974988 A JP27974988 A JP 27974988A JP H02125522 A JPH02125522 A JP H02125522A
Authority
JP
Japan
Prior art keywords
node
gate
output
logic gate
external signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63279749A
Other languages
Japanese (ja)
Inventor
Naohiko Sugibayashi
直彦 杉林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63279749A priority Critical patent/JPH02125522A/en
Publication of JPH02125522A publication Critical patent/JPH02125522A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01Modifications for accelerating switching
    • H03K19/017Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01707Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
    • H03K19/01721Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To quicken the operation assisting the operation of the 1st stage CMOS logic gate by connecting two MOS transistors(TRs) whose gates receives an output of a CMOS logic gate of the 2nd and succeeding stages or its inverted output and an external signal in series between the 1st logic gate output and a ground terminal or a power terminal. CONSTITUTION:An output node N3 of the 3rd stage CMOS logic gate G3 is connected to a gate of an N-channel TR Q2 and an external signal AD is connected to a gate of an N-channel TR Q1. The two TRs Q1, Q2 are connected in series and the source of the TR Q1 is connected to a node N1 and the source of the TR Q2 is connected to ground. When the external signal AD changes from a low to a high level, the TRs Q1, Q2 are turned on and the node N1 is extracted through two buses and changes quickly to a low level, the node N2 goes to a high level and the node N3 goes to a low level and then the TR Q2 is turned off. Thus, the TRs Q1, Q2 are acted.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はCMOS半導体集積回路に関し、特に外部信号
の入力バッフ1回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS semiconductor integrated circuit, and particularly to an input buffer 1 circuit for external signals.

〔従来の技術〕[Conventional technology]

第4図はこの種の入力バッファ回路の従来例の回路図で
ある。△Dは外部信号入力である。ALは、外部信号入
力バッファを“Hi gh ”でイネーブル状態とし、
“LOW ”で入力データをラッチする信号である。破
線で囲まれたG+ 、G2・・・G6がそれぞれ0MO
8論理ゲートとなっており、0MO8論理ゲートを用い
た回路図を第3図に示ず。
FIG. 4 is a circuit diagram of a conventional example of this type of input buffer circuit. ΔD is an external signal input. AL enables the external signal input buffer at “High”,
This is a signal that latches input data at "LOW". G+, G2...G6 surrounded by broken lines are each 0 MO
There are 8 logic gates, and a circuit diagram using 0MO8 logic gates is not shown in FIG.

YAは外部fThq人カバツカバッファである。YA is an external fThq buffer.

一般に、CMOS半導体集積回路はT 1−1−レベル
の入力電圧を保πFしている。これは”tliOh”が
2.4 V、  ”Low ”が0.8Vである。しか
1ノながら、CMOS半導体集積回路の内部では”ll
igh”は電源゛電圧、゛シO膚″はOvである。仙作
保iil:側トよ1h通4.5V〜5.5vであるので
電源電圧5■とすると、トランジスタυイズ当りの初段
0MO3論理ゲートの電流能力は内部に比べてNチャン
ネルトランジスタではしきい値電圧VTN・・0.8V
のとき(2,4−0,8> 2 / (5,0−0,8
> 2 =0.15倍となる。また、Pチャンネルトラ
ンジスタでは同様にV TP = 0.8 Vのとき(
5,(1−0,8−0,8”) 2 / (5,0−0
,8) 2・・0.66倍となる。
Generally, a CMOS semiconductor integrated circuit maintains an input voltage of T1-1- level. This means that "tliOh" is 2.4 V and "Low" is 0.8 V. However, inside a CMOS semiconductor integrated circuit,
"high" is the power supply voltage, and "voltage" is Ov. Sensaku Yasushi: Since the voltage on the side is 4.5V to 5.5V for 1 hour, if the power supply voltage is 5■, the current capacity of the first stage 0 MO3 logic gate per transistor υ size is the threshold for an N-channel transistor compared to the internal one. Value voltage VTN...0.8V
When (2,4-0,8>2/(5,0-0,8
> 2 = 0.15 times. Similarly, for a P-channel transistor, when V TP = 0.8 V (
5, (1-0,8-0,8") 2 / (5,0-0
,8) 2...0.66 times.

このように初段0MO8論理ゲートは電流能力がないた
めに入クツ信号ADを反転させた場合、初段ゲートG1
の出力N1は他の内部節点よりゆっくりと反転すること
になる。0MO3論理ゲートは反転中にNチャンネルト
ランジスタもPチャンネルトランジスタもオンするため
電源から接地へ貫通電流が流れる。この場合、節点N1
がゆっくり反転することによりゲートG2が電流を流す
。このため入力バッファ回路付近の接地の電位が浮き上
がる。入力信号へ〇を“Low″から゛′旧gh“に変
えたときに以上のようなことが起ると、初段ゲートG1
のNチャンネルトランジスタのソース・ドレイン間の電
圧が接地電位の上昇により減少するためNチャンネルト
ランジスタの電流能ツノは減る。そのため、節点N1の
反転速度はいよいよ遅くなりゲートG2は′:Pi流を
流しつづけ、またそれによって節点N1の反転が遅くな
るという相乗効果によって入力バッファの動作がおくれ
、入力信号ALによってラッチする時制に節点N2が反
転しておらず誤動作してしまう。これに対して初段のト
ランジスタサイズを大きくして対策しようとすると、ゲ
ート容ルも大きくなり容量による遅れが生じ、効果的な
対策とはなっていなかった。
In this way, the first-stage 0MO8 logic gate does not have current capability, so when the input signal AD is inverted, the first-stage gate G1
The output N1 of will invert more slowly than other internal nodes. Since the 0MO3 logic gate turns on both the N-channel transistor and the P-channel transistor during inversion, a through current flows from the power supply to the ground. In this case, node N1
is slowly reversed, causing the gate G2 to conduct current. Therefore, the ground potential near the input buffer circuit rises. If the above happens when the input signal 〇 is changed from “Low” to “old gh”, the first stage gate G1
Since the voltage between the source and drain of the N-channel transistor decreases due to the rise in ground potential, the current capability of the N-channel transistor decreases. Therefore, the inversion speed of the node N1 becomes slower and the gate G2 continues to pass the ':Pi current, and the operation of the input buffer is delayed due to the synergistic effect of slowing down the inversion of the node N1. Since the node N2 is not inverted, a malfunction occurs. If an attempt was made to counter this by increasing the size of the first-stage transistor, the gate capacitance would also increase, causing a delay due to the capacitance, and this was not an effective countermeasure.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の入力バッファ回路は、動作しはじめると
同時に発生する貫通電流によって接地電位が浮き上がる
ため、トランジスタ能力の小さい初段0MO8論理ゲー
ト・の動作がおくれるという欠点がある。
The conventional input buffer circuit described above has the disadvantage that the ground potential rises due to the through current generated at the same time as the input buffer circuit starts to operate, so that the operation of the first-stage 0MO8 logic gate, which has a small transistor capacity, is delayed.

〔課題を解決するための手段) 本発明の入力バッファ回路は、初段論理ゲート出りと接
地端子または電源端子の間に、接地9=;子の場合には
2つのNチャンネルMOSトランジスタが、電源端子の
場合には2つのPチャンネルMOSトランジスタが互い
に直列に接続され、それらトランジスタはそれぞれ2段
目以降の0MO8論理ゲート出力またはその反転出力と
外部信号をゲート入力とすることを特徴とする。
[Means for Solving the Problems] In the input buffer circuit of the present invention, two N-channel MOS transistors are connected between the output of the first stage logic gate and the ground terminal or the power supply terminal. In the case of a terminal, two P-channel MOS transistors are connected in series, and each of these transistors is characterized in that the output of the 0MO8 logic gate from the second stage or later or its inverted output and an external signal are input to the gate.

〔作用〕[Effect]

これら両トランジスタは、外部信号が” Low ”か
ら“旧gh”に変わったとき(NチャンネルMOSトラ
ンジスタの場合)、外部信号が“High”から’Lo
w”に変わったとき(PチャンネルMOSトランジスタ
の場合)オンし、初段の論理ゲートの出力がすばやくそ
れぞれLow”、′旧oh”になる。
Both of these transistors change the external signal from "High" to "Low" when the external signal changes from "Low" to "old GH" (in the case of N-channel MOS transistors).
When the voltage changes to "W" (in the case of a P-channel MOS transistor), it turns on, and the outputs of the first-stage logic gates quickly become Low" and 'old oh', respectively.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の入力バッフ7回路の一実施例の回路図
で、ある。
FIG. 1 is a circuit diagram of one embodiment of the seven input buffer circuits of the present invention.

3段目の0MO8論理ゲートG3の出力節点N3がNチ
ャンネルトランジスタQ2のゲートに接続され、外部信
MADがNチャンネルトランジスタQ1のゲートに接1
1されている。そしてこれら2つのトランジスタQ1.
Q2は直列に接続され、トランジスタQ1のソースは節
点N1に接続され、トランジスタQ2のソースは接地さ
れている。今、外部信号ADがtow ”から゛″旧9
h″に変わったとする。このときトランジスタQ1はオ
ンする。また、節点N3も゛旧gh”であるため、トラ
ンジスタQ2がオンする。1ノたがって、節点N1は2
つのパスで引きぬかれることになり、節点N1はすばや
くLow ”になる。節点N1 が” Low ”にな
ると節点N2が”lligh” 、節点N3が°“+、
ow ”となり、トランジスタQ2がオフする。
The output node N3 of the third-stage 0MO8 logic gate G3 is connected to the gate of the N-channel transistor Q2, and the external signal MAD is connected to the gate of the N-channel transistor Q1.
1 has been done. And these two transistors Q1.
Q2 are connected in series, the source of transistor Q1 is connected to node N1, and the source of transistor Q2 is grounded. Now, the external signal AD is changing from “tow” to “old 9”.
In this case, the transistor Q1 is turned on. Since the node N3 is also "old gh", the transistor Q2 is turned on. Therefore, node N1 is 2
As a result, the node N1 quickly becomes ``Low''. When the node N1 becomes ``Low'', the node N2 becomes ``lligh'', the node N3 becomes ``+'',
ow” and the transistor Q2 is turned off.

そのため、このあと外部信号ADをIf i g h 
”から”tow”にするとぎには、この直列接続のトラ
ンジスタQ1.Q2は影響を及ぼさない。したがって、
外部信号へ〇がLow ’“から“’1Iic+h”に
変化するときにのみ、トランジスタ0+ 、Q2が働く
ことになる。
Therefore, after this, if the external signal AD is
When changing from "to" to "tow", these series-connected transistors Q1 and Q2 have no effect. Therefore,
Transistors 0+ and Q2 will work only when the external signal 〇 changes from ``Low'' to ``1Iic+h''.

第2図は本発明の入力バッフ7回路の第2の実施例の回
路図である。
FIG. 2 is a circuit diagram of a second embodiment of the input buffer 7 circuit of the present invention.

PチャンネルトランジスタQ3 、Q、iは、第1の実
施例のNヂ!・ンネルトランジスタQ+ 、Q2とは逆
に外部信号ADが’Iligh”から’Low”のとぎ
のみ働く。
P-channel transistors Q3, Q, i are the same as Nji! of the first embodiment.・Contrary to the channel transistors Q+ and Q2, they work only when the external signal AD changes from 'Ilight' to 'Low'.

ゲートG2が貫通電流を流したとき、接地電位のうさ上
りより電源電位のしずみの方が影響が犬きい場合有効で
ある。
This is effective if, when a through current flows through the gate G2, a drop in the power supply potential has a stronger effect than a rise in the ground potential.

なお、第1の実施例と第2の実施例を組合せて行なうこ
とも可能であり、接地電位のうぎ上りにも電、I!電位
のしずみにb有効である。
It should be noted that it is also possible to carry out a combination of the first embodiment and the second embodiment, and even when the ground potential rises, it is possible to carry out an electric current, I! It is effective for reducing the potential.

(発明の効果) 以上説明したように本発明は、初段論理ゲート出力と1
8地端子または電源Qさ子の間に、2段目以時の0MO
8論理ゲート出力またはその反転出力と外部信届をゲー
ト入力す52′つのM OS l゛−ランジスタを直列
接続することにより、入カバツア回路が+)+作しはじ
めて貫通電流が流れ、それによってノイズを発生し、そ
のノイズによって動作がおくれだ場合、直列の2つの1
〜ランジスタが初段0MO5論理ゲートの動作を助ける
動作を速める効果がある。
(Effects of the Invention) As explained above, the present invention provides the first stage logic gate output and the first stage logic gate output.
8 Ground terminal or between the power supply Q and 0 MO from the second stage onwards
By connecting in series 52' MOS transistors that input 8 logic gate outputs or their inverted outputs and external signals to the gates, the input cover circuit starts to operate and a through current flows, which causes noise. occurs, and if the operation is delayed due to the noise, two 1s in series
~The transistor has the effect of speeding up the operation of the first stage 0MO5 logic gate.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はてれぞれ本発明の第1.第2の実施例
の回路図、第3図、第4図は従来例の回路図である1゜ G+   G2.G8・・・CMOSNORゲート、G
3 、Ga 、Gb・・・CMOSインバータ、N+ 
、N2 、N3・・・接点、 Ql、G2・・・NチャンネルMO3)−ランジスタ、
△D・・・外部信舅、 AL・・・外部信呂人カイネーブル信号、Y△・・・入
カバッフ7回路出力。 第 図 第 図
FIGS. 1 and 2 respectively show the first embodiment of the present invention. The circuit diagram of the second embodiment, FIGS. 3 and 4, are the circuit diagrams of the conventional example, 1°G+G2. G8...CMOSNOR gate, G
3, Ga, Gb...CMOS inverter, N+
, N2, N3... Contact, Ql, G2... N-channel MO3) - transistor,
△D...External signal input, AL...External signal enable signal, Y△...7 input buffer circuit output. Figure Figure

Claims (1)

【特許請求の範囲】 1、CMOS半導体集積回路の外部信号の入力バッファ
回路において、 初段論理ゲート出力と接地端子または電源端子の間に、
接地端子の場合には2つのNチャンネルMOSトランジ
スタが、電源端子の場合には2つのPチャンネルMOS
トランジスタが互いに直列に接続され、それらトランジ
スタはそれぞれ2段目以降のCMOS論理ゲート出力ま
たは反転出力と外部信号をゲート入力とすることを特徴
とする入力バッファ回路。
[Claims] 1. In the external signal input buffer circuit of a CMOS semiconductor integrated circuit, between the first stage logic gate output and the ground terminal or power supply terminal,
Two N-channel MOS transistors in case of ground terminal, two P-channel MOS transistors in case of power terminal
An input buffer circuit characterized in that transistors are connected in series with each other, and each of these transistors receives an output or inverted output of a CMOS logic gate from a second stage or later and an external signal as a gate input.
JP63279749A 1988-11-04 1988-11-04 Input buffer circuit Pending JPH02125522A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63279749A JPH02125522A (en) 1988-11-04 1988-11-04 Input buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63279749A JPH02125522A (en) 1988-11-04 1988-11-04 Input buffer circuit

Publications (1)

Publication Number Publication Date
JPH02125522A true JPH02125522A (en) 1990-05-14

Family

ID=17615371

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63279749A Pending JPH02125522A (en) 1988-11-04 1988-11-04 Input buffer circuit

Country Status (1)

Country Link
JP (1) JPH02125522A (en)

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