JPH02125522A - Input buffer circuit - Google Patents

Abstract

PURPOSE:To quicken the operation assisting the operation of the 1st stage CMOS logic gate by connecting two MOS transistors(TRs) whose gates receives an output of a CMOS logic gate of the 2nd and succeeding stages or its inverted output and an external signal in series between the 1st logic gate output and a ground terminal or a power terminal. CONSTITUTION:An output node N3 of the 3rd stage CMOS logic gate G3 is connected to a gate of an N-channel TR Q2 and an external signal AD is connected to a gate of an N-channel TR Q1. The two TRs Q1, Q2 are connected in series and the source of the TR Q1 is connected to a node N1 and the source of the TR Q2 is connected to ground. When the external signal AD changes from a low to a high level, the TRs Q1, Q2 are turned on and the node N1 is extracted through two buses and changes quickly to a low level, the node N2 goes to a high level and the node N3 goes to a low level and then the TR Q2 is turned off. Thus, the TRs Q1, Q2 are acted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS semiconductor integrated circuit, and particularly to an input buffer 1 circuit for external signals.

[Conventional technology]

FIG. 4 is a circuit diagram of a conventional example of this type of input buffer circuit. ΔD is an external signal input. AL enables the external signal input buffer at “High”,
This is a signal that latches input data at "LOW". G+, G2...G6 surrounded by broken lines are each 0 MO
There are 8 logic gates, and a circuit diagram using 0MO8 logic gates is not shown in FIG.

YA is an external fThq buffer.

Generally, a CMOS semiconductor integrated circuit maintains an input voltage of T1-1- level. This means that "tliOh" is 2.4 V and "Low" is 0.8 V. However, inside a CMOS semiconductor integrated circuit,
"high" is the power supply voltage, and "voltage" is Ov. Sensaku Yasushi: Since the voltage on the side is 4.5V to 5.5V for 1 hour, if the power supply voltage is 5■, the current capacity of the first stage 0 MO3 logic gate per transistor υ size is the threshold for an N-channel transistor compared to the internal one. Value voltage VTN...0.8V
When (2,4-0,8>2/(5,0-0,8
> 2 = 0.15 times. Similarly, for a P-channel transistor, when V TP = 0.8 V (
5, (1-0,8-0,8") 2 / (5,0-0
,8) 2...0.66 times.

In this way, the first-stage 0MO8 logic gate does not have current capability, so when the input signal AD is inverted, the first-stage gate G1
The output N1 of will invert more slowly than other internal nodes. Since the 0MO3 logic gate turns on both the N-channel transistor and the P-channel transistor during inversion, a through current flows from the power supply to the ground. In this case, node N1
is slowly reversed, causing the gate G2 to conduct current. Therefore, the ground potential near the input buffer circuit rises. If the above happens when the input signal 〇 is changed from “Low” to “old gh”, the first stage gate G1
Since the voltage between the source and drain of the N-channel transistor decreases due to the rise in ground potential, the current capability of the N-channel transistor decreases. Therefore, the inversion speed of the node N1 becomes slower and the gate G2 continues to pass the ':Pi current, and the operation of the input buffer is delayed due to the synergistic effect of slowing down the inversion of the node N1. Since the node N2 is not inverted, a malfunction occurs. If an attempt was made to counter this by increasing the size of the first-stage transistor, the gate capacitance would also increase, causing a delay due to the capacitance, and this was not an effective countermeasure.

[Problem to be solved by the invention]

The conventional input buffer circuit described above has the disadvantage that the ground potential rises due to the through current generated at the same time as the input buffer circuit starts to operate, so that the operation of the first-stage 0MO8 logic gate, which has a small transistor capacity, is delayed.

[Means for Solving the Problems] In the input buffer circuit of the present invention, two N-channel MOS transistors are connected between the output of the first stage logic gate and the ground terminal or the power supply terminal. In the case of a terminal, two P-channel MOS transistors are connected in series, and each of these transistors is characterized in that the output of the 0MO8 logic gate from the second stage or later or its inverted output and an external signal are input to the gate.

[Effect]

Both of these transistors change the external signal from "High" to "Low" when the external signal changes from "Low" to "old GH" (in the case of N-channel MOS transistors).
When the voltage changes to "W" (in the case of a P-channel MOS transistor), it turns on, and the outputs of the first-stage logic gates quickly become Low" and 'old oh', respectively.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of one embodiment of the seven input buffer circuits of the present invention.

The output node N3 of the third-stage 0MO8 logic gate G3 is connected to the gate of the N-channel transistor Q2, and the external signal MAD is connected to the gate of the N-channel transistor Q1.
1 has been done. And these two transistors Q1.
Q2 are connected in series, the source of transistor Q1 is connected to node N1, and the source of transistor Q2 is grounded. Now, the external signal AD is changing from “tow” to “old 9”.
In this case, the transistor Q1 is turned on. Since the node N3 is also "old gh", the transistor Q2 is turned on. Therefore, node N1 is 2
As a result, the node N1 quickly becomes ``Low''. When the node N1 becomes ``Low'', the node N2 becomes ``lligh'', the node N3 becomes ``+'',
ow” and the transistor Q2 is turned off.

Therefore, after this, if the external signal AD is
When changing from "to" to "tow", these series-connected transistors Q1 and Q2 have no effect. Therefore,
Transistors 0+ and Q2 will work only when the external signal 〇 changes from ``Low'' to ``1Iic+h''.

FIG. 2 is a circuit diagram of a second embodiment of the input buffer 7 circuit of the present invention.

P-channel transistors Q3, Q, i are the same as Nji! of the first embodiment.・Contrary to the channel transistors Q+ and Q2, they work only when the external signal AD changes from 'Ilight' to 'Low'.

This is effective if, when a through current flows through the gate G2, a drop in the power supply potential has a stronger effect than a rise in the ground potential.

It should be noted that it is also possible to carry out a combination of the first embodiment and the second embodiment, and even when the ground potential rises, it is possible to carry out an electric current, I! It is effective for reducing the potential.

(Effects of the Invention) As explained above, the present invention provides the first stage logic gate output and the first stage logic gate output.
8 Ground terminal or between the power supply Q and 0 MO from the second stage onwards
By connecting in series 52' MOS transistors that input 8 logic gate outputs or their inverted outputs and external signals to the gates, the input cover circuit starts to operate and a through current flows, which causes noise. occurs, and if the operation is delayed due to the noise, two 1s in series
~The transistor has the effect of speeding up the operation of the first stage 0MO5 logic gate.

[Brief explanation of the drawing]

FIGS. 1 and 2 respectively show the first embodiment of the present invention. The circuit diagram of the second embodiment, FIGS. 3 and 4, are the circuit diagrams of the conventional example, 1°G+G2. G8...CMOSNOR gate, G
3, Ga, Gb...CMOS inverter, N+
, N2, N3... Contact, Ql, G2... N-channel MO3) - transistor,
△D...External signal input, AL...External signal enable signal, Y△...7 input buffer circuit output. Figure Figure

Claims (1)

[Claims] 1. In the external signal input buffer circuit of a CMOS semiconductor integrated circuit, between the first stage logic gate output and the ground terminal or power supply terminal,
Two N-channel MOS transistors in case of ground terminal, two P-channel MOS transistors in case of power terminal
An input buffer circuit characterized in that transistors are connected in series with each other, and each of these transistors receives an output or inverted output of a CMOS logic gate from a second stage or later and an external signal as a gate input.