JPH0358260A - Controller - Google Patents

Abstract

PURPOSE:To use another controller when the fault, etc., of a processor is generated by resetting a counter circuit, which outputs a carry out signal, and makes a busy signal inactive after the lapse of prescribed time, once within prescribed time by a control program. CONSTITUTION:A reset instructing means is operated to output one reset instruction at least from a processor 54 within the prescribed time based on the control program stored in a memory 51. Further, a counter circuit 56 is operated to receive the reset instruction, to repeat one time of reset at least within the prescribed time, to output the carry out signal to a busy signal generating circuit 57 at the time of carrying over after the lapse of the prescribed time when the reset instruction is interrupted at the time of generating a fault, and to turn the busy signal to an inactive state. Thus, when the busy signal BSY is set in the inactive state and the fault of the processor or the run-away of the control program is generated, the busy signal BSY is made inactive and the occupation of an interface bus is canceled. Then, the other controller can be used.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to computer peripheral equipment, such as SCSI devices connected to small computer system interfaces (hereinafter referred to as SCSI), and particularly to execution of peripheral equipment operations. This is related to the controller that performs the following.

(Conventional technology) Since then, as technology in this field, the Japanese Standards Association Japanese translation ANSI X3.131 (1986)
computer system interface)
J.P. There were items described in 15=36. below,
The structure will be explained using figures.

FIG. 2 is a configuration block diagram showing an example of the configuration of the SCS'I system.

This SCSI system includes host adapters 12 to 14 and controllers 15 to 19, which are SCSI devices,
Those host adapters 12 to 14 and controller 1
5 to 19 are interconnected via an interface bus 11. Further, computers 21 to 23 are connected to the host 1 adapters 12 to 14, respectively, and peripheral devices 3 such as printers are connected to the controllers 15 to 1, respectively.
1-1~31-”n.32 1-32-n.33-1
~33-n, 34-1~34-n. 35-1 to 35n are connected to each other.

Here, host adapters]-2 to 14 are devices (initiators) that instruct the operation of peripheral devices such as printers, etc.
The controllers 15 to 19 are devices (targets) that perform operations on the printer.

Next, the operation will be explained.

For example, host adapter 2, which is an initiator, acquires the right to use the interface bus 11 in order to issue an operation command, and selects, for example, one controller of the target. The selected controller 19 activates the busy signal BSY in order to respond that it has been selected.
A busy signal BSY is output to the host adapter 12 via the interface bus 11.

In this way, Busy No. 3 BSY is sometimes used for control to acquire usage of the interface bus 11, but is normally controlled by the controller l9, and is used to control the busy No. 3 BSY to indicate that the interface bus 1l is in use. This is the number. Therefore, the selected controller 19 keeps the busy signal BSY in the active state until it releases the interface bus 11.

With the busy signal BSY activated, the controller 19 controls the signal line of the interface bus 11 in accordance with the SCSI standard, receives commands from the host adapter 12 through a transmitting/receiving unit (not shown), and operates the printer, etc. Perform operations on peripheral devices. However, when the operation can be performed without occupying the interface bus 11 or when the operation is completed, the busy signal BSY and all interface bus signals are deactivated to free the interface bus for other SCSI devices. . When the interface bus is released, the acquisition of the right to use the interface bus is controlled again, and the above operation is repeated.

As mentioned above, the interface bus 11 has a plurality of S
CSI devices are connected and use the interface bus in a time-sharing manner. The time division is performed by control in each SCSI device, especially by controlling the busy signal BSY.

FIG. 3 is a block diagram showing a configuration example of the conventional controller 19 in FIG. 2. As shown in FIG.

This controller 19 includes a processor 19a, a memory 1
9b, an address decode 19c, and a busy signal generation circuit 19d. The processor 19a, memory 19b and address decode 19c are connected to the address bus 19.
The processor 19a, memory 19b, and busy signal generation circuit 19d are further connected to each other via a data bus 19f. The address decode 19c is connected to the busy signal generation circuit 19d.

In the busy signal generation circuit 19d, a register 19d-1 and a driver circuit 19d-2 are connected in cascade, and a pull-up termination resistor 19g is connected to the output side of the driver circuit 19d-2. 1]
．． is connected.

This controller 19 turns on the busy 1 word BSY by writing "1" in the register 19d-1 according to the instruction of the processor 19a, and conversely,
By writing 0++, the busy signal BSY is turned off and controlled.

(Problems to be Solved by the Invention) However, the controller with the above configuration has the following problems.

For example, controller ■9 is selected and the busy signal BS
If a failure of the processor 19a or a runaway of the control program occurs while Y is in the on state, not only will one controller become unusable, but the interface bus l1 will remain in use, so the interface bus l1 The problem was that it became impossible to use all the devices connected to the .

The present invention provides a controller that solves the problem of the prior art in that failure of one controller makes it impossible to use all the devices connected to the interface bus.

(Means for Solving the Problems) In order to solve the above problems, the present invention includes a memory storing a control program for controlling a peripheral unit, and a computer connected to the computer via an interface bus based on the control program. a processor that controls the interface with the peripheral device; and a processor that outputs a busy signal to the interface bus based on instructions from the processor;
The controller has a busy signal generation circuit that prohibits the use of the controller on the interface bus, and takes the following measures.

a reset command means for outputting a reset command from the processor at least once within a predetermined time based on the control program; and a reset setting function based on the reset 1i'ir command, after the predetermined time elapses. and a counter circuit that outputs a carry-out signal to the busy signal generation circuit and shifts the busy signal to an inactive state.

(Operation) According to the present invention, since the controller is configured as described above, the reset command means causes the processor to output at least one reset command within a predetermined time based on the control program stored in the memory. work like that. Further, the counter circuit receives the reset command and repeats the reset at least once within the predetermined time period;
If the reset command is cut off in the event of a failure, a carry-out signal is output to the busy signal generation circuit upon carryover after the predetermined time has elapsed, and the busy signal is inactivated.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a structural block diagram of a controller 1-roller showing an embodiment of the present invention.

This controller is used in place of the single controller shown in FIG. 2, and elements common to those in FIG. 2 are given the same reference numerals.

This controller has a memory 51 that stores a control program for controlling peripheral devices 35-1 to 35n such as printers, magnetic disks, and magnetic tapes. The memory 51 is connected to a processor 54 via an address bus 52 and a data bus 53, and an address decoder 55 is further connected to the processor 54 via an address bus 52. Also, address bus 5
2 and the data bus 53 are connected to the computers 2 - 23.
Internal circuits (not shown) such as a transmitting/receiving circuit for transmitting and receiving data between the terminal and the peripheral devices 35-1 to 35-n under the control of the processor 54 are connected.

Here, the processor 54 is equipped to control data transfer between the computers 21 to 23 and the peripheral devices 35-1 to 35-n via the interface bus based on the control program in the memory 51. The address decoder 55 is a circuit that decodes the address/code of the address bus 52 when the processor 54 exchanges data with an internal circuit (not shown) via the data bus 53 or outputs a control signal.

An output terminal Q1 for the reset signal S1 of the address decoder 55 is connected to a counter circuit 56. The counter circuit 56 has a reset terminal Rl. connected to the output terminal Q1 of the address decoder 55. Clock terminal W. for clock signal CL. Set the logic to “0'° and clock signal C.
A preset terminal LD is used to set the D period value when L rises, and an enable terminal EPF is used to stop the count. T. Output terminal RC for carryout signal Sg
0, and counter output terminals 1, I, J, and K. This counter circuit 56 is counted up by evening lock No. 13 CL, and according to the control program stored in the memory 51, the output terminal Q of the address decoder 55 is counted up.
This circuit resets the count when the reset signal S, which is the output of the output terminal RCO, becomes "0'°.A busy signal generation circuit 57 is connected to the output terminal RCO.

Here, a control program which is a reset command means for resetting the counter circuit 56 is stored in advance in the memory 5l. That is, the output terminal H of the counter circuit 56
Within a predetermined time when all K become ゛゜1'゛ and carry over, the reset signal S1 of ``O'゜ is sent to the counter circuit 5.
output to 6. The program structure incorporates at least one f7 interreset fir instruction in the number of program execution steps corresponding to the carryover time, for example.

The busy signal circuit generation circuit 57 includes a register 571 and a driver circuit 57-2. The register 57-1 is a circuit that controls the busy signal BSY by making the busy signal BSY active 1 (logic 0°) or inactive (logic 1). It has a reset terminal R2 to which the output terminal RCO is connected and a terminal S for the register set signal S2.The terminal S is connected to the output terminal Q2 of the address decoder 55.One of them is the register 57. The input signal 1 of -l is connected to the data bus 53 via the data signal S3, and the output signal 1 is connected to the input signal of the driver circuit 57-2 via the output signal S4.Driver circuit 57- 2 drives the output of register 57-1 to interface bus 11.
A terminal resistor 58 is connected to the output of the driver circuit 57-2 to pull up the busy signal BSY and achieve impedance matching with the interface bus 11. An interface bus 11 is connected. Note that this terminating resistor 58 is connected to the interface bus 11 by this controller.
Provided only when connected to the end of the terminal, otherwise unnecessary.

Next, FIG. 4 is a time chart of FIG. 2, and the operation of FIG. 1 will be explained with reference to this diagram.

(B) When activating the operation busy signal BSY before time t1, the processor 54 transmits address information for selecting the output terminal Q1 of the address decoder 55 to the address bus according to the control program stored in the memory 51 in advance. Output to 52.

(Expression) Operation at time tl-t2 Address decoder 55 decodes the address information and outputs reset signal S1 from output terminal Q1. As a result, the counter circuit 56 is initialized to "0'°, so that the output terminals H to K all change from "1" to "0'°.

Thereafter, the clock signal C1 input to the clock terminal W
-, the counter value is counted up by 1 each time the clock signal CI1 rises.

(c) Operation between times t2 and t3 The processor 54 holds the data signal S3 at "°1'°" via the data bus 53.
The output signal of the 2-hair address decoder 55 outputs address information for selecting the first child Q2. The A1-res decoder 55 is
The address information on the address bus 52 is decoded and the output terminal Q
A register set signal S2 of 2 to 0 is output.

(2) Operation from time t3 to t4 At time t3, the register set signal S2 changes from "O'" to "L", and the data signal S3, which was previously held at "1", is written to the register. At the same time, the output signal S4 of the register changes to "1'°, is invertedly driven in the driver circuit, and is outputted to the interface bus l1 in the form of an activated busy signal BSY of "0°'.

(PO) At operating times t4 and t5 from time t4 to t6, when the reset signal S1 of ゜“0゛゜ is output by the control 1 output program stored in the memory 51, the output terminal 1 of the counter circuit 56
The outputs of ~K all become "O°" and are reset.

Thereafter, the counter value is incremented by 1 each time the clock signal CL rises due to the crossword 1 word CL input again to the clock terminal W. Such operations are repeatedly executed when the programs in the processor 54 and memory 51 are operating normally. Eventually, when the operation of the peripheral device 35-1, 35-n is completed, ``0'' is written in the register by a command from the processor 54, and the busy signal BSY becomes the inactive state of It.sub.t++.

(F) Operation from time t6 to time t7 At time t6, if an abnormality occurs in the processor 54 or a failure such as a runaway program occurs, the counter circuit 56
It becomes impossible to execute the reset command for . Therefore,
The counter circuit 56 continues to count up. Subsequently, at time 7, the counter circuit 56 enters carryover and changes the carryout signal Sg from ゜゛1゜゜ to "O". As a result, the output signal S4 of the register changes from ゜゛1゛゜ to ``゜0''.Therefore, the busy signal BSY becomes an inactive state of ゛゜1゛'.

This embodiment has the following advantages.

(1) A counter circuit 56 is provided which outputs a carryout signal Sg to deactivate the bus 1/1 word BSY when a predetermined time has elapsed, and the counter circuit 56 is controlled by a control program within the predetermined time. Since the reset is performed periodically, when the busy signal BSY is activated and the processor 54 malfunctions or the control program goes out of control, the processor 54 and the control program will not function properly. The counter circuit 56 cannot be reset within the predetermined time. As a result, the count circuit 56 continues to count up, and finally carries over and outputs the carry-out signal Sg. This makes it possible to deactivate the busy signal BSY,
Eliminate the problem of interface bus 11 and connect the pond controller 1
・Rollers can be made usable.

(2) Since the counter circuit 56 is used as a means to automatically deactivate the busy signal BSY after a predetermined time after a failure occurs, the circuit structure is simpler than, for example, using a delay means of a CR integration circuit. Moreover, the busy signal BS is accurate.
Y can be deactivated.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following variations.

(I> In the above embodiment, an up counter is used for the counter circuit 56, but a down counter or an up/'
An up/down counter for down switching may be used.

(n) In the above embodiment, the control program stored in the memory 51 includes:
The reset signal S1 of “0” is output, and the counter circuit 5
117 grams to reset 6 are stored in advance. Although the program structure is such that at least one counter reset instruction is included in the number of execution steps of the program corresponding to the carryover time, it is also possible to use other programs.

(Effects of the Invention) As described in detail above, in the present invention, a counter circuit is provided which outputs a carry-out signal and deactivates a busy signal when a predetermined time has elapsed, and the counter circuit is controlled by a control program as described above. Since it is reset at least once within a predetermined time, when the busy signal is in the active 1 state and a processor failure or control program runaway occurs, a carryout 1 word is output and the system is automatically reset. The busy signal can be deactivated to enable use of other controllers.

Furthermore, since a counter circuit is used as a means to deactivate the busy signal in the event of a failure, the circuit layout is simpler than, for example, using a delay means of a CR integration circuit, and moreover, the busy signal can be deactivated accurately. can be converted into

[Brief explanation of drawings]

Figure 1 (2) is a configuration diagram of a controller showing an embodiment of the present invention, Figure 2 is a configuration diagram of a SCSI system, Figure 3 is a configuration diagram of a conventional controller 1 to rollers, and Figure 4 is Figure 1. This is a time chart. 11... Interface bus, 1.5, 16
17,18.19... Controller, 31-■
〜31-n32-1〜32-n. 33-1 to 33-n,
34-1~34 n, 35 1~35-n...
・Peripheral equipment, 21, 22. 23...Computer, 51...Memory, 54...Processor, 56...Counter reading, 57...・・・
・Busy signal generation circuit, S1...Reset signal, Sg...Carryout signal, BSY...
...Busy signal.

Claims (1)

[Scope of Claims] A memory storing a control program for controlling a peripheral device, and controlling for functional connection between a computer and the peripheral device via an interface bus based on the control program. A controller comprising a processor and a busy signal generation circuit that outputs a busy signal to the interface bus based on instructions from the processor and prohibits use of other controllers on the interface bus, the controller being configured with the control program and configured to operate within a predetermined time. a reset command means for causing the processor to output at least one reset command; and a reset function for resetting based on the reset command, and outputting a carryout signal to the busy signal generation circuit after the predetermined time has elapsed. and a counter circuit for inactivating the busy signal.