CN114691386A

CN114691386A - Event trigger main control terminal, control chip and control method

Info

Publication number: CN114691386A
Application number: CN202111549803.9A
Authority: CN
Inventors: 林宗民
Original assignee: Nuvoton Technology Corp
Current assignee: Nuvoton Technology Corp
Priority date: 2020-12-31
Filing date: 2021-12-17
Publication date: 2022-07-01
Also published as: TW202227984A; TWI811606B

Abstract

An event trigger main control end, a control chip and a control method are provided, wherein the event trigger main control end comprises: the system comprises an event receiving interface, a memory device, a state machine and a main control interface. The event receiving interface is used for receiving an event request. The memory device has a command queue for storing at least one set command. When the event request is triggered, the state machine executes the setting instruction to access a first peripheral device or a second peripheral device. The main control interface is coupled between the state machine and the peripheral device. The state machine accesses the first or second peripheral device through the master control interface.

Description

Event trigger main control end, control chip and control method

Technical Field

The present invention relates to an event trigger host, and more particularly, to an event trigger host coupled between a processor and a peripheral device.

Background

With the advancement of technology, the types and functions of electronic devices are increasing. The electronic device has a plurality of control chips therein. The control chip typically has a processor therein. The processor is used as the heart of the control chip and is responsible for controlling all devices in the chip.

For example, the processor may trigger a first specific circuit to command the first specific circuit to perform a predetermined operation. A processor may read and execute a code while a first particular circuit performs a predetermined operation. After the preset operation is completed, the first specific circuit sends out an event notice. Therefore, the processor suspends the execution of the code and triggers a second specific circuit according to the event notification sent by the first specific circuit. The processor resumes executing the code while the second particular circuit performs the corresponding default operation. After the second specific circuit completes the preset operation, the second specific circuit sends out an event notice. Therefore, the processor suspends the execution of the code again and acts according to the interrupt signal sent by the second specific circuit. The performance of the processor is reduced because the operation of the processor is interrupted multiple times.

Disclosure of Invention

An embodiment of the present invention provides an event triggered master control terminal, which includes an event receiving interface, a memory device, a state machine, and a master control interface. The event receiving interface is used for receiving an event request. The memory device has a command queue for storing a set command. When the event request is triggered, the state machine executes the setting instruction to access a first peripheral device or a second peripheral device. The main control interface is coupled with the state machine, the first peripheral device and the second peripheral device. The state machine accesses the first or second peripheral device through the master control interface.

The present invention further provides a control chip, which includes a first peripheral device, a second peripheral device, a peripheral system bus, and an event-triggered master. The peripheral system bus is coupled with the first and the second peripheral devices. The event trigger master control end is communicated with the first and second peripheral devices through a peripheral system bus and comprises an event receiving interface, a storage device, a state machine and a master control interface. The event receiving interface is used for receiving an event request. The memory device has a command queue for storing a set command. When the event request is triggered, the state machine executes a configuration instruction for accessing the first or second peripheral device. The master interface is coupled between the state machine and the peripheral system bus. The state machine accesses the first or second peripheral device through the master interface and the peripheral system bus.

Another embodiment of the present invention provides a control method for controlling a first peripheral device and a second peripheral device. The control method of the invention comprises storing a setting instruction and judging whether an event request is triggered. When the event request is triggered, a configuration instruction is executed to access the first or the second peripheral device. The setting instruction is provided by a processor. The setting instruction is executed by an event triggering the main control end. The event trigger main control end responds according to the triggered event request. The processor does not respond according to the event request that is triggered.

The control method of the present invention can be actually operated by the event-triggered main control terminal or the control chip of the present invention, which is hardware or firmware capable of executing specific functions, or can be recorded in a recording medium by means of codes and actually operated in combination with specific hardware. When the code is loaded into and executed by an electronic device, processor, computer, or machine, the electronic device, processor, computer, or machine becomes an event-triggered master or control chip for implementing the present invention.

In the embodiment of the invention, the event triggering main control end monitors whether the event request is triggered or not and responds when the event request is triggered. Thus, the processor does not need to respond to the event request. At this point, the processor may perform other operations without responding each time an event request occurs. Therefore, the efficiency of the processor is greatly improved.

Drawings

Fig. 1 is a schematic diagram of a control chip according to the present invention.

Fig. 2 is a schematic diagram of an event triggered master according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a possible control chip according to the present invention.

Fig. 4 is a schematic flow chart of a control method according to the present invention.

Reference numerals

100. 300, and (2) 300: control chip

102. 302: processor with a memory having a plurality of memory cells

104. 304: main system bus

106. 200, 306: event trigger main control terminal

108: peripheral circuit

110. 308: peripheral system bus

112: transmission interface

E1-EN: event request

PD _1 to PD _ 3: peripheral device

202: memory device

204: state machine

206: event receiving interface

208: master control interface

210: slave interface

QU _1 to QU _ N: instruction queue

CM1_1 to CM1_ X, CM2_1 to CM2_ Y, CMN _1 to CM2_ Z: setting instructions

CME: terminate instruction

310: time-meter

312: analog-to-digital converter

314: direct memory access controller

316: serial peripheral interface

And (3) AIN: analog signal

DOUT: output signal

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. The present description provides various examples to illustrate the technical features of various embodiments of the present invention. The configuration of each device in the embodiments is for illustration and not for limitation. In addition, the reference numerals in the embodiments are partially repeated to simplify the description, and do not indicate the relationship between the different embodiments.

FIG. 1 is a diagram of a control chip according to the present invention. As shown, the control chip 100 includes a processor (processor)102, a main system bus (main system bus)104, an event trigger master (event trigger master)106, and a peripheral circuit 108. Processor 102 is coupled to main system bus 104. In one possible embodiment, the processor 102 is a Central Processing Unit (CPU).

The event triggered master 106 is coupled to the peripheral circuit 108 and receives event requests E1-EN. When an event request is triggered, the event-triggered host 106 configures the peripheral circuit 108 to command the peripheral circuit 108 to perform a specific action. After completing a particular action, the peripheral circuit 108 may trigger one of the event requests E1-EN. At this time, the eventing master 106 performs a specific action, such as interrupting the processor 102, or resets the peripheral circuit 108 according to the triggered event request, so as to instruct the peripheral circuit 108 to perform another specific action. In the present embodiment, the event triggered host 106 serves as a host device for controlling the peripheral circuit 108. In this example, the peripheral circuit 108 acts as a slave.

In some embodiments, the event-triggered master 106 is coupled directly to the main system bus 104. In this example, the event triggers the master 106 to send an interrupt signal to the processor 102 via the main system bus 104. In addition, the processor 102 may send data to the eventing master 106 or receive data from the eventing master 106. At this time, the processor 102 acts as a master (master) and the event triggers the master 106 to act as a slave (slave). In this embodiment, the main system bus 104 provides a connection for the processor 102 to access the event-triggered master 106.

In other embodiments, the control chip 100 further includes a transmission interface 112. The transmission interface 112 is coupled between the main system bus 104 and the peripheral circuits 108. In this case, the processor 102 sends data to the peripheral circuit 108 or receives data from the peripheral circuit 108 through the transmission interface 112. In addition, the processor 102 can also send data to the eventing master 106 or receive data from the eventing master 106 through the transmission interface 112 and the peripheral circuit 108.

In one embodiment, the peripheral circuit 108 generates the event requests E1-EN and includes a peripheral system bus (peripheral system bus)110 and the peripheral devices PD _ 1-PD _ 3. The peripheral system bus 110 is coupled between the event trigger host 106 and the peripheral devices PD _1 to PD _ 3. In the present embodiment, the peripheral system bus 110 provides a connection so that the event triggered host 106 can perform an access operation, such as a set operation, on the peripheral devices PD _1 to PD _ 3.

For example, the event-triggered host 106 outputs control commands to the peripheral devices PD _1 to PD _3 or receives response data from the peripheral devices PD _1 to PD _3 via the peripheral system bus 110. In other embodiments, the processor 102 communicates with the event-triggered master 106 via the peripheral system bus 110, the transport interface 112, and the main system bus 104.

The peripheral devices PD _1 to PD _3 are coupled to the peripheral system bus 110 for receiving data from the peripheral system bus 110 or outputting data to the peripheral system bus 110. For convenience of illustration, FIG. 1 only shows the peripheral devices PD _1 to PD _3, but not for limiting the invention. In other embodiments, peripheral circuitry 108 has more or fewer peripheral devices.

In the present embodiment, the event requests E1 to EN are generated by the peripheral devices PD _1 to PD _ 3. The number of event requests generated by each peripheral device is not limited in the present invention. In one possible embodiment, each peripheral device generates a single event request. In this example, the number of event requests E1-EN is the same as the number of peripheral devices in the peripheral circuit 108.

In other embodiments, at least one of the peripheral devices PD _ 1-PD _3 generates a multiple-event request. In this case, the peripheral device triggers different event requests when the same peripheral device completes different specific actions. Taking the peripheral device PD _1 as an example, the peripheral device PD _1 triggers the event request E1 after the peripheral device PD _1 completes a first action (e.g., a timing operation). After the peripheral device PD _1 completes a second action (e.g., a counting operation), the peripheral device PD _1 triggers the event request E2. In some embodiments, the first and second actions may both be timed operations, but the execution time of the first action is different from the execution time of the second action. In this example, the first action is considered different from the second action. In other embodiments, at least one of the peripheral devices PD _1 to PD _3 generates a different number of event requests than another one of the peripheral devices PD _1 to PD _ 3.

The present invention does not limit the types of the peripheral devices PD _1 to PD _ 3. At least one of the peripheral devices PD _1 to PD _3 may be the same type as another one of the peripheral devices PD _1 to PD _ 3. In one possible embodiment, any one of the peripheral devices PD _ 1-PD _3 may be a Serial Peripheral Interface (SPI), a pulse-width modulation (PWM) circuit, an analog-to-digital converter (ADC), a Direct Memory Access (DMA) controller, a timer (timer) …, etc.

In the embodiment, the eventing master 106 knows whether the peripheral devices PD _1 to PD _3 complete the specific actions according to the event requests E1 to EN, and triggers any one of the peripheral devices PD _1 to PD _3 according to the setting data (not shown) stored in the eventing master after the specific actions are completed. Thus, the processor 102 is not interrupted multiple times. The processor 102 only needs to execute the corresponding operation after the event triggers the master 106 to issue an interrupt signal, so that the processor 102 has more time to perform other operations, thereby increasing the efficiency of the processor 102.

In other embodiments, the processor 102 is located in a first power region (not shown), and the event-triggered master 106 and the peripheral circuits 108 are located in a second power region (not shown). The first power supply region (power domain) and the second power supply region are independent of each other. Therefore, when the power of the first power supply area is reduced, even if the processor 102 enters the power saving mode and stops operating, the event-triggered host 106 and the peripheral circuit 108 can both operate normally as long as the power of the second power supply area is sufficient.

In other embodiments, the processor 102 is located in a first clock region (not shown), and the EVENT host 106 and the peripheral devices PD _ 1-PD _3 are located in a second clock region (not shown). The first clock domain and the second clock domain are independent of each other. Therefore, when the frequency of the clock signal in the first clock region decreases, even if the processor 102 enters the power saving mode and stops operating, the event-triggered master 106 and the peripheral circuit 108 can both operate normally as long as the frequency of the clock signal in the second clock region remains unchanged. In this case, the processor 102 may be located in the same power supply area as the event-triggered master 106 and the peripheral circuits 108.

Fig. 2 is a schematic diagram of an event triggered master according to an embodiment of the present invention. As shown, the EVEN master 200 includes a memory device 202, a state machine 204, an event receiving interface 206, and a master interface 208. Memory device 202 has instruction queues (queues) QU _ 1-QU _ N. The number of queues is not limited by the present invention. In one embodiment, the number of queues is the same as the number of event requests. In addition, the instruction queues QU _ 1-QU _ N may be stored in different blocks of the same memory. In other embodiments, the memory device 202 has different memories, each storing a corresponding queue.

In the present embodiment, each queue stores at least one setting instruction. As shown, the command queue QU _1 stores the set commands CM1_ 1-CM 1_ X. The instruction queue QU _2 stores setting instructions CM2_1 to CM2_ Y. The instruction queue QU _ N stores setting instructions CMN _1 to CM2_ Z. The number of setting instructions stored in the instruction queues QU _1 to QU _ N is not limited in the present invention. One of the instruction queues QU _ 1-QU _ N may store the same number of set instructions or may be different from the other of the instruction queues QU _ 1-QU _ N.

In some embodiments, each of the instruction queues QU _ 1-QU _ N further includes a termination instruction (end of command) CME. The termination instruction CME is located after the last set instruction of the instruction queues QU _1 to QU _ N. Using instruction queue QU _1 as an example, assume that set instructions CM1_ 1-CM 1_ X are arranged in sequence, where set instruction CM1_1 is the first set instruction and set instruction CM1_ X is the last set instruction. In this example, the termination instruction CME is located after the set instruction CM1_ X. In one embodiment, the termination instruction CME represents the end of the queue, which may have a value of 0xFFFF _ FFFF or 0x0000_ 0000.

The present invention does not limit the format of the setting instructions of the instruction queues QU _1 to QU _ N. Using the instruction queue QU _1 as an example, each of the set instructions CM1_ 1-CM 1_ X may have an address information (address) and a set information (data). In another embodiment, each set instruction in the instruction queue QU _1 further has a bit floor information (bit mask). In some embodiments, each set instruction of the instruction queue QU _1 may have a device identification code (ID code).

The state machine 204 is coupled to the memory device 202, the event receiving interface 206, and the master interface 208. The state machine 204 receives event requests E1-EN through the event reception interface 206. When an event request is triggered, the state machine 204 reads a corresponding queue (e.g., command queue QU _1) of the memory device 202 and executes the set commands (e.g., CM1_ 1-CM _ X) of the queue to provide at least one setting value to a corresponding peripheral device. In one embodiment, when the state machine 204 reads the termination CME instruction in the instruction queue QU _1, it indicates that all the set instructions in the queue have been executed. Thus, the state machine 204 triggers the corresponding peripheral device. At this time, the corresponding peripheral device operates according to the setting value provided by the state machine 204. After the peripheral device completes a specific action, the peripheral device triggers an event request, such that the state machine 204 reads a corresponding queue according to the triggered event request and executes a setting instruction in the queue.

The event receiving interface 206 is coupled between the state machine 204 and a peripheral circuit (e.g., 108) for receiving event requests E1-EN from the peripheral circuit and providing event requests E1-EN to the state machine 204. In one embodiment, the event receiving interface 206 has a plurality of pins (not shown) for receiving event requests E1-EN. In this example, the number of pins of the event receiver interface 206 is the same as the number of the event requests E1-EN.

The master interface 208 is coupled between the state machine 204 and a peripheral circuit. Taking FIG. 1 as an example, the host interface 208 is coupled to the peripheral system bus 110 of the peripheral circuit 108. In this example, the state machine 204 outputs the setting value to a corresponding peripheral device via the host interface 208 and the peripheral system bus 110. Thus, the host interface 208 provides a connection that allows the state machine 204 to perform configuration operations with multiple peripheral devices. For convenience of illustration, it is assumed that the state machine 204 communicates with the peripheral devices PD _1 PD _3 via the peripheral system bus 110.

In one embodiment, the set instructions in different queues are for different peripheral devices. For example, when the peripheral device PD _1 completes a first action, the peripheral device PD _1 triggers the event request E1. At this point, state machine 204 reads a corresponding instruction queue, such as QU _1, according to the triggered event request E1. In this example, the state machine 204 reads and executes the set commands CM1_ 1-CM 1_ X for writing data into the peripheral PD _2 until the termination command CME is read. When the state machine 204 reads the termination command CME, the command reaction to the event request E1 is completed. In this embodiment, the termination instruction CME represents the end of the queue.

After the peripheral device PD _2 completes a second action, the peripheral device PD _2 triggers the event request E2. Thus, state machine 204 reads a corresponding instruction queue, such as QU _ 2. In this example, the state machine 204 reads and executes the set commands CM2_ 1-CM 2_ Y for writing data into the peripheral PD _3 until the termination command CME of the command queue QU _2 is read. The termination instruction CME of the instruction queue QU _2 may be identical to the termination instruction CME of the instruction queue QU _ 1. In one embodiment, the peripheral device PD _3 triggers the event request EN after the peripheral device PD _3 completes the operation. Thus, the state machine 204 reads a corresponding instruction queue, such as QU _ N. In this example, after executing the set instructions CMN _ 1-CMN _ Z, the state machine 204 may issue an interrupt signal to a processor (102) via the host interface 208.

In other embodiments, the set instructions of different queues may be for the same peripheral device. In this case, the same peripheral device executes different actions according to the setting commands of different queues. For example, when the event request E1 is triggered, the state machine 204 reads the command queue QU _1 and executes the set commands CM1_ 1-CM 1_ X to write a plurality of data into the peripheral device PD _ 1. Then, the peripheral device PD _1 performs a first operation. After completing the first action, the peripheral device PD _1 may trigger the event request E2. At this time, the state machine 204 may read the command queue QU _2 and execute the set commands CM2_ 1-CM 2_ Y to write a plurality of data into the peripheral device PD _ 1. Then, the peripheral device PD _1 starts a second operation.

In other embodiments, different configuration commands for the same queue may be for different peripherals. Taking instruction queue QU _1 as an example, when event request E1 is triggered, the state machine reads instruction queue QU _ 1. In this example, the state machine 204 writes a first data message to the peripheral device PD _1 according to the device ID of the set command CM1_1, writes a second data message to the peripheral device PD _2 according to the device ID of the set command CM1_2, and writes a third data message to the peripheral device PD _3 according to the device ID of the set command CM1_ 3.

In some embodiments, the state machine 204 receives data from the processor 102 via the host interface 208 (e.g., set instructions CM1_ 1-CM 1_ X, CM2_ 1-CM 2_ Y, CMN _ 1-CMN _ Z and terminate instruction CME). In this example, the state machine 204 writes the setting commands CM1_1 to CM1_ X, CM2_1 to CM2_ Y, CMN _1 to CMN _ Z into the command queues QU _1 to QU _ N, respectively. In other embodiments, the eventing master 200 further comprises a slave interface 210. The slave interface 210 is coupled between the state machine 204 and the processor 102. In this example, the slave interface 210 is configured to receive the specific instructions CM1_ 1-CM 1_ X, CM2_ 1-CM 2_ Y, CMN _ 1-CMN _ Z and the termination instruction CME from the main system bus 104. The state machine 204 writes the designation instructions CM1_ 1-CM 1_ X, CM2_ 1-CM 2_ Y, CMN _ 1-CMN _ Z and the termination instruction CME into the memory device 202. The present invention does not limit the kind of the slave interface 210. In one embodiment, the slave interface 210 is the same type as the master interface 208.

FIG. 3 is a control diagram of a control chip according to one embodiment of the present invention. As shown, the control chip 300 includes a processor 302, a main system bus 304, an event-triggered host 306, a peripheral system bus 308, a timer 310, an analog-to-digital converter (ADC)312, a direct memory access controller (DMA)314, and a serial peripheral interface 316. The timer 310, the ADC 312, the DMA controller 314, and the serial peripheral interface 316 are peripheral devices.

In one possible embodiment, the processor 302, the EVM master 306, and the DMA 314 may each access a Static Random Access Memory (SRAM), an analog-to-digital converter 312, and a serial peripheral interface 316. In the present embodiment, the event trigger host 306 receives event requests E1-E4 generated by the timer 310, the ADC 312, the DMA 314 and the SPI 316.

When the timer 310 counts to a point in time, the timer 310 triggers the event signal E1. Therefore, the event triggers the host 306 to execute a setting command of a first queue (not shown) for setting the adc 312. In this example, the adc 312 samples an analog signal AIN. After sampling is complete, the analog-to-digital converter 312 triggers the event signal E2. At this time, the event triggers the host 306 to execute a second queue configuration command for configuring the DMA controller 314. After completing the setting, the dma controller 314 reads the sampling result of the adc 312 and writes the sampling result into the register of the spi 316. Upon completion of the operation, the direct memory access controller 314 triggers the event signal E3.

At this time, the event triggers the host 306 to execute a third queue configuration command for configuring the serial peripheral interface 316. In this example, the serial peripheral interface 316 takes the sampling result of the ADC 312 as an output data, and the output data is encoded in the output signal DOUT. When the serial peripheral interface 316 completes the output action, the serial peripheral interface 316 may trigger the event signal E4. In this example, the event triggers the host 306 to execute a set command of a fourth queue for issuing an interrupt signal to the processor 302. In other embodiments, when the serial peripheral interface 316 completes the output, the serial peripheral interface 316 directly issues an interrupt to the processor 302.

After receiving the interrupt signal, the processor 302 knows that a series of operations are completed, i.e. when the timer 310 counts a time point, the adc 312 samples the analog signal AIN and outputs the sampling result through the serial peripheral interface 316. In this embodiment, the processor 302 may perform other operations without monitoring whether each peripheral device has completed a specific operation, thereby improving the efficiency of the processor 302.

Fig. 4 is a schematic flow chart of a control method according to the present invention. The control method of the invention is used for controlling the multi-peripheral device. For convenience of description, the following description will be made by taking a first peripheral device and a second peripheral device as examples.

First, at least one setting command is stored (step S411). In this embodiment, the setting instruction is provided by a processor. In this case, the processor may write the set command to an event triggering the master via a main system bus. In other embodiments, the processor may write the configuration command to an event-triggered master via a main system bus and a peripheral system bus. In some embodiments, the processor further provides at least one termination command to the event triggered master. The present invention does not limit the format of the setting instruction. In one embodiment, the setting instruction may have an address information and a setting information. In another possible embodiment, the set instruction further has a bit of backplane information. In some embodiments, the set instruction may have a device identification code.

It is determined whether an event request is triggered (step S412). When the event request is not triggered, return to step S412. When the event request is triggered, a setting instruction is executed to set the first or second peripheral device (step S413). In one possible embodiment, the event trigger master detects whether the event request is triggered. In this case, the event triggered host has at least one queue for storing the setting command. When an event request is triggered, the event trigger master reads and executes the corresponding queue to set a corresponding peripheral device.

In this embodiment, the event trigger host monitors whether the event request is triggered, and responds when the event request is triggered. Thus, the processor does not need to respond to the event request. At this point, the processor may perform other operations without responding each time an event request occurs. Therefore, the efficiency of the processor is greatly improved.

The control methods of the present invention, or certain aspects or portions thereof, may exist in the form of codes. The code may be stored on a tangible medium such as a floppy disk, an optical disk, a hard disk, or any other machine-readable (e.g., computer-readable) storage medium, or may be embodied in a computer program product, wherein, when the code is loaded into and executed by a machine, such as a computer, the machine becomes an event-triggered master or control chip for participating in the present invention. The code may also be transmitted over some transmission medium, such as over electrical wiring or cabling, through fiber optics, or via any other form of transmission, wherein, when the code is received and loaded into and executed by a machine, such as a computer, the machine becomes an event-triggered master or control chip for use in conjunction with the present invention. When implemented in a general-purpose processing unit, the code combines with the processing unit to provide a unique apparatus that operates analogously to application specific logic circuits.

Unless otherwise defined, all terms (including technical and scientific terms) used herein are to be understood as commonly understood by one of ordinary skill in the art. Moreover, unless expressly stated otherwise, the definition of a term in a general dictionary shall be construed as being synonymous with the meaning in the context of the relevant art and shall not be construed as an idealized or overly formal definition. Although the terms "first," "second," etc. may be used to describe various devices, these devices should not be limited by these terms. These terms are only used to distinguish one device from another.

Although the present invention has been described with reference to the preferred embodiments, it is to be understood that the invention is not limited thereto, and that various changes and modifications may be made by those skilled in the art without departing from the spirit and scope of the invention. For example, the systems, devices, or methods described in connection with the embodiments disclosed herein may be implemented in hardware, software, or a combination of hardware and software. Therefore, the scope of the present invention is to be defined only by the terms of the appended claims.

Claims

1. An event-triggered master device, coupled to a first peripheral device, comprising:

an event receiving interface for receiving a first event request;

the memory device is provided with a first instruction queue and a second instruction queue, wherein the first instruction queue is used for storing a first setting instruction;

a state machine, when the first event request is triggered, the state machine executes the first setting instruction to access the first peripheral device or a second peripheral device; and

a host interface coupled to the state machine, the first peripheral device and the second peripheral device, wherein the state machine accesses the first peripheral device or the second peripheral device through the host interface.

2. The EVM master of claim 1, wherein the state machine receives the first SET command from a processor via the master interface and writes the first SET command into the memory device.

3. The event triggered master of claim 1, further comprising:

a slave interface coupled between the state machine and a processor;

the state machine receives the first setting command from the processor through the slave interface and writes the first setting command into the memory device.

4. The EVM master of claim 1, wherein the memory device further comprises:

a second instruction queue for storing a second set instruction.

5. The EVM master of claim 4, wherein the state machine executes the first configuration command to access the first peripheral device when the first event request is triggered, and executes the second configuration command to access the second peripheral device when a second event request is triggered.

6. The EVM master as claimed in claim 4, wherein the state machine executes the first configuration command to access the first peripheral device and command the first peripheral device to perform a first action when the first event request is triggered, and executes the second configuration command to access the first peripheral device and command the first peripheral device to perform a second action when a second event request is triggered.

7. The event-triggered host computer according to claim 6, wherein the first command queue has a plurality of first setting commands and a first terminating command, when the first event request is triggered, the state machine reads and executes the plurality of first setting commands of the first command queue until the first terminating command is read, and the state machine stops reading the first command queue after the first terminating command is read.

8. A control chip, comprising:

a first peripheral device;

a second peripheral device;

a peripheral system bus coupled to the first peripheral device and the second peripheral device; and

an event triggering host, communicating with the first peripheral device and the second peripheral device via the peripheral system bus, comprising:

an event receiving interface for receiving a first event request;

a state machine, when the first event request is triggered, the state machine executes the first setting instruction to access the first peripheral device or the second peripheral device; and

and the state machine accesses the first peripheral device or the second peripheral device through the master interface and the peripheral system bus.

9. The control chip as claimed in claim 8, wherein the first instruction queue further stores a second configuration instruction, the state machine executes the first configuration instruction to configure the first peripheral device when the first event request is triggered, and executes the second configuration instruction to configure the second peripheral device when a second event request is triggered.

10. A control method for controlling a first peripheral device and a second peripheral device, the control method comprising:

storing a setting instruction, wherein the setting instruction is provided by a processor;

judging whether an event request is triggered;

executing the setting command to access the first peripheral device or the second peripheral device when the event request is triggered;

the setting instruction is executed by an event triggering main control end, the event triggering main control end responds according to the triggered event request, and the processor does not respond according to the triggered event request.