CN115794693A - GPIO (general purpose input/output) interface control method and system, storage medium and equipment - Google Patents
GPIO (general purpose input/output) interface control method and system, storage medium and equipment Download PDFInfo
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Abstract
The invention discloses a method, a system, a storage medium and a device for controlling a GPIO interface. According to the method, the state of a corresponding bit of a general IO control register or a general IO data register in a CPU is not directly modified to change the state of the GPIO interface, but the state value of the corresponding bit of a memory array in a memory is modified, namely, the corresponding virtual resource is modified, and when the state value is changed, the state change of the target GPIO interface is controlled, so that a plurality of tasks can be executed based on a time sequence interval, only one task controls the writing of the target GPIO interface corresponding to the task at the same time, the mutual exclusion control of the GPIO interface among the tasks is effectively realized, and the condition that the tasks are mutually influenced is avoided.
Description
Technical Field
The invention relates to the field of embedded technology, in particular to a GPIO interface control method, a GPIO interface control system, a storage medium and GPIO interface control equipment.
Background
There are usually a large number of peripheral devices with a simple structure in an embedded system, and for the control of these devices, only the input/output mode and the high/low level are usually determined. In the prior art, a set of General Purpose programmable IO interfaces (GPIOs) is generally provided. The CPU controls all GPIOs mainly through two registers of general IO control register and general IO data register, so as to trigger or monitor corresponding peripheral equipment by GPIOs
In the GPIO control process, when it is desired to modify the state of a GPIO, all GPIO state values are usually read first, and a bit is modified and rewritten in a GPIO data register, so that only a specific GPIO can be changed without affecting the states of other GPIOs. When a plurality of tasks periodically modify the state of the GPIO, there may be a case where a certain task pulls up the state of the GPIO at a certain time, another task just finishes reading, and the original state of the GPIO is written back again. In the case where there is no effective mutual exclusion between tasks, a situation may occur where multiple tasks modify the GPIO state simultaneously.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: how to realize the mutual exclusion control of the GPIO interface among the multiple tasks and avoid the mutual influence among the multiple tasks.
In order to solve the technical problem, the invention provides a GPIO interface control method, a GPIO interface control system, a storage medium and a GPIO interface control device
In a first aspect of the present invention, a GPIO interface control method is provided, where the GPIO interface control method is applied to an embedded system, and includes:
running a preset task;
modifying a state value corresponding to a target GPIO interface in a preset memory array based on the preset task;
and controlling the target GPIO interface based on the modified state value.
In some embodiments, before modifying the state value corresponding to the target GPIO interface in the preset memory array based on the preset task, the method further includes:
and presetting the preset memory array in a memory, wherein the state values in the preset memory array correspond to GPIO interfaces in the embedded system one by one.
In some embodiments, before the controlling the target GPIO interface based on the modified state value, the method further comprises:
starting a timer to periodically detect whether the state value in the preset memory array changes or not;
and when the state value is detected to be changed, controlling the target GPIO interface based on the modified state value.
In some embodiments, starting a timer to periodically detect whether the state value in the preset memory array changes includes:
and starting the timer and periodically detecting whether the state value in the preset memory array changes or not based on the scheduling period of the embedded system.
In some embodiments, after the controlling the target GPIO interface based on the modified state value, the method further comprises:
and controlling the peripheral equipment based on the target GPIO interface.
In a second aspect of the present invention, a storage medium is provided, where a computer program is stored, and when being executed by a processor, the computer program implements the GPIO interface control method as described in any one of the above.
In a third aspect of the present invention, there is provided a device, which includes a memory and a processor, wherein the memory stores a computer program, and when the computer program is executed by the processor, the computer program implements the GPIO interface control method as described in any one of the above.
In a fourth aspect of the present invention, an embedded system is provided, which includes: the GPIO interface control method comprises a central processing unit, a memory and a GPIO interface, wherein the central processing unit, the memory and the GPIO interface are respectively connected with a bus, a computer program is stored in the memory, and the computer program is executed by the central processing unit to realize the GPIO interface control method.
In some embodiments, the embedded system further comprises a timer, the timer being coupled to the bus.
In some embodiments, the embedded system further comprises a peripheral device.
Compared with the prior art, one or more embodiments in the above scheme can have the following advantages or beneficial effects:
the method is applied to an embedded system, and by running a preset task, the state value corresponding to the target GPIO interface in the preset memory array is modified based on the preset task, and the target GPIO interface is controlled based on the modified state value. According to the method, the state of a corresponding bit of a general IO control register or a general IO data register in a CPU is not directly modified to change the state of the GPIO interface, but the state value of the corresponding bit of a memory array in a memory is modified, namely, the corresponding virtual resource is modified, and when the state value is changed, the state change of the target GPIO interface is controlled, so that a plurality of tasks can be executed based on a time sequence interval, only one task controls the writing of the target GPIO interface corresponding to the task at the same time, the mutual exclusion control of the GPIO interface among the tasks is effectively realized, and the condition that the tasks are mutually influenced is avoided.
Drawings
The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. Wherein the included drawings are:
fig. 1 shows a flow chart of a GPIO interface control method according to an embodiment of the present invention;
fig. 2 is a schematic flowchart illustrating a GPIO interface control method according to a second embodiment of the present invention;
fig. 3 is a schematic flowchart illustrating a GPIO interface control method according to a third embodiment of the present invention;
fig. 4 is a schematic structural diagram of an embedded system according to an embodiment of the present invention;
fig. 5 shows a schematic structural diagram of an apparatus provided in an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the following will describe in detail an implementation method of the present invention with reference to the accompanying drawings and embodiments, so that how to apply technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.
There are usually a large number of peripheral devices with a simple structure in the embedded system, and for the control of these devices, only the input/output mode and the high/low level are usually determined. In the prior art, a set of General Purpose programmable IO interfaces (GPIOs) is generally provided. The CPU mainly realizes the control of all GPIOs through two registers of a general IO control register and a general IO data register, so that the GPIOs realize the triggering or monitoring of corresponding peripheral equipment
In the GPIO control process, when it is desired to modify the state of a GPIO, all GPIO state values are usually read first, and a bit is modified and rewritten in a GPIO data register, so that only a specific GPIO can be changed without affecting the states of other GPIOs. When a plurality of tasks periodically modify the state of the GPIO, there may be a case where a certain task pulls up the state of the GPIO at a certain time, another task just finishes reading, and the original state of the GPIO is written back again. In the case where there is no effective mutual exclusion between tasks, a situation may occur where multiple tasks modify the GPIO state simultaneously.
For example, task a turns over GPIO1 with a 50ms period and task B turns over GPIO2 with a 10ms period. Assume that at time t0, task a task B has read the states of all GPIOs at the same time, all at low level. Then at time t1 task a will output a high to GPIO1 and task B will write a low to GPIO1 while outputting a high to GPIO2. Therefore, at the time t1, the task a and the task B output opposite signals to the GPIO1, and the actual state of the external output of the GPIO1 is unpredictable due to the competitive access.
In view of this, the present invention provides a GPIO interface control method, which is applied to an embedded system, and which modifies a state value corresponding to a target GPIO interface in a preset memory array based on a preset task by running the preset task, and controls the target GPIO interface based on the modified state value. According to the method, the state of the corresponding bit of the general IO control register or the general IO data register in the CPU is modified, the state value of the corresponding bit of the memory array in the memory is modified instead of directly changing the state of the GPIO interface, namely, the corresponding virtual resource is modified, and the state of the target GPIO interface is controlled to change when the state value changes, so that multiple tasks can be executed based on a time sequence interval and only one task controls the writing of the target GPIO interface at the same time, the mutual exclusion control of the GPIO interface among the multiple tasks is effectively realized, the mutual influence among the multiple tasks is avoided, and the stability of the system is effectively improved.
Example one
Referring to fig. 1, fig. 1 is a schematic flowchart illustrating a flow of a GPIO interface control method according to an embodiment of the present invention, where the method is applied to an embedded system, and may include:
step S101: running a preset task;
step S102: modifying a state value corresponding to a target GPIO interface in a preset memory array based on a preset task;
step S103: and controlling the target GPIO interface based on the modified state value.
In some embodiments, the preset task may have a plurality of tasks, and the preset task may be a task of triggering the peripheral device or monitoring the peripheral device. As a specific example, the preset task may be at least one of a task of triggering a watchdog, a task of triggering an LED indicator lamp, and a task of monitoring insertion and removal of an SD card.
In the embodiment of the present invention, the preset memory array is an array preset in the memory, wherein the state values in the preset memory array correspond to the GPIO interfaces in the embedded system one to one, and the array length of the preset memory array is equal to the number of the GPIO interfaces in the embedded system. As an example, when 3 GPIO interfaces are included in an embedded system: GPIO (general purpose input/output) 1 、GPIO 2 And GPIO 3 In time, the preset memory array may be { state value 1, state value 2, state value 3}, state value 1, and GPIO 1 Correspondingly, state value 2 and GPIO 2 Correspondingly, state value 3 and GPIO 3 And (7) correspondingly. Setting the state value to be 1 at high level and 0 at low level, and operating the preset task by the GPIO 2 Modified by GPIO 2 As the target GPIO interface, the preset memory array is {0, 0} before modification, the preset memory array is {0,1,0} after step S102, and the GPIO interface can be controlled based on the state value of the second bit in the preset memory array in step S103 2 。
Based on the above example, if the preset task is executed in step S101 at this time, there are multiple preset tasks, for example, there are preset task 1 and preset task 2, and the GPIO needs to be processed when preset task 1 is executed 2 Modifying, and operating the preset task 2 by requiring GPIO 3 Modifying, namely, after the step S102 is carried out based on the preset task 1, presetting the memory array to be {0,1,0}, modifying the current preset memory array {0,1,0} based on the preset task 2 to obtain the preset memory array {0, 1}, and in the step S103, controlling the GPIO based on the state value of the second bit in the preset memory array {0, 1} 2 Controlling GPIO based on the state value of the third bit in the preset memory array {0, 1} 3 。
The GPIO interface control method provided by the invention is applied to an embedded system, and is characterized in that the preset task is operated, the state value corresponding to the target GPIO interface in the preset memory array is modified based on the preset task, and the target GPIO interface is controlled based on the modified state value. The method modifies the state of the corresponding bit of the general IO control register or the general IO data register in the CPU, does not directly change the state of the GPIO interface, but modifies the state value of the corresponding bit of the memory array in the memory, namely modifies the corresponding virtual resource, and controls the state change of the target GPIO interface when the state value is changed, so that a plurality of tasks can be executed based on time sequence intervals, and only one task controls the writing of the target GPIO interface at the same time, thereby effectively realizing the exclusive control of the GPIO interface among the plurality of tasks and avoiding the mutual influence among the plurality of tasks.
In the embodiment of the present invention, a preset memory array may be preset in the memory, which may be specifically referred to the description in the second embodiment below.
Example two
Referring to fig. 2, fig. 2 is a schematic flowchart illustrating a method for controlling a GPIO interface according to a second embodiment of the present invention, where the method is applied to an embedded system, and may include:
step S200: presetting a preset memory array in a memory, wherein state values in the preset memory array correspond to GPIO interfaces in the embedded system one by one;
step S201: running a preset task;
step S202: modifying a state value corresponding to a target GPIO interface in a preset memory array based on a preset task;
step S203: and controlling the target GPIO interface based on the modified state value.
It should be noted that, in the embodiment of the present invention, the execution sequence of step S200 and step S201 is not limited, step S200 may be executed first and then step S201 may be executed, step S201 may be executed first and then step S200 may be executed, or step S200 and step S201 may be executed simultaneously.
In this embodiment of the present invention, step S200 may specifically be to set a preset memory array in which the array length is equal to the number of GPIO interfaces in the memory, and associate the preset memory array with the GPIO interfaces, where state values in the preset memory array correspond to the GPIO interfaces in the embedded system one to one.
In some embodiments, the preset task in step S201 may have a plurality of tasks, and the preset task may be a task of triggering a peripheral device or monitoring a peripheral device. As a specific example, the preset task may be at least one of a task of triggering a watchdog, a task of triggering an LED indicator lamp, and a task of monitoring insertion and removal of an SD card.
In the embodiment of the present invention, the preset memory array in step S202 is an array preset in the memory, wherein the state values in the preset memory array correspond to the GPIO interfaces in the embedded system one to one, and the array length of the preset memory array is equal to the number of the GPIO interfaces in the embedded system. As an example, when 3 GPIO interfaces are included in an embedded system: GPIO 1 、GPIO 2 And GPIO 3 In time, the preset memory array may be { state value 1, state value 2, state value 3}, state value 1, and GPIO 1 Correspondingly, state value 2 and GPIO 2 Correspondingly, state value 3 and GPIO 3 And (7) corresponding. Setting the state value to be 1 when the high level is set and the state value to be 0 when the low level is set, and operating the preset task, the GPIO is required to be adjusted 2 Modified by GPIO 2 As the target GPIO interface, the preset memory array is {0, 0} before modification, the preset memory array is {0,1,0} after step S202, and the GPIO interface can be controlled based on the state value of the second bit in the preset memory array in step S203 2 。
Based on the above example, if the preset task is executed in step S201, there are multiple preset tasks, for example, there are preset task 1 and preset task 2, and GPIO is required to be executed when preset task 1 is executed 2 Modification is carried out, and GPIO is required to be modified when preset task 2 is operated 3 Modifying, namely presetting the memory array to be {0,1,0} after the step S202 is carried out based on the preset task 1, modifying the current preset memory array {0,1,0} based on the preset task 2 to obtain the preset memory array {0, 1}, and controlling GPIO (general purpose input/output) based on the state value of the second bit in the preset memory array {0, 1} in the step S203 2 Controlling GPIO based on the state value of the third bit in the preset memory array {0, 1} 3 。
The method is applied to the embedded system, the preset memory array is arranged in the memory in advance, the state values in the preset memory array correspond to the GPIO interfaces in the embedded system one by one, the preset task is operated, the state value corresponding to the target GPIO interface in the preset memory array is modified based on the preset task, and the target GPIO interface is controlled based on the modified state value. The method presets virtual resources corresponding to the GPIO interface, modifies the state of a corresponding bit of a general IO control register or a general IO data register in a CPU (Central processing Unit) not directly to change the state of the GPIO interface, but modifies the state value of a corresponding bit of a memory array in a memory, namely modifies the corresponding virtual resources, and controls the state change of a target GPIO interface when the state value is changed, so that a plurality of tasks can be executed based on a time sequence interval, only one task controls the writing of the target GPIO interface corresponding to the task at the same time, the mutual exclusion control of the GPIO interface among the tasks is effectively realized, and the mutual influence among the tasks is avoided.
In the embodiment of the present invention, before controlling the target GPIO interface based on the modified state value, whether the state value in the preset memory array changes may be periodically detected, and control may be performed in time, which may be specifically described in embodiment three.
EXAMPLE III
It should be noted that this embodiment can be implemented based on the above embodiment one or embodiment two, and the following description will take the implementation based on embodiment two as an example.
Referring to fig. 3, fig. 3 is a schematic flowchart illustrating a method for controlling a GPIO interface according to a third embodiment of the present invention, where the method is applied to an embedded system and may include:
step S300: presetting a preset memory array in a memory in advance, wherein state values in the preset memory array correspond to GPIO interfaces in the embedded system one by one;
step S301: running a preset task;
step S302: modifying a state value corresponding to a target GPIO interface in a preset memory array based on a preset task;
step S303: starting a timer to periodically detect whether the state value in the preset memory array changes or not;
step S304: and when the state value changes, controlling the target GPIO interface based on the modified state value.
It should be noted that, in the embodiment of the present invention, the execution sequence of step S300 and step S301 is not limited, and step S300 may be executed first and then step S301 may be executed, step S301 may be executed first and then step S300 may be executed, or step S300 and step S301 may be executed simultaneously.
In this embodiment of the present invention, step S300 may specifically be to set a preset memory array in which the array length is equal to the number of GPIO interfaces in the memory, and associate the preset memory array with the GPIO interfaces, where state values in the preset memory array correspond to the GPIO interfaces in the embedded system one to one.
In some embodiments, the preset task in step S301 may have a plurality of tasks, and the preset task may be a task for triggering a peripheral device or monitoring a peripheral device. As a specific example, the preset task may be at least one of a task of triggering a watchdog, a task of triggering an LED indicator lamp, and a task of monitoring insertion and removal of an SD card.
In this embodiment of the present invention, the preset memory array in step S302 is an array set in the memory in advance, where the state values in the preset memory array correspond to the GPIO interfaces in the embedded system one to one, and the length of the preset memory array is equal to the number of the GPIO interfaces in the embedded system. As an example, when 3 GPIO interfaces are included in an embedded system: GPIO (general purpose input/output) 1 、GPIO 2 And GPIO 3 In this case, the preset memory array may be { state value 1, state value 2, state value 3}, state value 1, and GPIO 1 Correspondingly, state value 2 and GPIO 2 Correspondingly, state value 3 and GPIO 3 And (7) correspondingly. Setting the state value to be 1 at high level and 0 at low level, and operating the preset task by the GPIO 2 Modified by GPIO 2 As the target GPIO interface, the preset memory array is {0, 0} before modification, the preset memory array is {0,1,0} after step S302, and the preset memory array may be based on the second memory array in the preset memory array in step S304Bit state value control GPIO 2 。
Based on the above example, if the preset task is executed in step S301, there are multiple preset tasks, for example, there are preset task 1 and preset task 2, and the GPIO needs to be executed when the preset task 1 is executed 2 Modification is carried out, and GPIO is required to be modified when preset task 2 is operated 3 Modifying, namely, after the step S302 is carried out based on the preset task 1, presetting the memory array to be {0,1,0}, modifying the current preset memory array {0,1,0} based on the preset task 2 to obtain the preset memory array {0, 1}, and in the step S304, controlling the GPIO based on the state value of the second bit in the preset memory array {0, 1} 2 Controlling GPIO based on the state value of the third bit in the preset memory array {0, 1} 3 。
In the embodiment of the present invention, step S303 may be executed in synchronization with step S301, and step S303 may also be executed after step S301 and before step S304.
In this embodiment of the present invention, step S303 may specifically be to start a timer and periodically detect whether the state value in the preset memory array changes based on a scheduling period of the embedded system. As an example, whether the state value in the preset memory array is changed or not may be periodically detected based on the shortest scheduling period that can be achieved by the embedded system, and control may be performed in real time.
In this embodiment of the present invention, step S304 may specifically be to control the target GPIO interface based on the modified state value when it is detected that the state value changes, which is beneficial to quickly controlling the target GPIO interface.
It should be noted that, in the embodiment of the present invention, the method may further include step S305: and controlling the peripheral equipment based on the target GPIO interface.
In some embodiments the peripheral devices may include a watchdog and/or LED indicator, where the watchdog is a timer circuit that may be used to enable the system to automatically reset in the event of an abnormal condition.
The method is applied to an embedded system, and comprises the steps of presetting a preset memory array in a memory, enabling state values in the preset memory array to correspond to GPIO interfaces in the embedded system one by one, operating a preset task, modifying the state values corresponding to target GPIO interfaces in the preset memory array based on the preset task, starting a timer to periodically detect whether the state values in the preset memory array change, and controlling the target GPIO interfaces based on the modified state values when the state values are detected to change. The method presets virtual resources corresponding to the GPIO interface, modifies the state of a corresponding bit of a general IO control register or a general IO data register in a CPU (Central processing Unit) not directly to change the state of the GPIO interface, but modifies the state value of a corresponding bit of a memory array in a memory, namely modifies the corresponding virtual resources, and controls the state change of a target GPIO interface when the state value is changed, so that a plurality of tasks can be executed based on a time sequence interval, only one task controls the writing of the target GPIO interface corresponding to the task at the same time, the mutual exclusion control of the GPIO interface among the tasks is effectively realized, and the mutual influence among the tasks is avoided. In addition, a timer can be started to periodically detect whether the state value in the preset memory array changes, and the target GPIO interface can be controlled timely.
Correspondingly, the embodiment of the present invention further provides an embedded system, which can be specifically referred to the description in the fourth embodiment below.
Example four
Referring to fig. 4, fig. 4 shows a schematic structural diagram of an embedded system according to an embodiment of the present invention, which may include:
the central processing unit 41, the memory 42 and the GPIO interface 43 are respectively connected to the bus, the memory 42 stores a computer program, and the computer program is executed by the central processing unit 41 to implement the GPIO interface control method in any one of the first to third embodiments.
In the embodiment of the present invention, a plurality of GPIO interfaces 43 may be provided, and a target GPIO interface may be determined from the GPIO interfaces 43 based on a preset task that is executed.
In some embodiments, the embedded memory system may further include a timer 44, the timer 44 is connected to the bus, and the timer 44 may be configured to periodically detect whether the status value of the predetermined memory array in the memory 42 changes.
In some embodiments, the embedded memory system may also include a peripheral device 45, and as an example the peripheral device 43 may include a watchdog and/or an LED indicator, where the watchdog is a timer circuit that may be used to enable the system to automatically reset in the event of an abnormal condition. The watchdog mainly has an input, i.e., a watchdog feeding pin and a RESET pin, the watchdog feeding pin is connected with a GPIO interface 43 arranged on the central processing unit 41, the RESET pin is connected with a RESET pin of the central processing unit 41, if the level of the watchdog feeding pin is not changed within a certain time, the watchdog will give a RESET signal to the central processing unit 41 to RESET the central processing unit 41, thereby preventing abnormal situations such as program dead loop and the like.
The GPIO interface control system provided in the embodiments of the present invention may include a central processing unit 41, a memory 42, and a GPIO interface 43, where the central processing unit 41, the memory 42, and the GPIO interface 43 are connected to a bus, and a computer program is stored in the memory 42, and executed by the central processing unit 41, the GPIO interface control method in any one of the first to third embodiments may be implemented by the computer program, so as to achieve the same advantageous effects as those in any one of the first to third embodiments.
Another aspect of the present invention further provides a storage medium, where a computer program is stored, and when the computer program is executed by a processor, the GPIO interface control method according to any one of the above embodiments can be implemented.
The processes, functions, methods, and/or software described above may be recorded, stored, or fixed in one or more computer-readable storage media that include program instructions to be implemented by a computer to cause a processor to execute the program instructions. The storage media may also include program instructions, data files, data structures, etc., either alone or in combination. The storage media or program instructions may be those specially designed and constructed for the purposes of the computer software, or they may be of the kind well known and available to those having skill in the computer software arts. Examples of computer readable media include: magnetic media such as hard disks, floppy disks, and magnetic tape; optical media, such as CDROM disks and DVDs; magneto-optical media, e.g., optical disks; and hardware devices specifically configured to store and execute program instructions, such as Read Only Memory (ROM), random Access Memory (RAM), flash memory, and the like. Examples of program instructions include both machine code, such as produced by a compiler, and files containing higher level code that may be executed by the computer using an interpreter. The described hardware devices may be configured to act as one or more software modules to perform the operations and methods described above, and vice versa. In addition, computer readable storage media may be distributed over network coupled computer systems and may store and execute computer readable code or program instructions in a distributed fashion.
Another aspect of the present invention provides a device, referring to fig. 5, fig. 5 illustrates a schematic structural diagram of a device provided in an embodiment of the present invention, which includes a memory 51 and a processor 52, where the memory 51 stores a computer program, and when the computer program is executed by the processor 52, the GPIO interface control method according to any one of the above embodiments can be implemented.
It should be noted that the device may include one or more processors 52 and a memory 51, and the processors 52 and the memory 51 may be connected by a bus or other means. The memory 51, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 52 executes various functional applications and data processing of the device by running the nonvolatile software programs, instructions and modules stored in the memory 51, that is, implements the GPIO interface control method as described in any one of the above embodiments.
Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A GPIO interface control method is applied to an embedded system and is characterized by comprising the following steps:
running a preset task;
modifying a state value corresponding to a target GPIO interface in a preset memory array based on the preset task;
and controlling the target GPIO interface based on the modified state value.
2. The method of claim 1, wherein before modifying the state value corresponding to the target GPIO interface in the preset memory array based on the preset task, the method further comprises:
and presetting the preset memory array in a memory, wherein the state values in the preset memory array correspond to GPIO interfaces in the embedded system one by one.
3. The method of claim 1, wherein before the controlling the target GPIO interface based on the modified state value, the method further comprises:
starting a timer to periodically detect whether the state value in the preset memory array changes or not;
and when the state value is detected to be changed, controlling the target GPIO interface based on the modified state value.
4. The method of claim 3, wherein starting a timer to periodically detect whether the state value in the predetermined memory array has changed comprises:
and starting the timer and periodically detecting whether the state value in the preset memory array changes or not based on the scheduling period of the embedded system.
5. The method of claim 1, wherein after the controlling the target GPIO interface based on the modified state value, the method further comprises:
and controlling the peripheral equipment based on the target GPIO interface.
6. A storage medium, characterized in that the storage medium has stored therein a computer program, which when executed by a processor implements the GPIO interface control method of any one of claims 1 to 5.
7. An apparatus, characterized by comprising a memory and a processor, wherein the memory stores a computer program, and the computer program is executed by the processor to implement the GPIO interface control method of any one of claims 1 to 5.
8. An embedded system, comprising: the GPIO interface control device comprises a central processing unit, a memory and a GPIO interface, wherein the central processing unit, the memory and the GPIO interface are respectively connected with a bus, a computer program is stored in the memory, and the computer program realizes the GPIO interface control method of any one of claims 1 to 5 when being executed by the central processing unit.
9. The embedded system of claim 8, further comprising a timer, the timer coupled to the bus.
10. The embedded system of claim 8, further comprising a peripheral device.
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| CN202111057417.8A Pending CN115794693A (en) | 2021-09-09 | 2021-09-09 | GPIO (general purpose input/output) interface control method and system, storage medium and equipment |
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