JPH0319582B2 - - Google Patents
Info
- Publication number
- JPH0319582B2 JPH0319582B2 JP1938282A JP1938282A JPH0319582B2 JP H0319582 B2 JPH0319582 B2 JP H0319582B2 JP 1938282 A JP1938282 A JP 1938282A JP 1938282 A JP1938282 A JP 1938282A JP H0319582 B2 JPH0319582 B2 JP H0319582B2
- Authority
- JP
- Japan
- Prior art keywords
- reset
- power supply
- state
- power
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000007246 mechanism Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- 230000006266 hibernation Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
- G06Q40/00—Finance; Insurance; Tax strategies; Processing of corporate or income taxes
- G06Q40/02—Banking, e.g. interest calculation or account maintenance
Landscapes
- Business, Economics & Management (AREA)
- Accounting & Taxation (AREA)
- Finance (AREA)
- Engineering & Computer Science (AREA)
- Development Economics (AREA)
- Economics (AREA)
- Marketing (AREA)
- Strategic Management (AREA)
- Technology Law (AREA)
- Physics & Mathematics (AREA)
- General Business, Economics & Management (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Sources (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は複数の取引機構（Ｉ／Ｏ）に個別電源
を設けて、これらの個別電源のオンオフを電源制
御部により制御する自動取引装置に関するもので
ある。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an automatic transaction device in which a plurality of transaction mechanisms (I/Os) are provided with individual power supplies, and the on/off of these individual power supplies is controlled by a power supply control unit. It is something.
この種の自動取引装置はたとえば第１図ａに装
置１０で示すように、各Ｉ／Ｏ１1〜１4に対応し
て個別電源２1〜２4が設けられる。そして、これ
らの個別電源２1〜２4を電源制御部３によつてオ
ンオフ制御するように構成される。この構成によ
つて、取引の種類（形態）に応じて、その取引に
必要なＩ／Ｏの電源のみをオンする制御が可能と
なり、全体として装置の消費電力を大幅に削減す
ることが可能となる。なお、第１図ａにおいて
は、装置１０のＩ／Ｏとしてカードリーダ１1、
キヤツシユカウンタ１2、通帳プリンタ１3、紙幣
鑑別機１4を示すものである。 In this type of automatic transaction apparatus, for example, as shown in the apparatus 10 in FIG. 1A, individual power supplies 21 to 24 are provided corresponding to the respective I/Os 11 to 14 . The individual power supplies 2 1 to 2 4 are then controlled to be turned on and off by the power supply control section 3 . With this configuration, it is possible to control the power of only the I/O required for the transaction to be turned on depending on the type (form) of the transaction, and it is possible to significantly reduce the power consumption of the device as a whole. Become. In addition, in FIG. 1a, the card reader 1 1 is used as the I/O of the device 10,
It shows a cash counter 1 2 , a passbook printer 1 3 , and a banknote validator 1 4 .
しかしてＩ／Ｏ毎に個別電源を持つ自動取引装
置において、装置リセツトがかかると従来では電
源制御部３を含む全ての制御部がリセツトされ
る。つまり各個別電源２1〜２4も一旦オフとさ
れ、各Ｉ／Ｏ１1〜１4にパワーオンリセツトがか
かるように構成されている。なお、この装置リセ
ツトがかかるのは、たとえば主制御部（プログラ
ム）によつて一つの取引が完了した場合、または
装置障害等により係員によつて操作される制御キ
ー５から指示される場合がある。
Conventionally, in an automatic transaction apparatus having a separate power supply for each I/O, when the apparatus is reset, all control sections including the power supply control section 3 are reset. In other words, each of the individual power supplies 2 1 to 2 4 is also once turned off, and each I/O 1 1 to 1 4 is configured to undergo a power-on reset. Note that this device reset may be performed, for example, when a transaction is completed by the main control unit (program), or when an instruction is given from the control key 5 operated by a staff member due to a device failure, etc. .
第１図ｂは、従来の装置リセツト時の動作を示
す図である。すなわち、リセツト指示（時刻t1）
により主電源４から装置各部への電源供給が全て
一旦オフとされる。 FIG. 1b is a diagram showing the operation at the time of resetting a conventional device. In other words, the reset instruction (time t 1 )
As a result, the power supply from the main power source 4 to each part of the device is temporarily turned off.
これにより、プロセツサを含む主制御部（図示
せず）および各Ｉ／Ｏ１1〜１4が一旦リセツトさ
れることになる。しかる後、時刻t2に再び主電源
４からの給電が再開される。この電源復帰によ
り、まず主制御部はイニシヤルルーチン（プログ
ラム）を実行し、装置の初期化を行なう。この装
置立上り（時間Ｔ）の動作終了後、つまり時刻t3
において主制御部はＩ／Ｏ選択命令等の通常動作
を行なうことになる。 As a result, the main control section (not shown) including the processor and each of the I/Os 11 to 14 are reset once. Thereafter, power supply from the main power source 4 is restarted again at time t2 . When the power is restored, the main control section first executes an initial routine (program) to initialize the device. After the start-up of the device (time T), that is, time t 3
In this step, the main control section performs normal operations such as I/O selection commands.
このように従来では「リセツト」がかかる毎に
各Ｉ／Ｏの個別電源がオンオフ駆動されるもので
ある。従つて、各個別電源の寿命を短くするとい
う問題点があつた。
In this way, conventionally, each I/O's individual power supply is turned on and off every time a "reset" is applied. Therefore, there was a problem that the life of each individual power source was shortened.
本発明の自動取引装置は、取引を遂行するに必
要な処理を行なう複数の取引処理機構と、これら
各取引処理機構に各々対応して設けられる個別電
源と、これら個別電源の電源オンオフ制御を行な
う電源制御部と、装置のリセツト手段によつてリ
セツト指示があつた時点以前の各個別電源の電源
オンオフ状態を記憶する保持手段とを設け、
装置のリセツト指示があつた場合には、各個別
電源は前記保持手段によつて表わされる状態に基
づきその状態を保持しておき、
リスタート時前記保持手段の状態を電源制御部
に再セツトし、次取引を遂行するに必要な取引処
理機構に対応し新たに必要な個別電源のみをオン
とし、不要な個別電源をオフとするようにしたこ
とを特徴とするものである。
The automatic transaction device of the present invention includes a plurality of transaction processing mechanisms that perform processing necessary to carry out transactions, individual power supplies provided corresponding to each of these transaction processing mechanisms, and power on/off control of these individual power supplies. A power supply control unit and a holding means for storing the power on/off state of each individual power supply before a reset instruction is given by the reset means of the device are provided, and when a reset instruction of the device is given, each individual power supply is maintains the state based on the state represented by the holding means, and upon restart, resets the state of the holding means in the power supply control unit to support the transaction processing mechanism necessary to execute the next transaction. The present invention is characterized in that only newly required individual power supplies are turned on, and unnecessary individual power supplies are turned off.
とくに制御キーによつて装置リセツトがかけら
れるのは、装置主制御部のプロセツサの暴走、ま
たは特定Ｉ／Ｏの動作障害によつて自動取引装置
が休止状態となつた場合である。
In particular, the device is reset using the control key when the automated teller machine goes into a hibernation state due to a runaway of the processor in the device's main control section or an operational failure of a specific I/O.
従つて、従来のように、全Ｉ／Ｏの個別電源オ
フによる全てのＩ／Ｏのリセツトは必要がない。
つまり、まず主制御部をリセツトし、主制御部の
再起動によつて装置は初期状態に戻る。この時、
動作不良となつていたＩ／Ｏについては、再起動
がかけられた主制御部による個別リセツト（ソフ
トリセツト）によつて対応できるものである。 Therefore, it is not necessary to reset all I/Os by turning off the power to all I/Os individually, as in the conventional case.
That is, first, the main control section is reset, and by restarting the main control section, the apparatus returns to its initial state. At this time,
The malfunctioning I/O can be dealt with by individual reset (soft reset) by the main control unit that has been restarted.
以下、実施例を用いて本発明を詳述する。 Hereinafter, the present invention will be explained in detail using Examples.
第２図は本発明の一実施例を示す図である。同
図は、第１図に示した装置における電源制御部３
の詳細構成を示す。すなわち、電源制御部３は、
レジスタ等から成る制御回路１１を有し、このレ
ジスタにセツトされるフラグの状態に応じて各個
別電源２1〜２4へ制御信号を供給する。制御回路
１１への電源投入指令は、装置の立上り時には制
御キー５によつて与えられる。また装置稼動時に
は、図示しない主制御部により各Ｉ／Ｏに対応し
たフラグ制御が行なわれるものである。制御信号
が与えられる各個別電源２1〜２4は、たとえばト
ランジスタを用いた駆動回路より成る。以下、こ
こを電源切替回路１と称する。そして、制御回路
１１からの制御信号に応じて、電源切替回路１３
の各個別電源２1〜２4は、主電源４からの電力を
選択的に対応するＩ／Ｏへ供給することになる。
FIG. 2 is a diagram showing an embodiment of the present invention. The figure shows the power supply control section 3 in the device shown in FIG.
The detailed configuration is shown below. That is, the power supply control section 3
It has a control circuit 11 consisting of a register and the like, and supplies a control signal to each of the individual power supplies 2 1 to 2 4 according to the state of a flag set in this register. A power-on command to the control circuit 11 is given by the control key 5 when the device is started up. Further, when the apparatus is in operation, flag control corresponding to each I/O is performed by a main control section (not shown). Each of the individual power supplies 2 1 to 2 4 to which a control signal is applied is composed of a drive circuit using, for example, a transistor. Hereinafter, this will be referred to as a power supply switching circuit 1. Then, according to the control signal from the control circuit 11, the power supply switching circuit 13
Each of the individual power supplies 2 1 to 2 4 selectively supplies power from the main power supply 4 to the corresponding I/O.
従来においては、装置の制御手段である制御キ
ー５によるリセツト指示により、制御回路１１の
レジスタ等がリセツトされていた。これにより、
制御回路１１のレジスタ内のフラグが全て“０”
となり、各Ｉ／Ｏの個別電源２1〜２4が主電源４
より切離される構成となつていた。なお制御回路
１１へのリセツト信号は、主制御部、メモリ等の
各回路へも供給されることは云うまでもない。 Conventionally, the registers and the like of the control circuit 11 have been reset by a reset instruction from the control key 5, which is the control means of the device. This results in
All flags in the register of control circuit 11 are “0”
Therefore, the individual power supplies 2 1 to 2 4 of each I/O are the main power supply 4.
It was structured to be more separated. It goes without saying that the reset signal to the control circuit 11 is also supplied to each circuit such as the main control section and memory.
これに対し、本実施例においては、このリセツ
ト信号を点線で図示するように、各個別電源２1
〜２4に供給するとともに、さらに、制御回路１
１の出力する制御信号の状態を保持するための保
持回路１２を設けてこれにも供給する。これらの
回路に供給されるリセツト信号はデータをリセツ
トするのではなくリセツト信号が与えられると、
各Ｉ／Ｏへの電源状態をリセツト直前の状態に保
持しておくように動作させる。 On the other hand, in this embodiment, this reset signal is expressed as a dotted line for each individual power supply 2 1
~2 4 , and furthermore, control circuit 1
A holding circuit 12 is provided to hold the state of the control signal outputted by the control signal 1, and the holding circuit 12 is also supplied thereto. The reset signal supplied to these circuits does not reset the data, but when the reset signal is applied,
The power supply state to each I/O is maintained at the state immediately before the reset.
この保持回路１２では、電源切替回路１３へ供
給されるリセツト信号により、たとえば、各個別
電源２1〜２4へ与えられる回路１１からの制御信
号の状態を保持する回路（ラツチ回路等）を起動
する。すなわち、このリセツト信号によつて個別
電源２1〜２4の電源オンオフ譲態を、リセツト指
示がある直前の状態に保持するようにする。 In this holding circuit 12, the reset signal supplied to the power supply switching circuit 13 activates, for example, a circuit (such as a latch circuit) that holds the state of the control signal from the circuit 11 given to each of the individual power supplies 21 to 24 . do. That is, this reset signal causes the power on/off states of the individual power supplies 2 1 to 2 4 to be maintained in the state immediately before the reset instruction was issued.
また保持回路１２は、リセツト信号により、制
御回路１１が出力する制御信号の状態（リセツト
がかかる前の状態）を記憶する。そして、リセツ
ト後の初期起動が終了した主制御部からのリスタ
ート命令によつて、リセツト前の電源状態を制御
回路１１に再セツトする。これとともに、リセツ
ト前の電源状態を主制御部や制御キーパネルに通
知（表示）する。 Further, the holding circuit 12 stores the state of the control signal output from the control circuit 11 (the state before the reset) based on the reset signal. Then, the power supply state before the reset is reset to the control circuit 11 by a restart command from the main control section after the initial start-up after the reset has been completed. At the same time, the main control unit and control key panel are notified (displayed) of the power state before the reset.
第３図ａ〜ｅは、本実施例における装置リセツ
ト時のＩ／Ｏ電源の状態を示すものである。同図
ａ〜ｄは第１図に示した各Ｉ／Ｏの電源ON・
OFF状態を示す。同図ｅは主制御部における制
御命令を示す。まず、制御キーによるリセツト指
示により、装置各部にリセツト信号が発せられ
る。従来においては破線で示すように、各Ｉ／Ｏ
の電源も一斉にオフとされていた。 3a to 3e show the state of the I/O power supply at the time of device reset in this embodiment. Figures a to d show that each I/O shown in Figure 1 is turned on and
Indicates OFF state. Figure e shows control commands in the main control section. First, in response to a reset instruction from a control key, a reset signal is issued to each part of the device. In the past, each I/O
The power was also turned off all at once.
本実施例においては上述のように、Ｉ／Ｏの電
源はリセツト前の状態を示す。なお、同図では全
てのＩ／Ｏ電源がオン状態の時に、リセツトがか
けられた例を示すものである。従つてリセツト前
から電源がオフのＩ／Ｏについてはリセツト後も
オフのままに保持されることになる。 In this embodiment, as described above, the I/O power supply shows the state before reset. Note that this figure shows an example in which a reset is applied when all I/O power supplies are in the on state. Therefore, I/Os whose power was off before the reset will remain off after the reset.
次に、リセツト信号パルスの終了により、主制
御部よりリスタート信号が発せられる。これによ
り主制御部のプロセツサ等は初期ルーチンを実行
することになる。一方Ｉ／Ｏ電源については、上
述のように保持回路１２による制御回路１１への
電源状態再セツトによつて、リセツト前の状態に
保持されている。そして主制御部の初期化終了に
よつて、主制御部によるＩ／Ｏ電源のオンオフ制
御が行なわれる。すなわち、装置初期状態におい
て不要なＩ／Ｏについての電源をオフとする。同
図に示す例では、主制御部からのＩ／Ｏ選択命令
に従つて、通帳プリンタと鑑別機の電源がオフと
される。つまり、カードリーダとキヤツシユカウ
ンタの電源はオン状態のままとして、いわゆる顧
客待ち状態となる。 Next, upon completion of the reset signal pulse, a restart signal is issued from the main control section. This causes the processor of the main control unit to execute the initial routine. On the other hand, the I/O power supply is maintained in the state before the reset by the holding circuit 12 resetting the power state to the control circuit 11 as described above. Upon completion of the initialization of the main control section, the main control section performs on/off control of the I/O power supply. That is, power is turned off for unnecessary I/O in the initial state of the device. In the example shown in the figure, the power to the passbook printer and the validator are turned off in accordance with an I/O selection command from the main control unit. In other words, the power to the card reader and cash counter remain on, and the machine enters a so-called customer waiting state.
なお、特定Ｉ／Ｏたとえばキヤツシユカウンタ
の動作不良に応じて装置がリセツトされたとす
る。この場合は、制御キーによるリセツトととも
に、キヤツシユカウンタのテストという命令初期
化指令が入力される。この結果、主制御部は、上
記顧客待ち状態（通帳プリンタおよび鑑別機の電
源オフ）の後に、キヤツシユカウンタのみの個別
リセツト（パワーオンリセツト）がかけられるこ
とになる。 Assume that the device is reset in response to malfunction of a specific I/O, such as a cash counter. In this case, along with the reset using the control key, an initialization command for testing the cash counter is input. As a result, the main control section performs an individual reset (power-on reset) of only the cash counter after the customer waiting state (power off of the passbook printer and validating machine).
以上説明したように、本発明によれば、前命令
の実行が完了しリセツトされた際、前のＩ／Ｏ電
源の状態を保持回路により保持しておき、次の命
令によるリスタートによりこの状態を電源制御回
路に戻し、命令の初期化により引続き必要なもの
をオンのままとし、新たに必要なものをオン、不
要なものをオフとする。これにより、Ｉ／Ｏ電源
のオンオフ回数を有効に減少することができるか
ら、Ｉ／Ｏ電源の寿命延長に役立つものである。
As explained above, according to the present invention, when the execution of the previous instruction is completed and the I/O power supply is reset, the previous I/O power supply state is held by the holding circuit, and this state is reset by the restart by the next instruction. is returned to the power supply control circuit, and by initializing the command, necessary items continue to be turned on, new necessary items are turned on, and unnecessary items are turned off. This makes it possible to effectively reduce the number of times the I/O power supply is turned on and off, thereby contributing to extending the life of the I/O power supply.
第１図ａ，ｂは従来例の構成と動作説明図、第
２図は本発明の実施例の構成説明図、第３図ａ〜
ｅは本発明の動作説明図であり、図中、２1〜２4
はＩ／Ｏ電源、４は主電源、１１は電源制御回
路、１２は保持回路、１３は電源切替回路を示
す。
Figures 1a and 1b are explanatory diagrams of the configuration and operation of the conventional example, Figure 2 is an explanatory diagram of the configuration of the embodiment of the present invention, and Figures 3a-
e is an explanatory diagram of the operation of the present invention, and in the figure, 2 1 to 2 4
1 is an I/O power supply, 4 is a main power supply, 11 is a power supply control circuit, 12 is a holding circuit, and 13 is a power supply switching circuit.
Claims (1)
取引処理機構と、これら各取引処理機構に各々対
応して設けられる個別電源と、これら個別電源の
電源オンオフ制御を行なう電源制御部と、装置の
リセツト手段によつてリセツト指示があつた時点
以前の各個別電源の電源オンオフ状態を記憶する
保持手段とを設け、 装置のリセツト指示があつた場合には、各個別
電源は前記保持手段によつて表わされる状態に基
づきその状態を保持しておき、 リスタート時前記保持手段の状態を電源制御部
に再セツトし、次取引を遂行するに必要な取引処
理機構に対応し新たに必要な個別電源のみをオン
とし、不要な個別電源をオフとするようにしたこ
とを特徴とする自動取引装置。[Scope of Claims] 1. A plurality of transaction processing mechanisms that perform processing necessary to carry out transactions, individual power supplies provided corresponding to each of these transaction processing mechanisms, and a power source that controls power on/off of these individual power supplies. A control section and a holding means for storing the power on/off state of each individual power supply before a reset instruction is given by a reset means of the device are provided, and when a reset instruction of the device is given, each individual power supply is turned on and off. The state is held based on the state represented by the holding means, and upon restart, the state of the holding means is reset in the power control unit to correspond to the transaction processing mechanism necessary to carry out the next transaction. An automatic transaction device characterized in that only newly required individual power supplies are turned on and unnecessary individual power supplies are turned off.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57019382A JPS58137080A (en) | 1982-02-09 | 1982-02-09 | Automatic transaction device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57019382A JPS58137080A (en) | 1982-02-09 | 1982-02-09 | Automatic transaction device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58137080A JPS58137080A (en) | 1983-08-15 |
| JPH0319582B2 true JPH0319582B2 (en) | 1991-03-15 |
Family
ID=11997753
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57019382A Granted JPS58137080A (en) | 1982-02-09 | 1982-02-09 | Automatic transaction device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58137080A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5945580A (en) * | 1982-09-06 | 1984-03-14 | Omron Tateisi Electronics Co | Transaction processing device |
| JP5321100B2 (en) * | 2009-02-02 | 2013-10-23 | 沖電気工業株式会社 | Automatic transaction equipment |
| JP2011085983A (en) * | 2009-10-13 | 2011-04-28 | Hitachi Omron Terminal Solutions Corp | Automatic teller machine |
| JP5337063B2 (en) * | 2010-01-18 | 2013-11-06 | 日立オムロンターミナルソリューションズ株式会社 | Automatic cash transaction apparatus and automatic cash transaction system |
| JP5445228B2 (en) * | 2010-03-03 | 2014-03-19 | 沖電気工業株式会社 | Check-in terminal |
| JP5692352B2 (en) * | 2013-12-25 | 2015-04-01 | 沖電気工業株式会社 | Ticketing terminal |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57146373A (en) * | 1981-03-04 | 1982-09-09 | Nec Corp | Power supply system for automatic transaction machine |
-
1982
- 1982-02-09 JP JP57019382A patent/JPS58137080A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57146373A (en) * | 1981-03-04 | 1982-09-09 | Nec Corp | Power supply system for automatic transaction machine |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58137080A (en) | 1983-08-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6327653B1 (en) | Technique for easily changing operating systems of a digital computer system using at least two pushbuttons | |
| US5416912A (en) | System for handling exceptions occurring during parallel execution of microinstructions | |
| US5535397A (en) | Method and apparatus for providing a context switch in response to an interrupt in a computer process | |
| US6122748A (en) | Control of computer system wake/sleep transitions | |
| JPH0816870B2 (en) | System for draining the instruction pipeline | |
| JPH02202636A (en) | Computer with fault tolerant capacity | |
| JPH07248897A (en) | Method and device for recovery from exception in computer system | |
| US7174549B2 (en) | Computer system and method for storing product keys thereof | |
| EP0588252A2 (en) | Apparatus for implementing interrupts in pipelined processors | |
| JPH0319582B2 (en) | ||
| JPH1185513A (en) | Processor | |
| KR920006768B1 (en) | Method and device to execute two instruction sequences in an order determined in advance | |
| JPH07141176A (en) | Command retrial control system | |
| US5673391A (en) | Hardware retry trap for millicoded processor | |
| JPS6161416B2 (en) | ||
| JP2552738B2 (en) | Data processing device | |
| US20050015580A1 (en) | Method for transferring a command among a plurality of devices in a computer system | |
| JPS60134957A (en) | Parallel operation processing device | |
| JP3844197B2 (en) | Information processing device | |
| JP2797674B2 (en) | Initial setting method | |
| JPH0210455B2 (en) | ||
| JP2978321B2 (en) | Data processing device, control method thereof, and data processing system device | |
| JPH0426913Y2 (en) | ||
| JP2002041437A (en) | Hard disk drive switching system | |
| JPH0670768B2 (en) | Power-on control method |