JPH04105156A - Common bus register controller - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a common bus register controller by stopping the operation of a microprocessor contained in an input/output controller when a conflict occurs between a register write request received from a processor and that received from the input/output controller. CONSTITUTION:When a conflict occurs between the register write request received from a processor 10 and that received from an input/output controller 30, a halt signal HALT is given to a microprocessor 32 so that the microprocessor 32 stops its operation. Meanwhile the data are written into a control register 31 from the processor 10. When the HALT state is released after the write of data is through with the processor 10, the microprocessor 32 writes its own data into the register 31. As a result, the processing efficiency is improved even when a conflict occurs with the access given to the register 31.

Description

[Detailed Description of the Invention] [Summary] Regarding a common bus register control device in a system in which a processor and a plurality of input/output control devices are connected via a common bus, the present invention relates to a common bus register control device in which a processor and a plurality of input/output control devices are connected to a control register from a channel control device and an input/output control device. In a system in which a processor and a plurality of input/output control devices are connected via a common bus, the input/output control device is installed inside the system for the purpose of efficiently processing when access requests conflict. The interface between the processor and the input/output control device is established according to the control data written from the processor and the input/output control device to the control register, and the access request to the control registers of the processor and the input/output control device is sent in the input/output control device. A collision detection circuit is provided to detect a conflict, and when a conflict between access requests from the processor and the input/output control device is detected, a stop signal is sent from the collision detection circuit to stop the operation of the microprocessor in the input/output control device. (HALT signal).

[Field of Industrial Application] The present invention relates to a common bus register control device in a system in which a processor and a plurality of input/output control devices are connected via a common bus.

In a system in which a processor and a plurality of input/output control devices are connected via a common bus, the interface between the two is often performed by a control register provided in the input/output control device. In this type of system, the problem is how to handle conflicting access requests to the control register.

[Prior Art] FIG. 5 is a block diagram showing an example of the configuration of a conventional system. In the figure, 10 is a processor (CP) and a central controller (CC) 1. It is composed of a channel control device (CHC) 2 and a main memory device (MM) 3. 20 is a common bus (C bus) connected to the processor 10 (actually, the channel control device 12 within the processor 10). 30 is a plurality of input/output control devices (10
C) and is connected to the common bus 20 in a similar manner.

40 is an input/output device (
10). As the input/output device 40, for example, a floppy disk device (FD) or a magnetic tape device (MT) is used. The input/output control device 30 is interposed between the input/output device 40 and the common bus 20 to provide an interface therebetween. Specifically, the input/output control device 30 interfaces the processor 10 and the input/output control device 30 according to control data written from the processor 10 and the input/output control device 30 to a control register 31 provided therein. It has become.

In a system configured in this way, for example, CC1
Consider a case where data is transferred from 1 to an input/output device 40 and data is written.

In this case, in the control register 31 of the input/output control device 30 where the CCII is located, the data length, the address on the main storage device 13 storing the data to be transferred, the direction of data transfer (the data in the input/output device 40 Is it sent to input/output device 4?
whether to receive data from 0), etc.

FIG. 6 is a diagram showing an example of the configuration of the control register 31. D
The SR (data status register) stores information regarding the input/output control device 30, the MAR (memory address register) stores the start address on the main storage device 13 at the time of pig transfer, and the BCR (byte・Count register) stores the number of bytes of data transfer,
The CMR (command register) stores read/write instructions from the CC] to the input/output control device 30. When the above information is written from the CC 11 to the control register 31, the CC 11 starts the input/output control device 30.

When the input/output control device 30 receives an operation request from the CCI, the input/output control device 30 performs the operation according to the contents written in the control register 31.
Transfers data from MM13.

In other words, the data from the MM13 is read and the input/output device 4
Send to 0. Once the data transfer is complete, input/output control device 3
0 writes a predetermined pig to the control register 31, CCII
Notify the end of processing. Thus, in conventional systems, operations on common bus 20 are performed via control registers 31.

FIG. 7 is a block diagram showing a conventional configuration example of the input/output control device 30. Components that are the same as those in FIG. 5 are designated by the same reference numerals. In the figure, 32 is a microprocessor that controls the overall operation of the input/output control device 30, and 33 is a register write request from the channel control device (CHC) 12 and a register write request from the input/output control device 30 that occur simultaneously. , CHC that gives priority to the channel control device 12 side
The priority circuit 34 is a selector that receives CHC data from the common bus 20 and data from the input/output control device 30 and selects either one using a select signal. The output of the selector 34 enters the control register 31 and is written therein.

The output of the CHC priority circuit 33 is used as the select signal. The output of control register 31 is then connected to both microprocessor 32 and common bus 20. The operation of the circuit configured as described above will be explained as follows.

First, it is assumed that a register write request is issued from the channel control device 12 side when there is no access conflict between the channel control device 12 and the input/output control device 30 to the control register 30 . At this time, when the CHC priority circuit 33 recognizes that it is a register write request from the channel control device 12, it sends a select signal to the selector 34,
Select CHC side data. As a result, the output data of the channel control device 12 is written to the control register 31 via the selector 34.

On the other hand, it is assumed that a register write request is issued from the input/output control device 30 side (specifically, from the microprocessor 32). At this time, when the CHC priority circuit 33 recognizes that it is a register write request from the input/output control device 30, it sends a select signal to the selector 34 to select data on the input/output control device side 30. As a result, the input/output control device data is passed through the selector 34 to the control register 31.
written to.

Here, if register write requests are generated from both the channel control device 12 and the input/output control device 30 at the same time, the CHC priority circuit 33
Give priority to register write requests from 2. As a result,
The selector 34 selects data from the channel control device 12 based on the select signal from the CHC priority circuit 33 and writes it into the control register 31. As a result, the register write request from the input/output control device 30 is ignored.

[Problems to be Solved by the Invention] As described above, writing/reading is performed on the control register 31 from both the channel control device 12 and the input/output control device 30. Therefore, writing to this control register 31 may occur from both the channel control device 12 and the input/output control device 30 (write conflict). When such access requests to the control register 31 conflict, conventionally the access from the channel control device 12 is given priority, so the write from the input/output control device 30 is ignored.

On the other hand, the microprocessor 32 in the input/output control device 30
own register write request and channel control unit 12
I don't know if there is a conflict with the register write request access. Therefore, when a register write request is issued, the control register 3 is checked each time whether data has been written.
I had to go see the contents of 1. If the data has not been written, it is necessary to perform the write operation and repeat the check until the data is written. In the case of an input/output control device using a microprocessor, these operations are performed by firmware, but a series of write and check routines are required every time a write is made to the control register 31, which is inefficient in terms of time. .

The present invention has been made in view of the above-mentioned problems, and provides a common bus register that can efficiently process when there is conflict between access requests to a control register from a channel control device and an input/output control device. The purpose is to provide a control device.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Figures 5 and 7
Components that are the same as those in the figures are designated by the same reference numerals. In the figure, 10 is the same processor as in FIG. 5, CCl1. , a channel control device 12 and a main storage device 13. 31 is a control register provided in the input/output control device 30, and 32 is a microprocessor. 35 is a collision detection circuit provided in the input/output control device 30, which connects the processor 10 and the control reno star 3 from the input/output control device 30.
This is to detect that there is a conflict of access requests to 1. The output of the collision detection circuit 35 is used to stop the operation of the microprocessor 32. In other words, the output of the collision detection circuit 35 serves as a HALT signal to the microprocessor 32. 40 is an input/output device (10 devices) connected to the input/output control device 30.

[Operation] Register write request from the processor 10 side (actually a register write request from the channel control device] 2) and register write request from the input/output control device 30 (actually a register write request from the microprocessor 32) When it detects that there is a conflict, it gives a stop signal (HALT signal) to the microprocessor 32 to stop its operation.
Stir.

During this time, data is written to the control register 31 from the processor 10 side. Then, when data writing on the side of the computer 10 is completed, the collision detection circuit 35 releases the HALT signal applied to the microprocessor 32.

When the HALT state is released, the microprocessor 32 writes its own data into the control register 31. Therefore,
According to the present invention, writing of data to the control register 31 from the input/output control device 30 is reliably guaranteed, so a check operation after the write operation (checking whether data has been written) is no longer necessary. It is possible to efficiently process the conflicting requests for access to the control lane from the channel control device (processor) and the input/output control device.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing a configuration example of an input/output control device used in the present invention. Components that are the same as those in FIGS. 1 and 7 are designated by the same reference numerals. In the figure, numeral 31 is a control register that interfaces between the processor 10 and the input/output control device 30 according to control data written from the processor 10 (see FIG. 1 and FIG. 5) and the input/output control device 30. .

32 is a microprocessor that performs the overall control operation of the input/output control device 30; 33 is a microprocessor that handles register write requests from the channel control device 12 (see FIG. 5) and the input/output control device 3;
A CH that gives priority to a register write request from the channel control device 12 when register write requests from 0 conflict.
A C priority circuit, 34, transfers data from the channel controller 12 and the microprocessor 32 (i.e., input/output controller 3).
This is a selector that receives data from 0) and selects either one. The selector 34 is the CHC priority circuit 33
The output is received as a select signal.

A collision detection circuit 35 outputs a HALT signal to stop the operation of the microprocessor 32 in the input/output control device 30 when a register write request from the channel control device 12 and a register write request from the microprocessor 32 occur. The operation of the circuit configured as described above will be explained as follows.

First, a description will be given of the operation when there is no conflict between the register write request from the channel control device 12 and the register write request from the microprocessor 32. Now, CC
Let us consider a case where data is transferred from II (see FIG. 5) to a certain input/output device 40 and data is written.

In this case, the CCII writes the data length, the address on the main storage device 13 storing the data to be transferred, the direction of data transfer, etc. to the control register 31 of the input/output control device 30.

When the above information is written from the CC 11 to the control register 3, the CCII starts the input/output control device 30. When the input/output control device 30 receives an operation request from the ccll, it transfers data from the MM 13 according to the contents written in the control register 3]. In other words, MM1
3 pieces of data are read out and sent to the input/output device 4o. When the data transfer is completed, the input/output control device 30 writes predetermined data into the control register 3 and notifies the ccll of the end of the process. The completion notification of this process is performed, for example, by an interrupt. In other words, the microprocessor 32 updates the processor 1 every time the contents of the control register 31 are updated.
The 0 side is notified of this by an interrupt.

On the other hand, assume that there is a conflict between a register write request from the channel control device 12 and a register write request from the microprocessor 32. At this time, the CHC priority circuit 33 provides a select signal to the selector 34 to select the register write request from the channel control device]2 side. As a result, the control register 31 has the common bus 2o.
Data sent from the channel control device 12 side via the channel control device 12 is also written.

On the other hand, when the collision detection circuit 35 detects a conflict between the register write request from the channel control device 12 and the register write request from the microprocessor 32, it outputs an operation stop signal HALT to the microprocessor 32. As a result, no data is written to the control register 31 of the microprocessor 32. During this time, when data writing from the channel control device 12 to the control register 31 is completed, the conflict is canceled. When the conflict is resolved, the collision detection circuit 35 releases the operation stop signal HALT to the microprocessor 32.

When the microprocessor 32 is released from HALT, it writes its own data to the control register 31. As described above, according to the present invention, since it is reliably guaranteed that the microprocessor 32 is writing to the control register 31, there is no need for a check operation to check whether writing to the control register 31 has been performed. Therefore, processing when access requests to the control register from the channel control device and the input/output control device conflict can be efficiently performed.

FIG. 3 is a diagram showing a specific example of the collision detection circuit 35. G1 receives a register write request from the input/output control device 30 (specifically, from the microprocessor 32), and C
The NAND gates that receive the register write request from the HC (channel control unit) 12, G2 and 03, are two-man powered NAND gates, each output of which crosses over the input of the other to form an RS flip-flop. .

The output of G1 is input to the other input of G2, and the register write request ■ from the channel control device 12 is input to the other input of G3. Then, the output of G2 becomes the HALT signal ■. The operation of the circuit configured as described above will be explained below with reference to the time chart of FIG.

First, as shown in (a), a register write request is generated from the channel control device 12, and then the input/output control device 30
It is assumed that a register write request from . . . occurs as shown in (b). As a result, the output of Nant gate G2 is (
As shown in c), it rises from "0" to "1". This G2 output is input to the microprocessor 32 as a stop signal HALT, and while HALT is 1#, the microprocessor 32 stops its operation.

During this time, data from the channel control device 12 is written to the control register 31, and when the write operation is completed, the write request from the channel control device 12 falls to "0" as shown in (a). When this write request falls to “0”, the output of Nant gate G3 changes from “O” to “0”.
1”, and the output of Nant gate G2 falls from “1” to “0” as shown in (C). As a result, H
The ALT state is released and data is written from the microprocessor 32 to the control register 31.

[Effects of the Invention] As described above in detail, according to the present invention, when a register write request from a channel control device and a register write request from an input/output control device conflict, the microprocessor in the input/output control device By stopping the operation of the microprocessor, data is first written to the control register from the channel control device, and then when the data writing from the channel control device to the control register is completed, the HALT state of the microprocessor is released. By allowing data to be written from the output control device, it is guaranteed that the data is written to the control register from the input/output control device, so there is no need for a check operation after writing.
Processing when access requests to the control register from the channel control device and the input/output control device conflict can be efficiently performed.

[Brief explanation of the drawing]

Fig. 1 is a basic block diagram of the present invention, Fig. 2 is a block diagram showing a configuration example of an input/output control device used in the present invention, Fig. 3 is a diagram showing a specific example of a collision detection circuit, and Fig. 4 is a block diagram showing a configuration example of an input/output control device used in the present invention. Figure 3 is a Tinu chart showing the operation of each part of the circuit, Figure 5 is a block diagram showing an example of the configuration of a conventional system, Figure 6 is a diagram showing an example of the configuration of a control register, and Figure 7 is a diagram of an input/output control device. FIG. 2 is a block diagram showing an example of a conventional configuration. In FIG. 1, 10 is a processor, 20 is a common bus, 30 is an input/output control device, 31 is a control register, 32 is a microprocessor, 35 is a collision detection circuit, and 40 is an input/output device.

Claims (1)

[Claims] (1) In a system in which a processor (10) and a plurality of input/output control devices (30) are connected via a common bus (20), the input/output control device (30) is Interfaces between the processor (10) and the input/output control device (30) according to control data written from the processor (10) and the input/output control device (30) to a control register (31) provided in the control register (31), and controls input/output. A collision detection circuit (35) is provided in the device (30) to detect conflicting requests for access to the control register (31) from the processor (10) and the input/output control device (30), When conflicting access requests from the input/output control device (30) are detected,
From the collision detection circuit (35) to the input/output control device (30)
A common bus register control device characterized in that it is configured to output a stop signal (HALT signal) for stopping the operation of a microprocessor (32) within the common bus register. (2) When the writing of data from the processor (10) side to the control register (31) is completed while the operation of the microprocessor (32) is stopped, the microprocessor (32)
) is released from the HALT state, and the input/output control device (30
2. The common bus register control device according to claim 1, wherein data from the common bus register (31) is written to the control register (31).