JPH0358180B2 - - Google Patents

Info

Publication number
JPH0358180B2
JPH0358180B2 JP57117969A JP11796982A JPH0358180B2 JP H0358180 B2 JPH0358180 B2 JP H0358180B2 JP 57117969 A JP57117969 A JP 57117969A JP 11796982 A JP11796982 A JP 11796982A JP H0358180 B2 JPH0358180 B2 JP H0358180B2
Authority
JP
Japan
Prior art keywords
guard ring
surface portion
layer
conductivity type
ring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57117969A
Other languages
English (en)
Japanese (ja)
Other versions
JPS598353A (ja
Inventor
Takao Kamata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP11796982A priority Critical patent/JPS598353A/ja
Publication of JPS598353A publication Critical patent/JPS598353A/ja
Publication of JPH0358180B2 publication Critical patent/JPH0358180B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
JP11796982A 1982-07-07 1982-07-07 半導体集積回路装置 Granted JPS598353A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11796982A JPS598353A (ja) 1982-07-07 1982-07-07 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11796982A JPS598353A (ja) 1982-07-07 1982-07-07 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS598353A JPS598353A (ja) 1984-01-17
JPH0358180B2 true JPH0358180B2 (enrdf_load_stackoverflow) 1991-09-04

Family

ID=14724753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11796982A Granted JPS598353A (ja) 1982-07-07 1982-07-07 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS598353A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2016449C (en) * 1989-07-28 1996-06-25 Steven J. Hillenius Planar isolation technique for integrated circuits

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5226182A (en) * 1975-08-25 1977-02-26 Hitachi Ltd Manufacturing method of semi-conductor unit

Also Published As

Publication number Publication date
JPS598353A (ja) 1984-01-17

Similar Documents

Publication Publication Date Title
US4895810A (en) Iopographic pattern delineated power mosfet with profile tailored recessed source
US5019522A (en) Method of making topographic pattern delineated power MOSFET with profile tailored recessed source
CA1166760A (en) Self-aligned metal process for integrated circuit metallization
US5182234A (en) Profile tailored trench etch using a SF6 -O2 etching composition wherein both isotropic and anisotropic etching is achieved by varying the amount of oxygen
JPH0680724B2 (ja) 絶縁分離のcmos fet集積装置の製造方法
JPS6118147A (ja) 半導体デバイスの形成方法
US6821858B2 (en) Semiconductor devices and methods for manufacturing the same
JP2000332246A (ja) 自己整列トレンチを有するmosゲートデバイスを形成するプロセス
US5480816A (en) Method of fabricating a bipolar transistor having a link base
US5089434A (en) Mask surrogate semiconductor process employing dopant-opaque region
US5256583A (en) Mask surrogate semiconductor process with polysilicon gate protection
US20040209433A1 (en) Method for manufacturing and structure of semiconductor device with shallow trench collector contact region
JPH0358180B2 (enrdf_load_stackoverflow)
JPH0363210B2 (enrdf_load_stackoverflow)
JPS63227059A (ja) 半導体装置およびその製造方法
JPH0334656B2 (enrdf_load_stackoverflow)
JPH09139382A (ja) 半導体装置の製造方法
JPH07273183A (ja) 半導体装置とその製造方法
JPH01251669A (ja) 電界効果トランジスタの製造方法
KR0147255B1 (ko) Mosfet의 제조방법
JPH07283300A (ja) 半導体装置及びその製造方法
JPH0481339B2 (enrdf_load_stackoverflow)
JPH0235458B2 (enrdf_load_stackoverflow)
JPH01112770A (ja) 半導体装置の製造方法
JPH0334657B2 (enrdf_load_stackoverflow)