JPH0358158A - Data processor - Google Patents

Abstract

PURPOSE:To prevent overrun of preceding data to improve the processing efficiency by detecting whether the quantity of effective data stored in a data buffer is larger or smaller than a certain value to temporarily stop or restart data transfer through a channel device. CONSTITUTION:Each of channel devices 51 to 5m detects whether the quantity of effective data in the data buffer is larger or smaller than a certain value by a preceding data overrun detecting means; and when it is larger than the certain value, a control signal to temporarily stop data transfer is sent, and a peripheral device 7 stops data transfer, and a priority level changing means 9 changes the priority level of the channel device. When the quantity of effective data is smaller than the certain value, data transfer is restarted by the same procedures. Thus, overrun of preceding data is prevented and the processing efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is used in a data processing device that controls high-speed data transfer, and particularly relates to a data processing device that has an improved data transfer method during data overrun.

〔overview〕

The present invention provides a data processing device that processes data transfer between a main memory device and a peripheral device while prioritizing data transfer based on requests from a channel device, in which the amount of effective data stored in a data buffer in the channel device is By detecting whether the amount exceeds or falls below a certain level, it is possible to temporarily suspend or resume data transfer with the peripheral device via the channel device, thereby preventing overruns of preceding data and improving processing efficiency. This is what I did.

[Conventional technology]

Conventionally, as a data transfer method for a channel device in a data processing device that controls this type of high-speed data transfer, data is specified to a peripheral processing device, especially when connecting a device that controls a rotating body such as a disk. You must be conscious of transferring data within a certain time, and if data is not transferred within a certain time, it is assumed that the data did not arrive correctly or was not received (data overrun), and data overrun processing is performed. I had to. Overrun processing involves restarting processing from the beginning of an I/O instruction through software intervention, or restarting execution from the beginning of a currently executing command.

[Problem that the invention seeks to solve]

As mentioned above, when a data overrun occurs, a channel device in a conventional data processing device handles one I/O
This method has the disadvantage that overrun processing must be performed many times to execute an instruction, which not only increases the load on the software but also reduces the processing efficiency of the entire data transfer process. In addition, in recent years, there has been a rapid increase in the use of disk control devices having large-capacity caches, and large-capacity, high-speed transfers that do not require rotation or mechanical structures, such as electronic disks. Especially when there are such large transfers,
There is a drawback that overrun processing due to data overrun has a greater influence on the system.

An object of the present invention is to provide a data processing device that can prevent data overruns and improve processing efficiency by eliminating the above-mentioned drawbacks.

[Means for solving problems]

The present invention provides a data processing device that performs data transfer between a main storage device and a peripheral device, which includes a data transfer control unit that controls data transfer, and a plurality of channel devices including data buffers. The unit includes a priority change means for changing the priority of transfer data, and the channel device includes an enable instruction means for enabling interruption or resumption of data transfer with the peripheral device, and an enable instruction means for instructing the start of data transfer. a priority signal generating means for sending a priority signal to the priority changing means; and a preceding means for detecting that the amount of valid data in the data buffer is below or above a certain amount. Data overrun detection means, and transfer inhibition means for sending a control signal to the priority signal generation means and the peripheral device to temporarily inhibit data transfer with the peripheral device in response to the detection result of the overrun detection means. It is characterized by including.

[Effect]

The channel device uses a preceding data overrun detection means to detect whether the amount of valid data in the data buffer is above or below a certain amount, and if the amount exceeds a certain amount, the transfer inhibiting means temporarily suspends data transfer. Control signals are sent to peripheral devices and priority signal generation means. As a result, the peripheral device stops data transfer, and the priority signal generating means sends a priority signal to that effect to the priority changing means of the data transfer control section.

Thereby, the priority order changing means changes the priority order of the channel device. When the effective data amount falls below a certain amount, data transfer is resumed using the same procedure.

Therefore, overrun of preceding data can be prevented, and processing efficiency can be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a channel device according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a system using a data processing device according to an embodiment of the present invention.

According to FIG. 2, a data processing device 2 according to an embodiment of the present invention
The system using the system includes a system control device 1, a data processing device 2, an arithmetic control device 3, a peripheral control device 6, and a peripheral device 7, and the system control device 1 has signal lines 10, 11, and l5, respectively. is connected to the data processing device 2, the main storage device 4, and the arithmetic and control device 3, and the peripheral device 7
is connected to the peripheral control device 6 by a signal line 14, and the peripheral control device 6 is connected to the data processing device 2 by a signal line 13.

The data processing device 2 is connected to the system control device 1 by a signal line 10, and includes a data transfer control section 8 that includes a priority order changing means 9 that changes the priority order of transfer data according to a request from each channel device. , this data transfer control unit 8 is connected to signal lines 12 . A plurality of n channel devices (CH) connected by ~12, 5. ~5o. Peripheral devices are connected to each channel device 5, to 5o through a peripheral device, but the components other than channel device 5 are omitted in the figure to make the figure complicated.

According to FIG. 1, the channel device 51 includes a channel control section 20, a buffer control section 21, a data buffer 22, a transfer starting means 23, a transfer control section 24, an I/O interface control section 25, registers 26, 27, 3l, and 32, selectors 28 and 38, comparison circuit 29, AND circuit 30
, a receiver 33, a driver 34, and a flip-flop 39. The channel control unit 20 further includes flip-flops (FF) 35 and 40, a data chain flag register (CD) 36, and an input/
It includes a flag register (IN/OUT) 37 for output.

The data transfer control unit 8 includes signals 50, 5L52,
53 and 85, and to the peripheral control device 6 by signals 67, 76, 79, 80, 81, and 82, and within the device by signals 54 to 84, respectively.

Here, the feature of the present invention is that a priority change means 9 is provided in the data transfer control section 8, and the channel device 5.
A flip-flop 35 as a valid indicating means for validating the interruption or resumption of data with the peripheral device 7 within ~5h.
and transfer start instruction means 23 for instructing the start of data transfer.
, a flip-flop 40 for high priority request as a priority signal generating means for sending a signal 85 indicating a high priority to the priority changing means 9, and a data buffer 2.
As a preceding data opalun detection means for detecting that the amount of effective data within 2 has become less than or more than a certain amount,
Registers 26, 27, selector 28, comparison circuit 29, flip-flop 39, and signal 67 as a control signal that temporarily inhibits data transfer with peripheral device 6 in response to detection result signal 84 output from flip-flop 39;
This is because an AND circuit 30 is provided as a transfer inhibiting means for transmitting the data to the flip-flop 40 and the peripheral device 6.

Next, the operation of this embodiment will be explained separately (a) at the time of interruption/resumption and (b) at the time of output.

(a) When suspending/resuming, in this case, the flip-flop 35 for enabling suspend/resume
It works like this:

For data transfer, a signal 53 is sent from the data transfer control unit 8 to set a flag circuit (IN/OUT) 37 for manual input/output instruction, a flag circuit (CD) 36 for chain data flag, and a flip-flop 35 for enabling interruption/resumption. The process is started by providing the transfer byte count as a signal 63 to the transfer control unit 24.

Note that, at this point, the flip-flop 40 for high priority requests is set to a logical value of "0". Further, registers 26 and 27 are given the amount of data in the buffer for which preceding data overrun should be detected at the time of input or output. It is selected by the signal 59 outputted from the comparator circuit 37 and inputted as the signal 64 to one input of the comparator circuit 29 . A signal 65 indicating the data valid buffer amount from the buffer control unit 2l is input to the other input of the comparison circuit 29 and compared. The signal 66 output from the comparison circuit 29 is used as a set signal for the flip-flop 39, and the signal 84 output from the flip-flop 39 is used as the signal 6 output from the flag register 36 for the chain data flag.
0 and the signal 61 output from the flip-flop 35
The signal 67 is also input to the AND circuit 30, and a signal 67 as a data transfer temporary inhibition signal is sent to the peripheral control device 6.

Further, a signal 71 output from the transfer start instructing means 23 is input to the reset terminal of the flip-flop 39.

The buffer control section 21 is connected to the data transfer control section 8 via a signal 52, and controls data transfer with the data transfer control section 8. The data is stored in the data buffer 22 via the selector 38 as a signal 50. When more than n bytes of data accumulate in the data buffer 22, the buffer control unit 2l sets the output signal 70 to a logical value "l". When the transfer start instructing means 23 receives this signal 70, it sends a signal 71 with a logic value of "1" to the transfer control unit 24, and also sets a signal 83 for enabling the comparison circuit 29 to a logic value of "1". Transfer control unit 2
4 receives this signal 71, outputs a signal 78 to the data out register 32, sets the reception of the signal 73 which is data from the data buffer 22, and transfers the data with the peripheral control device 6. Start.

Data is transferred to the peripheral control device 6 to reduce the byte count and increase the counter on the transfer side. This signal 80 is sent to the buffer control unit 21 by a signal 69 and is used to determine the amount of effective data in the buffer.

(b) At the time of output, the flip-flop 35 for enabling suspend/resume has a logic value of "1".
”, the flag register 36 for data chain has the logical value “
1" and the flag register 37 for input/output instruction has a logical value of "1", that is, when outputting, the byte count register 27 for detecting a preceding data overrun contains, for example, "
4'' is set, a transfer byte count is set in the byte count register 26, and transfer is started.

More than n bytes are stored in the data buffer 22, and the signal 7
0 becomes the logical value "1", and the signal 71 output from the transfer start instructing means 23 becomes the logical value "1", and the signal 8
3 is also set to logical value "1". The transfer control unit 24 starts data transfer with the I/O interface. Normally, the data buffer 22 is always full because the memory system has a larger transfer capacity, but the data buffer 22 is always full.
Memory requests may be forced to wait due to main memory contention with the main memory, resulting in data delays. When such a state occurs, data from the data transfer control unit 8 stops coming in, and the amount of effective data in the data buffer 22 decreases. The signal 65 from the buffer control unit 21 has a logical value of "4"
When the comparison circuit 29 finds a match and generates a signal 66 with a logical value of "1", the flip-flop 39
is set to logical value "1".

Then, the condition of the AND circuit 30 is determined by the signal 84 output from the flip-flop 39, and a signal 67 is sent to the peripheral control device 6 to temporarily inhibit the data transfer of the logical value "1". When the peripheral control device 6 detects this signal 67,
The transfer request signal from the peripheral control device 6 side is temporarily interrupted.

Further, when the signal 67 becomes a logical value "1", the flip-flop 40 for high priority requests becomes a logical value "1", and the data transfer request from the next channel device to the data transfer control unit 8 is changed to a high priority request. The signal 85 becomes a logic value "1" and goes out. When this signal 85 becomes a logical value "L" and is requested, the priority change means 9 in the data transfer control section 8
The channel device is recognized by the channel device and its priority level is increased.

In addition, when more than n bytes of data are accumulated, the transfer start instruction means 2
The signal 71 from 3 becomes the logical value "1" and resets the flip-flop 39. The output signal 84 becomes a logic value "0" and the signal 67 for temporarily inhibiting data transfer becomes a logic value "0" and data transfer is restarted again.

〔Effect of the invention〕

As described above, the present invention provides a means for enabling interruption or resumption of data transfer of an I/O interface, a means for instructing the start of data transfer, and a means for instructing the start of data transfer. preceding data overrun detection means for detecting that the above has occurred; means for generating a signal for temporarily inhibiting transfer of the I/O interface;
By including means for generating a priority signal, data transfer can be temporarily interrupted and resumed, and data transfer can be continued without causing a data overrun and without retrying ■/○ instructions, improving processing efficiency. There is an effect that can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a channel device according to an embodiment of the present invention. FIG. 2 is a block diagram showing an example of a system using an embodiment of the present invention. 1... System control device, 2... Data processing device,
3... Arithmetic control unit, 4... Main storage device, 5, 5
■, 5h-1, '5n... Channel device, 6... Peripheral control device, 7... Peripheral device, 8... Data transfer control unit, 9... Priority change means, 10, l1 , 121
~12. , 13-l5...Signal line, 20...Channel control section, 21...Buffer control section, 22...Data buffer, 23...Transfer start instruction means, 24...
Transfer control unit, 25...I/O interface control unit,
26, 27, 31, 32... register, 28, 38...
...Selector, 29...Comparison circuit, 30...AND circuit, 33...Receiver, 34...Driver, 3
5, 39, 40...Flip-flop (FF), 36
...Flag register (CD) 37...Flag register (IN/OUT), 50-85...Signal.

Claims (1)

[Scope of Claims] 1. A data processing device that transfers data between a main storage device and a peripheral device, which includes a data transfer control unit that controls data transfer, and a plurality of channel devices including data buffers, The data transfer control unit includes a priority change unit that changes the priority of transfer data, and the channel device includes an enable instruction unit that enables interruption or resumption of data transfer with the peripheral device, and a data transfer control unit that changes the priority of transfer data. transfer start instructing means for instructing the start of transfer; priority signal generating means for sending a priority signal to the priority changing means; a preceding data overrun detection means for detecting the overrun detection means; and, corresponding to the detection result of the overrun detection means, sending a control signal for temporarily inhibiting data transfer with the peripheral device to the priority signal generation means and the peripheral device; A data processing device comprising a transfer inhibiting means.