JPH03266158A - Channel device - Google Patents

Abstract

PURPOSE:To carry on data transfer by inhibiting data transfer temporarily when the amount of effective data on a data buffer reaches the amount of data whose overrun is to be detected and restarting the data transfer when the amount of data reaches the amt. of data when the data transfer is restarted. CONSTITUTION:When the amount of effective buffer data on the data buffer 22 becomes equal to the amount of data whose overrun is to be detected after the effectiveness of a data transfer interruption/restart function is indicated, a signal which inhibits the data transfer temporarily is outputted to a peripheral controller 6 and when the amount of effective data on the data buffer 22 reaches the amount of data at the restart of the transfer, the restart of the data transfer is enabled. Consequently, no data overrun is caused and the data transfer can be carried on without retrying an I/O instruction.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a channel device.

[Conventional technology]

With conventional channel devices, especially when connecting a device that controls a rotating body such as a disk, it is necessary to be conscious of transferring data to the peripheral processing device within a specified time. If no data is transferred,
Either the data did not arrive correctly or was not received (data overrun), and the data overrun had to be processed. Overrun processing means that software intervenes to restart processing from the beginning of the I10 instruction, or to restart execution from the beginning of the currently executing command.

[Problem to be solved by the invention]

In the conventional channel device described above, when a data overrun occurs, the overrun process must be performed many times to execute the ll10 instruction, which not only increases the load on the software but also reduces the performance of the entire data transfer process. There was a drawback. In addition, in recent years, there has been a rapid increase in the use of large-capacity caches in disk control devices, and large-capacity, high-speed transfers that do not require rotation or mechanics, such as electronic disks. In this case, there is a drawback that overrun processing due to data overrun in particular has a large influence on the system.

It is an object of the present invention to provide a channel device that does not cause data overruns and therefore can continue data transfers without retrying I10 instructions.

[Means to solve the problem]

The channel device of the present invention includes an interrupt/resume enable flip-flop that indicates whether the interrupt/resume function of data transfer is enabled or disabled based on an instruction from the transfer control device, and a flip-flop that allows the interrupt/resume function to be set/resumed according to data input/output by the transfer control device. an input/output instruction flag to be reset; first and second registers to which the amount of data in the data buffer is given by the transfer control device to detect preceding data overrun at the time of data input and output, respectively; and the transfer control device. The third and fourth registers are given the amount of data when data transfer is restarted during data input and output, respectively, and the output of the first register or the second register is selected according to the input/output instruction flag. a first selector; a second selector that selects the output of the third register or the fourth register according to the input/output instruction flag; a flip-flop tube; the output of the first selector and the effective data buffer amount. The first comparator circuit sets a flip-flop when they match, and the interrupt/resume enable flip-flop interrupts/resumes data transfer.
An AND gate that outputs a signal to the peripheral control device that indicates the restart function is enabled and temporarily inhibits data transfer when the flip-flop is set, and a second AND gate that is enabled when the flip-flop is set. The second selector output and the effective data buffer amount are compared, and if they match, the second flip-flop is reset.
and a comparison circuit that compares the effective data buffer amount with the first and second comparison circuits.
a buffer control section that outputs a detection signal when a predetermined number of bytes or more of data is accumulated in the data buffer; and transfer start instructing means for outputting a transfer start instructing signal, and transferring data between the peripheral control device and the data buffer according to the transfer start instructing signal,
and a data transfer control unit that reduces the byte count set by the transfer control device.

[Effect] After the data transfer interrupt/resume function is enabled, when the effective data buffer amount in the data buffer becomes equal to the data amount for which data overrun should be detected, a signal to temporarily inhibit data transfer is sent to the peripheral control device. When the amount of valid data in the data buffer becomes equal to the amount of data at the time of restarting the transfer, it is possible to restart the data transfer, so data overrun does not occur, and therefore the data can be transferred without retrying the work/○ instruction. can continue.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a system configuration diagram showing an embodiment of the present invention.

The transfer control device 2 is connected to the system control device l via the signal line 10.
and each signal line 1 is connected to the system control device 1.
1.15, the main storage device 4 and the arithmetic and control device 3 are connected. Each transfer control device 2 has a signal line 12. ．．
122. ...,' 12 n-+.

Channel device 58.5□,...+51 by 1211
'l-15n is connected, a peripheral control device 6 is connected to the channel device 5□ by a signal line 13, and a peripheral control installation 6
A peripheral device 7 is connected to the peripheral device 7 by a signal line 14 . Channel 5. transfers data between the main storage device 4 and the peripheral device 7.

FIG. 1 is a diagram showing the configuration of the channel device 5I.

The channel 51 includes a channel control section 2o and a buffer control section 2.
1, data buffer 22, transfer start instruction means 23, data transfer control section 24, I10 interface control section 25,
Registers 26, 27゜28.29, data out register 37, data in register 36, driver 39, receiver 38, selectors 30, 31, comparison circuit 32゜3
3. Flip-flop 34, AND circuit 35, input/output instruction flag 42, interrupt/resume enable flip-flop 4
1, and the transfer control device 2 consists of signal lines 50, 51,
It is connected to the peripheral control device 6 through signal lines 77.82, 83.84, and 85.86. In addition, each part in the channel has signal lines 54, 55° 56.57, 58, 59, 60, 61, 62° 63.6
4,65,66.67.68,69°70.71,72
, 73.74, 75.76°, 78.79, and 80.81, and data transfer is performed while providing information between each control unit. A startup instruction for the peripheral control device 6 is input to the channel control section 2o through the signal line 53, and is given to the I10 interface control section 25 through the input/output signal line 63. The I10 interface control unit 25 receives the signal on the input/output signal line 63 to activate the peripheral control device 6 via the signal line 85. In addition, the I10 interface control unit 25 connects a control line 85 to the peripheral control device 6.
．． 86 and signal lines 83 and 84 to exchange data with the peripheral control device 6 to prepare for data transfer. Data transfer is performed by setting the input/output instruction flag 42 and interrupt/resume enable flip-flop 41 from the transfer control device 2 through the signal line 53, and transmitting the transfer byte count to the data transfer control section 24 through the channel control section 20 via the signal line 64. It begins by giving. Also, register 2
6.27 gives the amount of data in the data buffer 22 for which preceding data overrun at the time of input/output should be detected,
Registers 28 and 29 are given the amount of data when restarting transfer during input/output. Here, input/output instruction flag 4
2 is "O" when data is transferred (input) from the peripheral device 7 to the main storage device 4, and becomes "1" when data is transferred (output) from the main storage device 4 to the peripheral device 7. The interrupt/resume enable flip-flop 41 is set to "1" when the data transfer interrupt/resume function is enabled, and set to "0" when disabled.

"Amount of data in the data buffer for which advance data overrun should be detected" is the amount of data that is transferred from when a transfer interruption instruction is issued until it is interrupted (a value that does not cause an overflow), and "the amount of data when the transfer is restarted." is the amount of data that can be used to resume interrupted data transfer. Therefore, when transferring output data, the amount of data to be stored in the data buffer to detect the preceding data overrun is the amount of data when the transfer is restarted.

At the time of input data transfer, the amount of data in the data buffer for which preceding data overrun should be detected is greater than the amount of data at which data is to be resumed. Output signals 57 and 58 of registers 26 and 27 are input to selector 30, selected by output signal 59 of input/output instruction flag register 42, and input as one input signal 65 of comparator circuit 32. A signal 67 indicating the data valid buffer amount (n bytes) from the buffer control unit 21 is input to the other input of the comparison circuit 32 and compared. The output signal 75 of the comparator circuit 32 is sent to the flip-flop 3.
4 is used as the set signal, and the output signal 76 is used as the interrupt/
A signal 77 that is input to the AND circuit 35 together with the output signal 62 of the restart enable flip-flop 41 and temporarily inhibits data transfer is sent to the peripheral control device 6, and the transfer control device 2
This signal is sent as a signal to increase the request priority of this channel. Further, the signal 76 is used as a valid signal for the comparison circuit 33. Output signal 6 of register 2829
0.61 is input to the selector 31 and selected by the selection signal 59, and is input as one input signal 66 of the comparison circuit 33. The other input of the comparator circuit 33 receives a signal 67 from the buffer control unit 21 indicating the data valid buffer amount.
are input and compared. The output signal 74 of the comparison circuit 33 is used as a reset signal for the flip-flop 34. Data is stored in data buffer 22 through selector 40 via signal 50. Here, data is written from the peripheral control device 6 to the data buffer 22 in 1-byte units, and from the transfer control device 2 to the data buffer 22.
Data writing to 2 is performed in units of 4 bytes. When n bytes or more of data accumulate in the data buffer 22, the buffer control unit 21 sets the signal line 69 to a logical value "1". Upon receiving this signal, the transfer start instructing means 23 sends a signal 72 with a logical value of "1" to the data transfer control section 24 and also sends the signal 72 to the comparison circuit 3.
The enable signal 73 that makes the signal 2 valid is set to the logic value "1". Upon receiving this signal, the data transfer control section 24 sets the data 71 from the data buffer 22 in the data out register 37 and starts data transfer with the peripheral control device 6. The data in the data out register 37 is transferred to the signal line 81.
The signal is sent to the driver 39 via the signal line 82 and sent to the peripheral control device 6 via the signal line 82. The data transfer control unit 24 transfers data with the peripheral control device 6 by exchanging signals 83 and 84, decreases the byte count, and increases the counter on the transfer side. This signal is sent to the buffer control unit 21 via the signal line 68 and is used to determine the amount of effective data in the data buffer 22. Inside the buffer control unit 21, there is a memory pointer that controls the start address from/to the memory to the data buffer 22, and a PSI pointer that controls the read/write address of the data buffer 22 to be transferred to the PSI interface side. The effective amount of data in the data buffer 22 is determined using both pointers.

Here, the data transfer operation at the time of output will be explained.

The interrupt/resume enable flip-flop 41 has a logic value of “1”,
When the input/output instruction flag 42 has a logical value of "1", that is, when it is output, the byte count register 27 for preceding data overrun detection is set to, for example, "8", and the register 2
9 is set to "16", a transfer byte count is set in the byte count register in the data transfer control unit 24, and the transfer is started. 1 to data buffer 22
When 6 bytes or more are stored, the signal 69 becomes a logical value "1" and the output signal 72 of the transfer start instruction means 23 becomes a logical value "1".
At the same time, the signal 73 is also set to the logic value "1". The data transfer control unit 24 starts data transfer with the I10 interface. Normally, the data buffer 22 is always full because the memory system has a larger transfer capacity, but there are cases where the memory request is kept waiting due to requests from other channels or main storage contention with the arithmetic control unit 3, and the data is delayed. Occur.

When such a state occurs, no more data is transferred to the transfer control device 2, and the amount of valid data in the data buffer 22 decreases. When the signal 67 from the buffer control unit 21 displays the logical value "8", a match is determined by the comparison circuit 32, and when the signal 75 with the logical value "1" is generated,
Flip-flop 34 is set to logic "1".

The condition of the AND circuit 35 is taken by the output signal 76 with a logic value of "1", and the data transfer-time inhibit signal 7 with a logic value of "1" is set.
7 is sent to the peripheral control device 6. Further, a signal 76 having a logical value of "1" is given as a valid signal to the comparator circuit 33.

When the peripheral control device 6 detects this signal, the peripheral control device 6
The transfer request signal from is temporarily interrupted. Further, when the signal 67 indicating the effective data buffer amount from the buffer control unit 21 indicates "16", the comparator circuit 33 finds a match, and a match signal 74 having a logical value of "1" is generated. Main signal 74
resets the flip-flop 34. Output signal 76
becomes the logical value "0" and the condition of the AND circuit 35 collapses,
The data transfer-time inhibit signal 77 becomes a logical value "0", and the data transfer is restarted again.

[Effects of the Invention] As explained above, the present invention outputs a signal that temporarily inhibits data transfer when the amount of valid data in the data buffer reaches the amount of data that should be used to detect a data overrun, and when data transfer is resumed. By making it possible to restart data transfer when the amount of data reaches , it is possible to continue data transfer without causing a data overrun and without retrying the I10 instruction.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a channel device according to an embodiment of the present invention, and FIG. 2 is a system configuration diagram. 1... System control device, 2... Transfer control device, 3
... Arithmetic control unit, 4... Main storage device, 51
~5o...channel, 6...peripheral control device, 7...
- Peripheral device, 20... Channel control unit, 21.
...Buffer control unit, 22...Data buffer, 23
...Transfer start instruction means, 24...Data transfer control unit, 25...I10 interface control unit, 26.27,
28, 29, 36. 37...Register, 38...Receiver-39...Driver 41...
Suspension/resume valid flip-flop, 42... Input/output instruction flag, 35... AND circuit, 32.33... Comparison circuit, 30.31... Selector, 34... Flip-flop.

Claims (1)

[Claims] 1. In the channel device, an interrupt/resume enable flip-flop that displays whether the interrupt/resume function of data transfer is enabled or disabled according to instructions from the transfer control device; and data input/output by the transfer control device. an input/output instruction flag that is set/reset according to the input/output instruction flag, and first and second registers to which the amount of data in the data buffer is given by the transfer control device to detect preceding data overrun at the time of data input and output, respectively. and third and fourth registers to which the transfer control device gives the amount of data when data transfer is restarted during data input and output, respectively, and a first register or a second register depending on the input/output instruction flag. a first selector that selects the output of the first selector, a second selector that selects the output of the third register or the fourth register according to the input/output instruction flag, a flip-flop, and the output of the first selector. The first comparator circuit compares the effective data buffer amount and sets a flip-flop when they match, and the interrupt/resume enable flip-flop interrupts/resumes data transfer.
An AND gate that outputs a signal to the peripheral control device that indicates the restart function is enabled and temporarily inhibits data transfer when the flip-flop is set, and a second AND gate that is enabled when the flip-flop is set. The second selector output and the effective data buffer amount are compared, and if they match, the second flip-flop is reset.
a comparison circuit; a buffer control unit that outputs the effective data buffer amount to the first and second comparison circuits and outputs a detection signal when a predetermined number of bytes or more of data is accumulated in the data buffer; When the detection signal is output from the controller, the first comparison circuit is enabled, and a transfer start instruction means outputs a transfer start instruction signal, and the transfer start instruction signal causes data transfer between the peripheral control device and the data buffer. 1. A channel device comprising: a data transfer control unit that performs data transfer and reduces a byte count set by a transfer control device.