JPH0635834A - Channel device - Google Patents

Abstract

PURPOSE:To prevent the occurrence of the overrun of data and also to prevent the overrun processing of software from affecting a system in regard to the data transfer control of a channel device. CONSTITUTION:An interruption restart validating flip-flop 37 is provided to validate the restart of the interrupted transfer of data of an I/O interface together with a comparator 32 which instructs of the start of the transfer of data, a comparator 31 which detects the advanced overrun of data, a flip-flop 39 which carries up the data transfer request priority, and an AND circuit 40 which temporarily suppresses the transfer of data of the I/O interface. In such a constitution, the temporary interruption of transfer of data can be restarted and the overrun of data is never caused. Furthermore, the transfer of data can be carried on with no retrial of an I/O instruction carried out by a peripheral controller and with no overrun processing carried out by software.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel device, and more particularly to a channel device for performing high speed data transfer with an electronic disk, a magnetic disk or the like.

[0002]

2. Description of the Related Art Conventionally, a channel device for controlling high-speed data transfer of this type is aware that data is transferred to a peripheral processing device within a prescribed time period, and data is transferred within a predetermined time period. If the data was not transferred, it was determined that the data did not arrive correctly or was not received (data overrun), and the data overrun had to be processed. The overrun process is mediated by software so that the process is restarted from the beginning of the channel program currently being executed, or the execution is restarted from the beginning of the command being executed.

[0003]

In the above-described conventional channel device, when a data overrun occurs, the overrun process must be performed by the number of data overrun occurrences, which not only increases the load on software, but also
There is a problem that the performance of the entire data transfer process is also reduced. Particularly, in recent years, when a large-capacity cache is installed in a disk control device or large-capacity / high-speed transfer that does not involve rotation and mechanical (mechanical) like electronic disks is rapidly increasing, overrun processing due to data overrun is performed in the system. Will have a greater effect on.

[0004]

The device of the present invention is a channel device in a data processing device for controlling high-speed data transfer between a main memory device and a peripheral device in accordance with a priority of the channel device according to a request from the channel device. , I /
A suspend / resume enable flip-flop that enables suspend / resume of the O interface data transfer, a means for detecting that valid data in the data buffer has reached a predetermined n byte, and instructing the start of data transfer, and a predetermined m byte. When the overrun flip-flop is set, the preceding data overrun flip-flop that is set when the overrun flip-flop is set, means for raising the request priority from the channel while the overrun flip-flop is set, and the transfer of the I / O interface Is provided with a means for temporarily suppressing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a channel device showing a first embodiment of the present invention. This channel device includes a channel controller 20, a buffer controller 21, a data buffer 22, a transfer controller 23, and an I / O interface controller 2.
4, 6 registers 25, 26, 27, 28, 29, 3
3, 34, three selectors 27, 30, 41, two comparison circuits 31, 32, a driver 36, a receiver 35,
Suspend / Resume Effective Plip-Flop 37, INPUT / OU
TPUT instruction flag 38, flip-flop 39, AN
The D circuit 40 is used.

The transfer control device 2 (shown in FIG. 4) is connected through five signal lines 50, 51, 52, 53 and 81, and the peripheral control device 6 (shown in FIG. 4) is connected to the signal line 6.
Are connected through all 73, 76, 77, 82, 84, 85. In the channel device, signal lines 54, 55, 5
6,57,58,59,60,61,62,63,6
4,65,66,67,68,69,70,71,7
2, 74, 75, 78, 79, 80 are connected, and data transfer is performed while giving information between the respective control units. Note that the above signal lines may be referred to as signals for the sake of description.

FIG. 4 is a diagram showing the configuration of an information processing system to which the present invention is applied. The transfer control device 2 is connected to the system control device 1 by a signal line 10. The system control device 1 is connected to the main storage device 4 via a signal line 11 and to the arithmetic and control unit 3 via a signal line 15. Further, the transfer control device 2 includes channel devices 5 ₁ , 5 ₂ ... 5 _n-1 , 5
_n is connected to the signal lines 12 ₁ , 12 ₂ ... 12 _n-1 , 12 _n , the channel device 5 ₁ is connected to the peripheral controller 6 via the signal line 13, and is connected to the main storage device 4. The data of is exchanged. The peripheral control device 6 is connected to the peripheral device 7 via a signal line 14.

Now, the interruption / resumption effective flip-flop 37
Data transfer when a means for raising the request priority from the channel device is used will be described. Transfer control device 2
Via the signal line 53, the INP in the channel control unit 20
A UT / OUTPUT instruction flag 38 and an interruption / resumption valid flip-flop 37 are set, and the transfer control unit 23 is also set.
The transfer byte count is provided through signal 62 to prepare the data transfer to begin.

Registers 28 and 29 have INPUT / OU
The data amount of the buffer to be instructed to start the transfer at the time of TOPUT is given and the selector 30 receives the output signals 65 and 66 of the registers 28 and 29. Register 25,
The data amount of the buffer for detecting the preceding data overrun at the time of INPUT / OUTPUT is given to 26, and the output signals 57, 58 of the registers 25, 26 are inputted to the sector 27.

The selectors 27 and 30 select respective input signals by using the output signal 59 of the INPUT / OUTPUT instruction flag register 38 as a select signal,
One of the input signals 63 and 6 of the comparison circuits 31 and 32, respectively.
Give as 7. Further, a signal 64 indicating the data effective buffer amount from the buffer control circuit 21 is applied to one input in common to the comparison circuits 31 and 32.

The output signal 78 of the comparison circuit 32 is supplied to the transfer control section 23 as a transfer start signal and to the flip-flop 39 as a reset signal. In addition, the comparison circuit 31
Is validated by an output signal 79 from the transfer control unit 23, and its output signal 80 is used as a set signal by the flip-flop 39. The output signal 81 of the flip-flop 39 is input to the AND circuit 40 together with the output signal 60 of the suspend / restart valid flip-flop 37, and the data transfer temporary inhibition signal 82 which is the output thereof is sent to the peripheral control device 6. The output signal 81 is also given to the transfer control device 2 as a request signal for raising the priority of data transfer.

The buffer controller 21 is connected to the transfer controller 2 via a signal line 52 and controls data transfer with the transfer controller 2. The buffer controller 21 controls the data storage position / read position of the buffer 22 by the signal line 54 and is initialized by the signal 55 from the channel controller 20. The transfer control unit 23 and the signal 68 control each other.

The data is stored in the buffer 22 via the signal line 50 and the selector 41. The empty condition of the data in the buffer 22 and the effective data amount of the buffer 22 are compared by the signal line 64 through the buffer control unit 21 to the comparison circuits 31, 32.
Given to. Here, the input signals 67 and 6 of the comparison 32 are
When a match of 4 is obtained, the output signal 78 of the logical value "1" becomes valid and is given to the transfer control unit 23. Transfer control unit 2
3 sets the valid signal 79 to the comparator 31 to the logical value "1".
By receiving the signal 78 of the register 34, in the case of output transfer, the output signal 75 from the transfer control unit 23 causes the register 34
Then, the data 70 is received from the buffer 22 and set, is input to the driver 36 as a signal 72, and is output to the bus 73 as output data. The data 73 is transferred to and from the peripheral control device 6 by leaning the signals 76 and 77 in the transfer controller 23. At this time, the transfer control unit 23 also controls the transfer byte count.
Count up on the transfer side.

In the case of input transfer, it is input to the receiver 35 through the bus 73. Output signal 7 of receiver 35
1 is input to the register 33 and held by the set signal 74. The output signal 69 of the register 33 is input to one of the selectors 41 and set in the buffer 22 as input data.

The I / O interface controller 24 is controlled by the signal 61 from the channel controller 20 and the signal 83 from the transfer controller 23, and the peripheral controller 6 and the signal 8 are controlled.
4, 85 controls the start and end. Here, an example of data transfer at the time of output transfer will be described.

When the interruption / restart valid flip-flop 37 has the logical value "1", and the flip-flop 39 has the logical value "1", that is, at the time of OUTPUT, for example, "16" is set in the transfer start byte count register 29, and the preceding data is set. "4" is set in the register 26 for overrun detection, the transfer byte count is set in the byte count register in the transfer control unit 23, and data transfer is started. Data is stored in the buffer 22 through the data line 50 and the control signal line 54.

The amount of data stored in the buffer 22 is input to the comparison circuits 31 and 32 by the signal 64 from the buffer controller 21. When the signal 64 indicates "16", the register 29
"16" of output signal 67 through selector 30 from
Then, the comparison circuit 32 generates an output signal 78 having a logical value of "1" which is input to the transfer control circuit 23 and resets the flip-flop 39. Upon receiving the signal 78, the transfer control unit 23 generates the signal 75, loads the data 70 of the buffer 22 into the register 34, and at the same time,
Data transfer signals 76, 7 on the I / O interface
Execute by 7.

Normally, since the memory system has a larger transfer capacity, the buffer 22 is always full, but the memory request has a request from another channel device or a competition of the main storage device 4 with the arithmetic and control unit 3. Then, the data may be delayed.

When such a state occurs, the transfer control device 2
No more data will come in, and the amount of valid data in the buffer 22 will decrease. Signal 6 of buffer control unit 21
When 4 indicates the logical value "4", the comparison circuit 31 makes a match and generates the signal 80 of the logical value "1". Signal 80
This sets the flip-flop 39 to the logical value "1". The condition of the AND circuit 40 is satisfied by the output signal 81, and the data transfer temporary inhibition signal 82 having the logical value “1” is sent to the peripheral control device 6. When the peripheral controller 6 detects this signal, the transfer request signal from the peripheral controller 6 is suspended.

The signal 81 having the logical value "1" is given to the transfer control device 2 as a data transfer request priority signal. With this signal, it is possible to raise the priority level over the conventional channel priority. Further, when the data has accumulated more than "16" bytes, the output signal 78 for instructing the start of the transfer of the comparison circuit 32 becomes the logical value "1" and the flip prop 39 is reset. The output signal 81 becomes the logical value "0", the data transfer temporary inhibition signal 82 becomes the logical value "0", and the data transfer is restarted.

FIG. 2 shows a second embodiment of the present invention.

In this embodiment, a flip-flop 41 is provided as compared with the first embodiment.

The present flip-flop 41 is set at the same time as the flip-flop 39 set by the signal 80 which becomes valid when the valid data described in the first embodiment becomes m bytes, and the present data transfer sequence ends. Hold that state until you do. Then, the next start-up is reset by receiving the signal 86 from the channel controller 20.

For this reason, the signal 87 for raising the priority of the data transfer request, when the preceding data overrun is detected once, is processed in the high priority until the end of the data transfer sequence. It will also be reduced and may improve performance for the system.

FIG. 3 shows a third embodiment of the present invention. In this embodiment, a counter 42, a flip-flop 42 and an AND circuit 44 are added to the first embodiment.

The counter is cleared by the start signal 86 and is incremented each time the preceding data overrun is detected. The flip-flop 42 is set when the counter reaches 1, and is cleared by the start signal 86 to raise the priority of the data request. Further, the AND circuit 44 is
When the counter 42 reaches (l + 1), the logical value "1"
become.

When the counter 42 reaches 1, the flip-flop 43 is set to "1" by the signal 88 which becomes the logical value "1" and the signal 87 for raising the priority of the data request is sent to the transfer control device 2. As a result, efficient and high transfer can be realized.

After the flip-flop 43 is set, when the preceding data overrun is generated again, the counter 42 is incremented by "1" and the signal 89 becomes the logical value "1", the output signal 90 of the AND circuit 44 is output. A logical value of "1" is input to the channel control unit 20 and the transfer control unit 23, and a data overrun is reported to software, so that a channel device that provides stable system performance can be provided.

[0030]

As described above, according to the present invention, the data transfer of the I / O interface is detected by detecting the fact that the valid data in the data buffer has become n bytes and the prep-flop which enables the interruption and resumption of the data transfer. A means for instructing the start, a preceding data overrun flip-flop that is set when the number of bytes becomes m, and reset when the number of bytes becomes n, and a means of increasing the request priority from the channel while the overrun flip-flop is set. , I /
By adding a means for temporarily suppressing the transfer of the O interface, it is possible to temporarily suspend and resume the data transfer, prevent the data overrun from occurring, and perform the I / O by the peripheral control device.
There is an effect that the data transfer can be continued without retrying the O instruction or overrun processing by software.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a third embodiment of the present invention.

FIG. 4 is a block diagram of an information processing system to which the present invention is applied.

[Explanation of symbols]

1 System control device 2 Transfer control device 3 Arithmetic control device 4 Red memory device 5 ₁ , 5 ₂ , ... 5 _n-1 , 5 _n channel device 6 Peripheral control device 7 Peripheral device 20 Channel control unit 21 Buffer control unit 22 Buffer 23 Transfer Control Unit 24 I / O Interface Control Unit 25, 26, 28, 29, 33, 34 Register 27, 30, 41 Selector 35 Receiver 36 Driver 37 Suspend / Restart Effective Flip-Flop 38 INPUT / OUTPUT Instruction Flag 39, 41, 43 Flip-flop 40,44 AND circuit 42 Counter

Claims (3)

[Claims] 1. A channel device in a data processing device for controlling high-speed data transfer between a main memory device and a peripheral device according to a priority of the channel device in response to a request from the channel device, and interruption of data transfer of an I / O interface. Suspend resuming enable flip-flop for enabling resuming, means for instructing the start of data transfer by detecting that the valid data in the data buffer has reached a predetermined n-byte, and set when a predetermined m-byte is reached, A preceding data overrun flip-flop that is reset when the byte is reached, means for raising the request priority from the channel while the overrun flip-flop is set, and means for temporarily suppressing transfer of the I / O interface are provided. A channel device characterized by the above. 2. The channel device according to claim 1, further comprising flip-flop means which is set at the same time as the preceding data overrun flip-flop and is cleared by the next activation to raise the priority of the data transfer request. . 3. A counter that is cleared at startup and is incremented each time a preceding data overrun is detected, and a request priority from a channel that is set when the counter reaches a predetermined number and cleared at startup. 2. The channel device according to claim 1, further comprising: a flip-flop for raising the flip-flop, and if the preceding data overrun flip-flop is set again after the flip-flop is set, it is reported as a data overrun.