JP2000020398A - Disk storage device and disk controller to be applied to the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of write command processing by realizing the case of write command processing, in which a CPU is not concerned, at the time of executing a write cache function, resultingly shortening write command processing time. SOLUTION: When the result of cache discrimination due to a cache discriminating circuit 12 for a write command shows cache hit, a disk controller 8 performs processing from the start of data transfer to the end of the command only through respective circuits 10-17 composed of hardware while a CPU 5 is not concerned in. In the case of not cache hit, processing from the start of data transfer, in which a firmware including the CPU 5 is concerned, to the end of the command is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a disk storage device such as a hard disk drive, and more particularly to a disk controller constituting an AT interface between a host system and a drive.

[0002]

2. Description of the Related Art Conventionally, a hard disk drive (HD)
D) has a mechanism for recording data on a disk as a recording medium and reproducing data from the disk in response to a read / write command from a host system (such as a personal computer). The HDD has an AT interface function for transferring read / write data to and from a host system. Specifically, the interface function is realized by an LSI (one-chip integrated circuit) called a disk controller (HDC).

As shown in FIG. 10, a disk controller 80 controls a buffer memory 9 composed of a DRAM (read / write IC memory) to execute data transfer control between the host system 2 and the disk 4. I have. The disk controller 80 stores the data read from the disk 4 in response to the read command in the buffer memory 9 and then transfers the data to the host system 2 side by sector (block). On the other hand, after the data transferred from the host system 2 is stored in the buffer memory 9 in sector units in response to the write command, the data is transferred from the buffer memory 9 to the disk 4.

A recent disk controller 80 decodes (determines) a command CMD from the host system 2.
When the buffer memory 9 is in a state where data transfer is possible, a function is provided for automatically executing data transfer control without the intervention of a CPU (microprocessor) which is a main control device of the HDD (state machine). function).

If the command CMD is a read command, the command processing is automatically executed when the data transfer processing in which the request data from the host system 2 is transferred from the buffer memory 9 to the host system 2 ends. Ends. On the other hand, in the case of a write command, even if the transfer of the requested data from the host system 2 ends, the command processing does not end until the data is written on the disk 4.

Hereinafter, the write command processing will be described with reference to FIGS. 10 and 11. When a write command is issued from the host system 2, the HDC 80 receives request data (hereinafter, referred to as host data HD) accompanying the write command in sector units and stores it in the buffer memory 9. When all host data HD (D1) associated with the write command is stored in the buffer memory 9 (end of data transfer), the HDC 80 executes data transfer (write processing) to the disk 4. The data transferred to the disk 4 is called disk data DD for convenience.

The HDC 80 has a built-in status register 81 and sets a BUSY flag (BSY) during command processing. When all data is written on the disk 4 and the transfer of the disk data DD is completed, the HDC 80
And outputs an interrupt signal (IRQ) to the host system 2. At this point, the command processing of the first write command (request data D1) ends. Therefore, the host system 2 issues the next write command (request data D2). Thereafter, the command processing is executed in the same procedure (see the timing chart of FIG. 11).

In such a write command processing method,
The transfer processing of the disk data DD requires a longer processing time than the transfer processing of the host data HD. Therefore, a write cache function (mode) has been developed as a method for improving the performance of write command processing. This write cache function, as shown in Figure 5,
When the transfer of the host data HD is completed, the BSY of the status register 81 is cleared and the IRQ is output.
Therefore, since the write command ends at the end of the data transfer, the host system can issue the next write command in a short time.

[0009]

As described above, with the write cache method, the processing time from the start to the end of the write command processing can be shortened, so that the performance of the write command processing can be improved. Become. In the write cache method, if the state of the buffer memory is such that data transfer is possible, the command processing can be automatically terminated by the state machine function. But,
If the disk data DD remains in the buffer memory without being transferred, the command processing is in a standby state until the buffer memory becomes ready for data transfer. In short, the CPU finally determines the end of the write command, and when the command processing ends, the host system can issue the next write command. Therefore,
Even in the case of an HDC having a write cache function, the CPU is actually involved in determining the end of the command processing, so that there is a limit in reducing the execution time required for the command processing.

Therefore, an object of the present invention is to realize a write command process in which the CPU is not involved in executing the write cache function, thereby shortening the write command processing time and improving the performance of the write command process. Is to improve.

[0011]

The present invention controls data transfer between a disk of an HDD having an AT interface and a host system, and instructs the end of a write command when data transfer from the host system is completed. The present invention relates to a disk controller having a write cache function.

A disk controller according to the present invention comprises: a cache determination unit for determining whether the content of a write command received from a host system satisfies a cache hit condition; Means for transmitting a signal for instructing the end of the write command to the host system when the data transfer from the host system is completed, and in the case of a write command that does not satisfy the cache hit condition, A process for instructing the end of the write command after the transfer of the accompanying data is completed and the data transfer from the buffer memory to the disk is started to secure a data storage area for the next write command in the buffer memory. And control means for executing.

Specifically, the conditions for a cache hit are:
That is, the address of the data associated with the write command is a sequential address that is continuous with the address of the data associated with the immediately preceding write command. The dedicated means is hardware that executes write command termination processing without involving the CPU. On the other hand, the control means is firmware including a CPU and a program.

With such a configuration, it is possible to execute the processing for terminating the write command processing at the time when the data transfer accompanying the write command has been completed, without involving the command termination judgment processing of the CPU. Therefore, the time required for the write command processing can be reduced, and the performance of the write command processing can be greatly improved.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing H related to the present embodiment.
FIG. 2 is a block diagram illustrating a main part of the DD, FIGS. 2 to 4 are flowcharts for explaining a write command process of the embodiment, and FIG. 6 illustrates an operation of a buffer control circuit of the embodiment. FIG. (Configuration of HDD and Disk Controller)
As shown in FIG. 1, the recording medium is roughly classified into a disk 4, a CPU 5, a ROM 6, an EEPROM 7, a disk controller (HDC) 8, and a buffer memory (DRA).
M) 9. The ROM 6 is a read-only memory that stores programs necessary for the operation of the CPU 5. In the present embodiment, the CPU 5 and the program in the ROM 6 may be referred to as firmware in comparison with hardware. The EEPROM 7 is a non-volatile memory that stores various parameters required for control processing (limited to write command processing in the present embodiment) by the CPU 5.

The disk controller 8 of the present embodiment comprises:
One-chip LS including buffer memory (DRAM) 9
I, and various circuits 10 to 17 necessary for command processing
Having. These circuits may be referred to as hardware in contrast to the firmware.

The disk controller 8 includes a command decode circuit 10, a host transfer processing circuit 11, a write command end control circuit 13, a buffer control circuit 14,
It has a host processing control circuit 16 and a disk processing control circuit 17. Host transfer processing circuit 11
Includes a cache determination circuit 12 described later. The buffer control circuit 14 includes a transfer control counter 15
A (hereinafter referred to as counter A) and transfer control counter 15
B (hereinafter referred to as counter B).

The command decode circuit 10 determines a command such as a write command issued from the host system 2. The host transfer processing circuit 11 executes an automatic transfer process of data between the host system 2 and the buffer memory 9 according to the command determined by the command decode circuit 10. Data transfer between the host system 2 and the buffer memory 9 is performed via the AT interface 3. The cache determination circuit 12 has a cache address determination function, and in this embodiment, determines whether or not an address accompanying a write command is a continuous sequential address. That is, the cache determination circuit 12 determines that a cache hit has occurred when the address of the received write command (the logical address of the write data) is a sequential address that is continuous with the address of the immediately preceding write command.

The write command end control circuit 13 confirms the end of data transfer and the availability of the buffer memory 9, clears the BUSY of the status register (see FIG. 10), generates an IRQ, and automatically ends the command. Has functions. The buffer control circuit 14 controls the input and output of data in the buffer memory 9 using the counters A and B. The host processing control circuit 16 has a function of adding the count value of the counter B to the counter A and initializing the counter B, as described later. The disk processing control circuit 17 executes data transfer processing (disk data transfer) between the buffer memory 9 and the disk 4.

In the present embodiment, since there is no direct relationship, mechanisms such as a head and a read / write circuit required for data read / write operation on the disk 4 are omitted from the description. (Operation of Disk Controller) In addition to FIG.
4 to FIG. 4 and FIG. 6, the operation of the disk controller of the present embodiment will be described.

First, when the HDC 8 receives a command from the host system 2 in the idle state, the command decode circuit 10 decodes the command and determines whether or not the command is a write command (step S1). Here, it is assumed that a write command is issued from the host system 2. The host transfer processing circuit 11 transfers host data accompanying the write command to the buffer memory 9 in sector units (block units).

Here, in the present embodiment, the cache determination circuit 12 executes a cache hit determination process of the received write command (step S2). If the address accompanying the first write command or the next write command is not a sequential address, no cache hit occurs (NO in step S3). At this time, the buffer control circuit 14 controls the input of the buffer memory 9 using the counter B (step S14 in FIG. 3). The host transfer processing circuit 11 starts transferring the host data HD (Step S15). The buffer control circuit 14 checks the available storage area of the buffer memory 9 based on the pointer (host pointer) of the buffer memory 9 obtained from the counter B,
The host data stored in the buffer memory 9 is stored.

The counter B is updated every time host data is transferred. When the counter B is updated, the counter A maintains the count value (write pointer) without being updated even when the transfer of the host data is executed. The counter A performs not only the host data transfer processing but also the data transfer processing (disk data DD) from the buffer memory 9 to the disk 4 by the disk processing control circuit 17.
Used for transfer). The host data transfer process using the counter B is executed independently of the disk data transfer process using the counter A. That is, newly transferred host data is only stored in the buffer memory 9 and is not immediately transferred to the disk 4.

Here, in the case of the first write command, the transfer processing of the disk data (host data accompanying the previous write command) is not executed. Therefore, in the present embodiment, when there is no cache hit, when the CPU 5 checks and confirms the end of the transfer of the host data, the BUSY of the status register is cleared, the IRQ is generated, and the write command ends (step S28-). S3
3). At this time, the CPU 5 executes the command end processing after confirming the existence of the free area of at least one block (one sector) of the buffer memory 9 (step S).
30, S31).

Next, a case where a write command is subsequently issued will be described. If a cache hit does not occur as described above, host data transfer processing using the counter B is automatically executed. Here, the processing procedure by the firmware by the CPU 5 will be described with reference to the flowchart of FIG. When receiving the write command, the CPU 5 refers to the determination result of the cache hit, and in the case of the cache hit, returns to the idle state (steps S20 to S22).

On the other hand, if there is no cache hit,
The CPU 5 checks the end of the write processing on the disk 4 side of the data transferred by the previous write command (steps S22 and S23). This write process is a process of writing the data stored in the buffer memory 9 by the previous write command onto the disk 4 (disk data transfer process). The CPU 5 waits until the write processing is completed, and after that, performs preparation processing for the write processing for the next write command (Y in step S24).
ES, S24). The preparation process is a process of seeking an address (a physical address specified by a track and a sector) for writing on the disk 4 and a process of setting various parameters necessary for the writing process.

After the preparation processing, the CPU 5 starts a disk data transfer processing for transferring the host data transferred from the host system 2 from the buffer memory 9 to the disk 4 (step S27). At this time, as described above, it is assumed that the host data for the first block has been transferred to the buffer memory 9 by the host transfer processing circuit 11 (see steps S14 and S15). C
The PU 5 controls the host processing control circuit 16 to add the count value of the counter B to the counter A,
Initialize the counter B. That is, a counter setting process for changing the counter used for the host data transfer process to the counter A is executed (step S25).

After the counter setting processing, the CPU 5 starts the transfer processing of the remaining host data and the transfer processing of the disk data (steps S26 and S27). When the host data transfer processing and the disk data transfer processing are started, the buffer control circuit 14 controls the input / output of the buffer memory 9 using the counter A (FIG. 4).
Steps S16 and S17). Specifically, for example, when the value of the counter A is “0” and the value of the counter B is “1”, the value of the counter A becomes “1” by the counter setting process. At this time, the counter B is initialized (the value is 0).
Then, as shown in FIG. 6, when the host data HD for the remaining three blocks is transferred to the buffer memory 9 after the data for the first block, the value of the counter A becomes “4”. The CPU 5 checks the end of the transfer of the host data by the pointer of the counter A, and executes the command end process after confirming the existence of the free area of at least one block (one sector) in the buffer memory 9 (step S28). To S33).

On the other hand, in the cache hit judging process in step S2 of FIG. 2, if a cache hit occurs, the buffer control circuit 14 executes the input / output control of the buffer memory 9 in the host data transfer using the counter A. (Steps S3 to S5). At this time, the buffer control circuit 14 checks the free area of the buffer memory 9 using the pointer indicated by the counter A (steps S6 and S7). That is, when the host data can be transferred by the write command (there is a free area in which the host data can be stored), the host data transferred in units of one block is stored in the buffer memory 9.
(Steps S8 and S9). Here, when there is no free area in the buffer memory 9, the host data transfer processing enters a standby state.

As described above, when the cache determination result of the write command is a cache hit, the CPU 5
(Firmware) without involvement
The transfer process of the host data is automatically executed by the hardware of C8. Then, after the write command end control circuit 13 included in the hardware confirms that there is at least one block of free area necessary for the next write command in the buffer memory 9, the command end processing is executed. That is, the BUS of the status register
Y is cleared, an IRQ is generated, and the write command ends (steps S11-S13). (Modification of this Embodiment) As described above, when the cache determination result of the write command is a cache hit, the host transfer processing circuit 1 can be executed without involving the CPU 5.
By 1, the host data of one block unit is automatically transferred. Further, the end of data transfer and the availability of the buffer memory 9 are checked by the write command end control circuit 13, and the end processing of the write command (BUSY
Clearing and generation of an IRQ). In this case, the buffer control circuit 14 uses the counter A to
The input / output control of the buffer memory 9 in the host data transfer and disk data transfer processing by the disk processing control circuit 17 is executed.

As a modification of this embodiment, the buffer control circuit 14 uses a command processing method using only the counter A without using the counter B, regardless of the result of the cache hit determination. This will be described with reference to FIG.

First, in the hardware procedure of the HDC 8 shown in FIG. 7, when the HDC 8 receives a command from the host system 2 in an idle state, the HDC 8 decodes the command by the command decode circuit 10 and determines whether or not it is a write command. (Step S40). In the case of a write command, the host transfer processing circuit 11 transfers one block of host data accompanying the write command to the buffer memory 9 (step S41).

Thereafter, the cache determination circuit 12 executes a cache hit determination process for the write command.
The process is in a state of waiting for the process on the firmware side, which is PU5 (from NO in step S43 to the process in FIG. 8).

On the firmware side, as shown in FIG. 8, when receiving the write command, the CPU 5 refers to the determination result of the cache hit, and returns to the idle state in the case of the cache hit (steps S60 to S6).
2). On the other hand, if there is no cache hit,
5 checks the end of the write processing on the disk 4 side of the data transferred by the previous write command, as described above (steps S62 and S63). The CPU 5 waits until the write processing is completed, and after that, executes preparation processing for the write processing for the next write command (YES in step S64, S65).

After the preparation process, the CPU 5 starts a disk data transfer process for transferring the host data transferred from the host system 2 from the buffer memory 9 to the disk 4 (step S27). At this time, the counter A is incremented as one block of data transfer (step S66). And, as mentioned above,
The CPU 5 starts the transfer processing of the remaining host data and the transfer processing of the disk data (steps S67 and S67).
68). When the host data transfer process and the disk data transfer process are started, the buffer control circuit 1
4 controls the input / output of the buffer memory 9 using the counter A (steps S54 and S55 in FIG. 9). CPU
5 checks the end of the transfer of the host data by the pointer of the counter A, and executes the command end process after confirming the existence of an empty area of at least one block (one sector) in the buffer memory 9 (step S69). To S74).

On the other hand, in the cache hit judging process of step S42 in FIG. 2, if a cache hit occurs, the counter A determines that one block of data has been transferred.
It is incremented (steps S43, S44). Then, the transfer processing of the remaining host data is started by the host transfer processing circuit 11 (step S45). At this time, the buffer control circuit 14 checks the free area of the buffer memory 9 using the pointer indicated by the counter A (step S46). That is, when the transfer of the host data by the write command is possible (there is a free area where the host data can be stored), the host data transferred in units of one block is stored in the buffer memory 9 (steps S47 and S48). ). Here, when there is no free area in the buffer memory 9, the host data transfer processing enters a standby state.

Then, the write command end control circuit 13
Thus, after confirming the existence of at least one block of free area necessary for the next write command in the buffer memory 9, the command end processing is executed. That is, the status register BUSY is cleared, an IRQ is generated, and the write command is terminated (steps S50-S53).

As described above, according to the present embodiment and its modification, when the cache determination result of the write command is a cache hit, the hardware of the HDC 8 shown in FIG. The transfer processing of the host data is automatically executed by the software.
That is, if the address of the data accompanying the write command is a sequential address that is consecutive to the address of the previous write command, if there is a storage area in the buffer memory, the data is automatically executed from the start of data transfer to the end of the command. You. On the other hand, if there is no cache hit,
From the start of data transfer to the end of the command, the CPU (firmware) is involved in processing. Therefore, a so-called write cache function capable of executing a command end process at the end of the host data transfer process can be realized. On the other hand, when a cache hit does not occur, a situation in which new host data is overwritten with data before the disk data transfer processing in the buffer memory 9 can be reliably prevented by the data transfer processing involving the CPU.

[0039]

As described above in detail, according to the present invention, a write cache function that is a write command process that does not involve the CPU based on a cache hit condition at the time of write command processing of a disk storage device such as a hard disk drive is provided. realizable. Therefore, as a result, the write command processing time can be reduced, and the performance of the write command processing can be improved.

[Brief description of the drawings]

FIG. 1 is an exemplary block diagram showing a main part of an HDD according to an embodiment of the present invention.

FIG. 2 is an exemplary flowchart for explaining write command processing according to the embodiment;

FIG. 3 is an exemplary flowchart for explaining write command processing according to the embodiment;

FIG. 4 is an exemplary flowchart for explaining write command processing according to the embodiment;

FIG. 5 is a timing chart for explaining a conventional write cache function.

FIG. 6 is an exemplary conceptual diagram for explaining the operation of the buffer control circuit of the embodiment.

FIG. 7 is a flowchart relating to a modification of the embodiment.

FIG. 8 is a flowchart relating to a modification of the embodiment.

FIG. 9 is a flowchart relating to a modification of the embodiment.

FIG. 10 is a block diagram for explaining a configuration of a conventional disk controller.

FIG. 11 is a timing chart for explaining the operation of a conventional disk controller.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Hard disk drive (HDD) 2 ... Host system 3 ... Host interface 4 ... Disk 5 ... CPU 6 ... ROM 7 ... EEPROM 8 ... Disk controller (HDC) 9 ... Buffer memory (DRAM) 10 ... Command decoding circuit 11 ... Host transfer Processing circuit 12 Cache determination circuit 13 Write command end control circuit 14 Buffer control circuit 15A Transfer control counter (counter A) 15B Transfer control counter (counter B) 16 Host processing control circuit 17 Disk processing control circuit

Claims (10)

[Claims] 1. A data transfer control for storing data transferred from the host system in a buffer memory in response to a write command from the host system, and when the data transfer from the host system is completed, the write operation is performed. A disk storage device comprising a disk controller having a write cache function for instructing termination of a command, wherein the disk controller, when the write cache function is enabled, a content of the write command received from the host system is a cache hit. Cache determination means for determining whether the condition of the cache hit is satisfied; and in the case of a write command satisfying the condition of the cache hit, instructing the end of the write command when data transfer from the host system is completed. Signal for the And a dedicated means for transmitting to the storage system. The present invention is applied to a disk storage device having a disk as a recording medium for recording data, and has a buffer memory for controlling data transfer between the disk and a host system, wherein data from the host system is transmitted. A disk controller having a write cache function for instructing the end of the write command at the time of completion of transfer, wherein when the write cache function is enabled, the content of the write command received from the host system determines a cache hit condition. A cache determining means for determining whether or not the write command is satisfied; and a write command which satisfies the cache hit condition, instructing the end of the write command when data transfer from the host system is completed. Dedicated to send signals to the host system If the write command does not satisfy the cache hit condition, the data transfer accompanying the write command ends, and the data transfer from the buffer memory to the disk is started. A controller for executing processing for instructing termination of the write command after securing a storage area for data accompanying the write command. 3. The disk storage device according to claim 1, wherein the condition of the cache hit is a sequential address in which a data address associated with the write command is continuous with an address of data associated with the immediately preceding write command. Alternatively, the disk controller according to claim 2. 4. A data transfer control for storing data transferred from the host system in a buffer memory in response to a write command from the host system, and when the data transfer from the host system ends, the write operation is performed. A disk storage device comprising a disk controller having a write cache function for instructing the end of a command, wherein the disk controller is configured such that, when the write cache function is enabled, an address of data accompanying the write command corresponds to a previous write command. A cache determination that determines whether or not the content of the write command received from the host system satisfies the condition of the cache hit, when the condition of the cache hit is that the address is a sequential address continuous to the address of the accompanying data. Means A first counter functioning in the case of a write command that satisfies the cache hit condition, and an output means for outputting a signal for instructing the end of the write command; A dedicated means for processing the data transfer from the host system and outputting a signal for instructing the end of the write command from the output means to the host system when the data transfer is completed; and the cache hit condition is not satisfied. In the case of a write command, the second counter means for processing the data transfer from the host system and in the case of a write command which does not satisfy the cache hit condition, the second While executing data transfer from the system, A data transfer from the buffer memory to the disk is performed so as to avoid overwriting, and a signal for instructing the end of the write command is sent to the host system when the data transfer from the host system is completed. A disk storage device comprising: a control unit for outputting. 5. A disk storage device having a disk as a recording medium for recording data, comprising a buffer memory for controlling data transfer between the disk and a host system, wherein the data from the host system is provided. A disk controller having a write cache function for instructing the end of the write command when transfer is completed, wherein when the write cache function is enabled, the address of the data accompanying the write command is the data address of the data associated with the immediately preceding write command. A cache determining unit that determines whether or not the content of the write command received from the host system satisfies the cache hit condition, when the condition of the cache hit is that the address is a sequential address continuous with the address; From the host system First counter means for processing both data transfer to the buffer memory and data transfer from the buffer memory to the disk; and second counter for processing data transfer from the host system to the buffer memory. Means, and in the case of a write command satisfying the cache hit condition, executing data transfer accompanying the write command by the first counter means, and terminating the write command when the data transfer ends. Dedicated means for transmitting a signal for instructing to the host system; and in the case of a write command which does not satisfy the cache hit condition, data transfer accompanying the write command is started by the second counter means, A first counter means for transferring the data from the buffer memory to the disk; A process of executing a data transfer process to secure a data storage area in the buffer memory, and executing a process for instructing the end of the write command when the data transfer to the buffer memory is completed. And a disk controller. 6. The apparatus according to claim 1, wherein said dedicated means has a hardware configuration including a dedicated circuit group, and said control means has a firmware configuration having a CPU that operates according to a program prepared in advance. A disk storage device according to any one of claims 1 to 5, and a disk controller according to any one of claims 2 and 5. 7. The exclusive means instructs the end of the write command at the time when the data transfer from the host system is completed and after securing a data storage area for the next write command in the buffer memory. The disk controller according to any one of claims 1 and 4, or a disk controller according to any one of claims 2 and 5, wherein a signal for outputting the signal is rubbed. 8. The present invention is applied to a disk storage device having a disk as a recording medium for recording data, and has a buffer memory for controlling data transfer between the disk and a host system, wherein data from the host system is What is claimed is: 1. A disk controller command processing method having a write cache function for instructing the end of said write command at the time of completion of transfer, comprising: receiving a write command issued from said host system; When the condition of the cache hit is that the address of the data associated with the write command is a sequential address that is consecutive to the address of the data associated with the immediately preceding write command, the content of the write command received from the host system is Cash hit Determining whether the condition of the cache hit is satisfied; and, in the case of a write command satisfying the condition of the cache hit, instructing the end of the write command when the data transfer from the host system is completed. And transmitting the signal to the host system. 9. In the step of judging the condition of the cache hit, when the write command does not satisfy the condition of the cache hit, the transfer of data accompanying the write command is started and the disk memory is read from the buffer memory. Starting a data transfer to the buffer memory to secure a storage area in the buffer memory; and executing a process for instructing the end of the write command when the data transfer accompanying the write command ends. 9. The command processing method according to claim 8, comprising: 10. When a write command is received while the write cache function is enabled, one from the host system is received.
When data transfer for a block is executed and the cache hits (sequential address) thereafter, the transfer processing counter for one block is updated, the remaining data transfer from the host system is started, and the data transfer ends. Then, after waiting for the capacity of one block in the buffer to become free, the command end processing (BUSY clear, IR
Q), and if the cache does not hit, terminate the process of writing the previous command to the media, and then update the transfer process counter by one block. Control means for executing the remaining host data transfer after that, starting the write processing on the medium by this command, and executing the command end processing.