JPH0355833A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0355833A
JPH0355833A JP19227889A JP19227889A JPH0355833A JP H0355833 A JPH0355833 A JP H0355833A JP 19227889 A JP19227889 A JP 19227889A JP 19227889 A JP19227889 A JP 19227889A JP H0355833 A JPH0355833 A JP H0355833A
Authority
JP
Japan
Prior art keywords
wiring pattern
metal layer
hole
etching
dry etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19227889A
Other languages
Japanese (ja)
Other versions
JP2786680B2 (en
Inventor
Satoshi Saito
聡 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP1192278A priority Critical patent/JP2786680B2/en
Publication of JPH0355833A publication Critical patent/JPH0355833A/en
Application granted granted Critical
Publication of JP2786680B2 publication Critical patent/JP2786680B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To easily eliminate reaction product which is generated by dry etching and attaches to the inside of a through hole, by a method wherein the etching process for forming a through hole is constituted of the following; a process for dry etching an insulating layer, and a post treatment process for dipping and eliminating the reaction product generated by dry etching while using a specified solution. CONSTITUTION:A semiconductor substrate has a laminated film on the surface, which film is composed of a lower wiring pattern metal layer 2 composed of aluminum and/or its alloy and an insulating film 3 formed on the layer 2. After said substrate is etched and a through hole 5 is formed in the insulating film 3, an upper wiring pattern metal layer 7 is formed. When a semiconductor device is formed by electrically connecting the lower wiring pattern metal layer 2 and the upper wiring pattern metal layer 7 via the through hole 5, the above etching is constituted of the following; a process for dry-etching the insulating film 3, and a post-treatment process wherein solution selected from hydrofluoric acid, etchant, and warm water is used and reaction product generated by dry etching is dipped and eliminated. Thereby a semiconductor device wherein the resistance between metal-metal is stabilized can be obtained.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は半導体装置の製造方法に関する。さらに詳し
くは、多層配線を用いたLSIの製造技術に好適な半導
体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a semiconductor device suitable for LSI manufacturing technology using multilayer wiring.

(口)従来の技術 通常、半導体装置は、半導体基板上に絶縁層を介して配
線パターン用のアルミニウム及びその合金等の金属層を
有して製造されるが、このとき上記絶縁層の所定の位置
にエッチングにより形成されている通孔(コンタクトホ
ール)を通じて半導体基板上に設けられた能動層と上記
金属層との導通が図られている。
(Example) Conventional technology Normally, a semiconductor device is manufactured by having a metal layer such as aluminum or its alloy for a wiring pattern on a semiconductor substrate via an insulating layer. The active layer provided on the semiconductor substrate and the metal layer are electrically connected through contact holes formed at the positions by etching.

またさらに、LSIの製造においては、配線を多層構造
にしてチップ面積の縮小を図ることが行われている。上
記多層配線は、複数の配線用金属層とこれらの金属層間
を絶縁する眉間絶縁層とを半導体基板上に積層して構成
されている。このような多層配線では、所定の位置で絶
縁層を貫通してその上下の金属層間を導通ずる通孔(不
ル〜ホール)と上記のごとく金属層と半導体基板の能動
層とを導通ずる通孔(コンタクトホール)とが設けられ
ている。
Furthermore, in the manufacture of LSIs, wiring is made into a multilayer structure in order to reduce the chip area. The multilayer wiring is constructed by laminating a plurality of wiring metal layers and a glabella insulating layer for insulating between these metal layers on a semiconductor substrate. In such multilayer wiring, there are through holes (holes) that penetrate the insulating layer at predetermined positions and provide conduction between the metal layers above and below the insulating layer, and holes that provide conduction between the metal layer and the active layer of the semiconductor substrate as described above. A hole (contact hole) is provided.

上記のようにコンタクトホール又はスルーホール等の通
孔の形成は、反応性ガス例えばCHP.CF4またはこ
れらにONを加えたガスを用いて絶縁層をエッチングす
るドライエッチングの手法により行われている。
As mentioned above, the formation of contact holes, through holes, etc. is performed using a reactive gas such as CHP. This is done by a dry etching method in which the insulating layer is etched using CF4 or a gas obtained by adding ON to CF4.

(ハ)発明が解決しようとする課題 しかしながら、上記ドライエッチングにおいては、エッ
チングガスと、配線パターン金属層を形成するアルミニ
ウムやその合金のアルミニウムとの化合物が生成し、こ
れが形成された通孔内、ことに該通孔内底部に露出され
るアルミニウム表面に付着する。
(c) Problems to be Solved by the Invention However, in the above-mentioned dry etching, a compound of the etching gas and aluminum or its alloy aluminum forming the wiring pattern metal layer is generated, and this creates a problem in the formed through hole. Particularly, it adheres to the aluminum surface exposed at the inner bottom of the through hole.

従来言われているドライエッチングでの反応生成物は、
O,プラズマを用いた有機物除去や有機洗浄により除去
されていたが、上記付着する反応生成物はこれらの除去
法では完全に除去しきれなく、従ってコンタクトエッチ
の際にはコンタクト抵抗を増大させたり、多層レジスト
による微細パターン形成の線幅制御を困難にしている。
The reaction products of conventional dry etching are
O, organic matter removal using plasma and organic cleaning have been used to remove the above-mentioned adhering reaction products, but these removal methods cannot completely remove them, so contact etching may increase contact resistance. This makes it difficult to control the line width in fine pattern formation using multilayer resists.

この発明はかかる状況に鑑み為されたものであり、絶縁
層での通孔形成時のドライエッチングにより発生し該通
孔内に付着する反応生成物を、特定の溶液・により簡便
に除去しうる処理が含まれた半導体装置の製造方法を提
供しようとするものである。
The present invention has been made in view of the above situation, and it is possible to easily remove reaction products generated by dry etching when forming a through hole in an insulating layer and adhere to the inside of the through hole using a specific solution. The present invention aims to provide a method for manufacturing a semiconductor device that includes processing.

(二)課題を解決するための手段 かくしてこの発明によれば、アルミニウム及び/又はそ
の合金からなる下部配線パターン金属層及び該層上に形
成される絶縁層とからなる積層膜を表面に有する半導体
基板をエッチングして上記絶縁層に通孔を形成した後、
上記絶縁層に上部配線パターン金属層を設け、上記通孔
を通じて前記下部配線パターン金属層と上記上部配線パ
ターン金属層とを導通して半導体装置を形成することか
らなり、上記エッチングが、絶縁層をドライエッチング
する工程と、フッ化水素酸、サイロックスエッチャント
及び温水から遺択される溶液を用いて上記ドライエッチ
ングで発生する反応生成物を浸漬除去する後処理工程と
からなることを特徴とする半導体装置の製這方法が提供
される。
(2) Means for Solving the Problems Thus, according to the present invention, a semiconductor having on its surface a laminated film comprising a lower wiring pattern metal layer made of aluminum and/or its alloy and an insulating layer formed on the layer. After etching the substrate to form a through hole in the insulating layer,
An upper wiring pattern metal layer is provided on the insulating layer, and the lower wiring pattern metal layer and the upper wiring pattern metal layer are electrically connected through the through hole to form a semiconductor device. A semiconductor characterized by comprising a step of dry etching, and a post-treatment step of removing reaction products generated in the dry etching by immersion using a solution selected from hydrofluoric acid, silox etchant, and hot water. A method of fabricating a device is provided.

この発明は、半導体装置の製造方法において、通孔を形
成する通常のドライエッチング工程の後に、特定の溶液
を用いるウエットエッチング工程を挿入したものとみる
ことができる。
The present invention can be seen as a method for manufacturing semiconductor devices in which a wet etching step using a specific solution is inserted after the normal dry etching step for forming through holes.

この発明の方法において、ドライエッチングの後処理に
用いられる溶液としては以下のものが挙げられる。すな
わち、フッ化水素酸(HF),サイロックスエッチャン
ト、温水である。これらは単独で用いられる。
In the method of this invention, the following solutions may be used in the post-treatment of dry etching. namely, hydrofluoric acid (HF), Cyrox etchant, and hot water. These are used alone.

この発明の方法において、上記溶液による除去処理は、
上記フッ化水素酸を用いる場合は、その濃度が約1%以
下のもので30秒以内の処理とされる。l%より高濃度
のもの又は30秒より長い処理時間ではアルミニウムを
エッチングしてしまう。
In the method of the present invention, the removal treatment using the solution includes:
When the above-mentioned hydrofluoric acid is used, the concentration thereof is about 1% or less and the treatment is carried out within 30 seconds. If the concentration is higher than 1% or the treatment time is longer than 30 seconds, aluminum will be etched.

上記サイロックスエッチャントを用いる場合、まずサイ
ロツクスエヅチャントはCH3COOH:NH.F :
 H,O=2 : l : 2の割合で混合された溶液
であり、PSG等のエッチャントとして公知のものであ
る。これはアルミニウムとの遺択比がある点で好ましい
が、この溶液による処理時間はlO秒以内とされる。1
0秒より長い処理時間の場合はSiOz系絶縁層をエッ
チングしてしまう。また温水によっても除去できる。こ
の場合温水の温度によって処理時間が多少変化する。例
えば60℃では2分以内、i00℃では1分以内の処理
とされる。
When using the above Pyrox etchant, first the Pyrox etchant is CH3COOH:NH. F:
The solution is a mixture of H and O in a ratio of 2:1:2, and is a well-known etchant such as PSG. This is preferable since it has a selective ratio with aluminum, but the treatment time with this solution is within 10 seconds. 1
If the processing time is longer than 0 seconds, the SiOz-based insulating layer will be etched. It can also be removed with warm water. In this case, the processing time varies somewhat depending on the temperature of the hot water. For example, at 60° C., the processing time is within 2 minutes, and at i00° C., the processing time is within 1 minute.

この温度による処理時間が長い場合は、絶縁層のハガレ
やフクレが発生し、半導体装置の不良の原因となる。
If the processing time at this temperature is long, peeling or blistering of the insulating layer will occur, causing defects in the semiconductor device.

この発明の方法において、ドライエッチング時に発生す
る反応生成物を除去する工程以外は、当該分野で公知の
方法、装置がそのまま用いられる。
In the method of this invention, methods and apparatuses known in the art can be used as they are, except for the step of removing reaction products generated during dry etching.

(ホ)作用 この発明によれば、半導体装置製造過程において、通孔
をドライエッチングにより形成する際発生したアルミニ
ウム化合物は、形成される通孔内に付着するが、該エッ
チング後、フッ化水素酸、サイロックスエッチャント及
び温水から選択される溶液に浸漬処理されると、通孔内
の絶縁層側壁及び底部に露出したアルミニウム及び/又
はその合金からなる金属層に付着したアルミニウム化合
物は、選択的に除去されることとなる。
(E) Effect According to the present invention, in the process of manufacturing a semiconductor device, aluminum compounds generated when forming through holes by dry etching adhere to the inside of the formed through holes, but after the etching, hydrofluoric acid When the aluminum compound adhering to the metal layer made of aluminum and/or its alloy exposed on the side walls and bottom of the insulating layer inside the through hole is selectively removed by immersion treatment in a solution selected from , Syrox etchant and hot water. It will be removed.

以下実施例によりこの発明を詳細に説明するが、これに
よ.りこの発明は限定されるものではない。
The present invention will be explained in detail with reference to Examples below. Riko's invention is not limited.

(へ)実施例 第1図はこの発明の方法の一実施例を示す工程説明図で
ある。
(f) Example FIG. 1 is a process diagram showing an example of the method of the present invention.

半導体基板上に設けられた絶縁膜(BPSG)(1)上
にアルミニウム合金を用いてリソグラフの手法により下
部配線パターン(2)を形成した後、この上に、眉間絶
縁膜( S iO t) (3)をプラズマCVDによ
り形成して上記配線パターンを被覆する(第1図(a)
)。
After forming a lower wiring pattern (2) using an aluminum alloy by a lithography method on an insulating film (BPSG) (1) provided on a semiconductor substrate, a glabellar insulating film (SiOt) ( 3) is formed by plasma CVD to cover the above wiring pattern (Fig. 1(a)).
).

次いで配線パターン(2)上にフォトレジスト(4)を
塗布し、露光、現像によってコンタクトホール形成用マ
スクを形成する。次いでこれをC H F s若しくは
CF4ガス又はこれらにO,を加えたガスを用いて反応
性イオンエッチング(RIE)にて、コンタクトホール
(5)を開孔する。このときこれらのエッチングガスと
アルミニウムとが反応してコンタクトホール内に反応生
成物(6)が付着する(同図(b))。
Next, a photoresist (4) is applied onto the wiring pattern (2), and a contact hole forming mask is formed by exposure and development. Next, a contact hole (5) is formed in this by reactive ion etching (RIE) using C H F s or CF 4 gas, or a gas in which O is added to these gases. At this time, these etching gases and aluminum react with each other, and a reaction product (6) is deposited inside the contact hole (FIG. 2(b)).

上記で得られた半導体基板を、下表に示す溶液のいずれ
かに所定時間浸漬すると、反応生戚物(6)のみが選択
的に除去される(同図(C))。
When the semiconductor substrate obtained above is immersed in any of the solutions shown in the table below for a predetermined period of time, only the reaction product (6) is selectively removed ((C) in the same figure).

上記浸漬後の半導体基板のレジストを、O,プラズマ、
ケミカルストリッパー、及びグイフロン、アセトン若し
くはイソプロビルアルコールによる有機洗浄に付して除
去し、洗浄後、上記形成されたコンタクトホール(5)
を含む層間絶縁層(3)上にアルミニウム合金による上
部配線パターン(7)を形成し、コンタクトホール(5
)を介して下部配線パターン(2)と上部配線パターン
(7)との導通を図る(同図(d))。
After the above immersion, the resist of the semiconductor substrate was washed with O, plasma,
The contact hole (5) formed above is removed by chemical stripper and organic cleaning using Guiflon, acetone or isopropyl alcohol.
An upper wiring pattern (7) made of aluminum alloy is formed on the interlayer insulating layer (3) containing contact holes (5).
) to establish conduction between the lower wiring pattern (2) and the upper wiring pattern (7) ((d) in the same figure).

以上の工程により、メタルーメタル間抵抗が安定した半
導体装置が得られた。
Through the above steps, a semiconductor device with stable metal-to-metal resistance was obtained.

(ト)発明の効果 この発明によれば、半導体装置の製造方法において、ア
ルミニウムや絶縁膜の形状を変えることなく付着物のみ
を除去することができる。従って安定したメタルーメタ
ル間抵抗が得られ、一方多層レジストプロセスの制御性
を向上できる。
(G) Effects of the Invention According to the present invention, in a method for manufacturing a semiconductor device, only deposits can be removed without changing the shape of aluminum or the insulating film. Therefore, stable metal-to-metal resistance can be obtained, while the controllability of the multilayer resist process can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の方法の一実施例の工程説明図である
。 l・・・・・・絶縁膜 2・・・・・・下部配線パターン、 3・・・・・・プラズマSin.、 4・・・・・・フォトレジスト、 5・・・・・・コンタクトホール、 6・・・・・・反応生成物 7・・・・・・上部配線パターン。 第 1 画 〜1 (d)
FIG. 1 is a process explanatory diagram of an embodiment of the method of the present invention. l... Insulating film 2... Lower wiring pattern, 3... Plasma Sin. , 4... Photoresist, 5... Contact hole, 6... Reaction product 7... Upper wiring pattern. 1st stroke~1 (d)

Claims (1)

【特許請求の範囲】 1、アルミニウム及び/又はその合金からなる下部配線
パターン金属層及び該層上に形成される絶縁層とからな
る積層膜を表面に有する半導体基板をエッチングして上
記絶縁層に通孔を形成した後、上記絶縁層に上部配線パ
ターン金属層を設け、上記通孔を通じて前記下部配線パ
ターン金属層と上記上部配線パターン金属層とを導通し
て半導体装置を形成することからなり、 上記エッチングが、絶縁層をドライエッチングする工程
と、フッ化水素酸、サイロックスエッチャント及び温水
から選択される溶液を用いて上記ドライエッチングで発
生する反応生成物を浸漬除去する後処理工程とからなる
ことを特徴とする半導体装置の製造方法。
[Claims] 1. A semiconductor substrate having a laminated film on its surface consisting of a lower wiring pattern metal layer made of aluminum and/or its alloy and an insulating layer formed on the layer is etched to form the insulating layer. After forming a through hole, an upper wiring pattern metal layer is provided in the insulating layer, and the lower wiring pattern metal layer and the upper wiring pattern metal layer are electrically connected through the through hole to form a semiconductor device, The etching comprises a step of dry etching the insulating layer, and a post-treatment step of removing reaction products generated in the dry etching by immersion using a solution selected from hydrofluoric acid, Cyrox etchant, and hot water. A method for manufacturing a semiconductor device, characterized in that:
JP1192278A 1989-07-24 1989-07-24 Method for manufacturing semiconductor device Expired - Fee Related JP2786680B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1192278A JP2786680B2 (en) 1989-07-24 1989-07-24 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1192278A JP2786680B2 (en) 1989-07-24 1989-07-24 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPH0355833A true JPH0355833A (en) 1991-03-11
JP2786680B2 JP2786680B2 (en) 1998-08-13

Family

ID=16288620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1192278A Expired - Fee Related JP2786680B2 (en) 1989-07-24 1989-07-24 Method for manufacturing semiconductor device

Country Status (1)

Country Link
JP (1) JP2786680B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041186A (en) * 1987-11-30 1991-08-20 Kabushiki Kaisha Toshiba Method for manufacturing compound semiconductor single crystals using a hydrogen monitor gas
JPH04302142A (en) * 1991-03-29 1992-10-26 Sharp Corp Manufactuer of semiconductor device
JPH05144775A (en) * 1991-11-18 1993-06-11 Sharp Corp Dry etching method
JPH0683279A (en) * 1991-12-31 1994-03-25 Hyundai Electron Ind Co Ltd Full page monitor
WO2002033741A1 (en) * 2000-10-18 2002-04-25 Sony Corporation Method for forming insulation film and method for manufacturing semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724540A (en) * 1980-07-19 1982-02-09 Nippon Telegr & Teleph Corp <Ntt> Rinsing of through hole in semiconductor device
JPS57169245A (en) * 1981-03-23 1982-10-18 Western Electric Co Method of producing semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5724540A (en) * 1980-07-19 1982-02-09 Nippon Telegr & Teleph Corp <Ntt> Rinsing of through hole in semiconductor device
JPS57169245A (en) * 1981-03-23 1982-10-18 Western Electric Co Method of producing semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5041186A (en) * 1987-11-30 1991-08-20 Kabushiki Kaisha Toshiba Method for manufacturing compound semiconductor single crystals using a hydrogen monitor gas
JPH04302142A (en) * 1991-03-29 1992-10-26 Sharp Corp Manufactuer of semiconductor device
JPH05144775A (en) * 1991-11-18 1993-06-11 Sharp Corp Dry etching method
JPH0683279A (en) * 1991-12-31 1994-03-25 Hyundai Electron Ind Co Ltd Full page monitor
WO2002033741A1 (en) * 2000-10-18 2002-04-25 Sony Corporation Method for forming insulation film and method for manufacturing semiconductor device

Also Published As

Publication number Publication date
JP2786680B2 (en) 1998-08-13

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