JPH0352255A - Structure of circuit board - Google Patents
Structure of circuit boardInfo
- Publication number
- JPH0352255A JPH0352255A JP1188070A JP18807089A JPH0352255A JP H0352255 A JPH0352255 A JP H0352255A JP 1188070 A JP1188070 A JP 1188070A JP 18807089 A JP18807089 A JP 18807089A JP H0352255 A JPH0352255 A JP H0352255A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- circuit board
- substrate
- slits
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 54
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 16
- 238000007789 sealing Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 22
- 230000002787 reinforcement Effects 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims 1
- 238000005336 cracking Methods 0.000 abstract description 4
- 238000005452 bending Methods 0.000 abstract description 2
- 239000000565 sealant Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Structure Of Printed Boards (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、例えばＩＣカードのような携帯型電子機器に
用いられる極めて厚みの薄い回路基板に搭載される半導
体素子を外圧から保護するための回路基板の構造に関す
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention is a method for protecting semiconductor elements mounted on extremely thin circuit boards used in portable electronic devices such as IC cards from external pressure. Regarding the structure of circuit boards.
回路基板に搭載する半導体素子を外圧から保護するため
、前記半導体素子を密封してなる回路基板において、前
記半導体素子の搭載領域近傍にスリットを設けることに
よりなされる。この構造によれば、回路基板に外部から
力が作用したとき、前記スリット部に応力が集中するの
で半導体素子に作用する力が城少され、該素子のワレ，
クラツク等の発生を防止できるものである。In order to protect the semiconductor element mounted on the circuit board from external pressure, a slit is provided in the vicinity of the mounting area of the semiconductor element in the circuit board in which the semiconductor element is sealed. According to this structure, when a force is applied to the circuit board from the outside, the stress is concentrated on the slit portion, so that the force acting on the semiconductor element is reduced and the element is prevented from cracking.
This can prevent the occurrence of cracks, etc.
（従来の技術）
ＩＣカードのような薄型の携帯型電子機器に使用される
回路基板は、第２図ｔａ＋〜（Ｃｌに示すようにその薄
型の要求から搭載する素子を、いわゆるチンブオンボー
ドで実装する方法が採用されている．また、このような
薄型の携帯型電子機器では、携帯に際してたえず外部か
ら力を受ける機会にさらされており、外圧により半導体
素子ｌ４と封止剤１６よりなるパッケージ本体が湾曲す
る現象が起きるので、内藏された半導体素子４をこの外
圧から保護するため、回路基板１２に補強板１３を積層
し剛性を高める構造としていた。ここで、補強板１３と
いう表現を用いているが、機能的には前記半導体素子４
を封止剤１６を密封するための例えば封止枠１５を設け
た構造をとる場合もあるし、回路バクーン１９が形成さ
れた基板１２を兼ねて回路パターン１９と半導体素子１
４とがワイヤー１７で結線し、積層される場合もある．
〔発明が解決しようとする課題〕
前記のように、補強板１３を積層し剛性を高くしても応
力を受けたときに半導体素子４を含むバソケージが湾曲
する現象は避けられず、搭載された半導体素子４には依
然としてワレ，クランク等が発生していた。この理由を
第２図に従って説明する。第２図（＆）は封止枠ｌ５を
設けた補強板１３を基板１２とａ層した従来の回路基板
】の部分平面図であり、第２図（ｂｌは同図ｔａ＋のＡ
−Ａ断面図、第２図（ｃｌは同図（ｂｌである．回路基
板１１は下部から上方に向かって力Ｆが作用し、回路基
板１１が湾曲した状態を示している。同図において、力
Ｆにより、回路基板１１が湾曲したとき、基板１２に搭
載された半導体素子４を厚み方向に折り曲げようとする
力が作用するが加わる力Ｆが基板１２に搭載された半導
体素子４の剛性を超えたとき、半導体素子４にはクラッ
ク８やワレが発生することとなる。このように、従来の
回路基板１１の構造においては、作用する力Ｆが半導体
素子４の剛性を超えたとき、該素子はワレやクランクを
生じてしまうという問題点があった。(Prior Art) Circuit boards used in thin portable electronic devices such as IC cards are required to be thin, so as shown in Fig. In addition, such thin portable electronic devices are constantly exposed to external force when carried, and the package consisting of the semiconductor element 14 and the encapsulant 16 is damaged by the external pressure. Since the phenomenon of bending of the main body occurs, in order to protect the semiconductor element 4 housed inside from this external pressure, a reinforcing plate 13 is laminated on the circuit board 12 to increase the rigidity. Although it is used, functionally the semiconductor element 4
For example, a structure may be adopted in which a sealing frame 15 is provided for sealing the sealant 16, and the circuit pattern 19 and the semiconductor element 1 may also be used as the substrate 12 on which the circuit bag 19 is formed.
4 may be connected with wire 17 and stacked. [Problems to be Solved by the Invention] As mentioned above, even if the reinforcing plate 13 is laminated to increase the rigidity, the phenomenon that the bass cage containing the semiconductor element 4 bends when subjected to stress is unavoidable, and the mounted The semiconductor element 4 still had cracks, cracks, etc. The reason for this will be explained with reference to FIG. FIG. 2 (&) is a partial plan view of a conventional circuit board in which a reinforcing plate 13 provided with a sealing frame l5 is layered with a substrate 12, and FIG.
-A sectional view, FIG. 2 (cl is the same figure (bl). The circuit board 11 is shown in a state where a force F is applied upward from the bottom and the circuit board 11 is curved. In the same figure, When the circuit board 11 is bent by the force F, a force acts to bend the semiconductor element 4 mounted on the board 12 in the thickness direction, but the applied force F reduces the rigidity of the semiconductor element 4 mounted on the board 12 When the force F exceeds the rigidity of the semiconductor element 4, cracks 8 and cracks occur in the semiconductor element 4.In this way, in the structure of the conventional circuit board 11, when the applied force F exceeds the rigidity of the semiconductor element 4, The problem was that the element would crack or crack.
このような問題点を解決するために、本発明は補強板と
封止枠の周囲にスリソトを設けておき、スリットを設け
た補強板を基板に積層することにより、半導体にクラッ
ク．ワレを発生しないようにしたものである。In order to solve these problems, the present invention provides slits around the reinforcing plate and the sealing frame, and stacks the reinforcing plate with the slits on the substrate, thereby preventing cracks in the semiconductor. This is to prevent cracks from occurring.
回路基板に外力Ｆにより回路基板は湾曲を呈するが、補
強板に設けられたスリソト１８により、この部分のみ他
より剛性が低くなるため応力が集中する。従って回路基
板１ｌの湾曲形状はスリ・ノト部近傍は変形量が大きい
が、半導体素子４が搭載された領域部は変形量が少ない
。即ち、半導体素子４に加わる力は非常に少ないものと
なるため、該素子のワレ，クランク等の発生を防止する
ことができるものである。Although the circuit board exhibits curvature due to the external force F on the circuit board, stress is concentrated on this part because the stiffness of this part is lower than that of the other parts due to the slit 18 provided on the reinforcing plate. Therefore, in the curved shape of the circuit board 1l, the amount of deformation is large in the vicinity of the slot/notch portion, but the amount of deformation is small in the area where the semiconductor element 4 is mounted. That is, since the force applied to the semiconductor element 4 is extremely small, it is possible to prevent the element from cracking, cranking, etc.
つまり、回路基板を湾曲させる力が作用しても補強板に
設けられたスリット部に応力が集中するため、半導体素
子に作用する応力は分散される。In other words, even if a force that bends the circuit board is applied, the stress is concentrated on the slit portion provided in the reinforcing plate, so that the stress acting on the semiconductor element is dispersed.
よって、該素子は外圧から保護される。The element is thus protected from external pressure.
本発明の一実施例を第１図（ａ）、第１図［ｂｌに従っ
て説明する。材料厚み０．１ ｍ、銅箔厚み１８μｍの
両面銅張積層仮に所定の回路導電パターン１９を形或し
た基板１２に、半導体素子１４（サイズ５．４ｆｉＸ５
．４嶋｝を載置し、前記半導体素子４の電極と基板１２
の導体パターン１７をワイヤーボンデイング法によるワ
イヤー１７で接続した。一方、基板１２と同等の形状に
外形加工し、封止枠ｌ５として３．４ｍＸ３．４關のサ
イズにマド抜き加工し、更に、前記封止枠１５の周囲に
スリソ目８を封止枠１５の各辺に沿って４ケ所設けた補
強板ｌ３を用意し、前記基板１２に接着材を介して積層
した．更に、封止枠１５内に樹脂を充填し硬化させたの
ち本発明による回路基板１１を得た．なお、前記スリッ
ト１８の幅は１ｎとした。また、補強板１３の厚さはパ
ッケージの総厚の規制から、３ｆｌとした．補強板１３
の材質はガラスエボキシ樹脂を使用したが、その他、ト
リアジン変性樹脂、祇フェノール、紙エボキシその他の
複合材料、あるいはステンレス等の金属材料などもよい
。なお本発明ではスリットとしているが、スリットに限
るものではなく、要は搭載した素子に加わる応力を分散
し、素子を保護できる構造を提供できるものであればよ
い。また、スリ・７Ｆは部材を貫通して形威しても非貫
通で形威してもどちらでもよいのは勿論のことである。An embodiment of the present invention will be described with reference to FIG. 1(a) and FIG. 1[bl]. A semiconductor element 14 (size 5.4 fi x 5
．． 4) is mounted, and the electrodes of the semiconductor element 4 and the substrate 12 are placed.
The conductor patterns 17 were connected with wires 17 by a wire bonding method. On the other hand, the outer shape is processed to have the same shape as the substrate 12, and the sealing frame 15 is cut out to a size of 3.4m x 3.4m, and a slot 8 is formed around the sealing frame 15. Reinforcement plates l3 were prepared at four locations along each side of the substrate 12, and were laminated to the substrate 12 via an adhesive. Furthermore, after filling the sealing frame 15 with resin and curing it, a circuit board 11 according to the present invention was obtained. Note that the width of the slit 18 was 1n. In addition, the thickness of the reinforcing plate 13 was set to 3fl due to regulations regarding the total thickness of the package. Reinforcement plate 13
Although glass epoxy resin is used as the material, other materials such as triazine-modified resin, phenol, paper epoxy, other composite materials, or metal materials such as stainless steel may also be used. Although slits are used in the present invention, the present invention is not limited to slits, and any structure may be used as long as it can disperse the stress applied to the mounted elements and provide a structure that can protect the elements. Furthermore, it goes without saying that the pickpocket 7F may either penetrate the member or not.
第３図ｔａｇ， （ｂｌｔｃ＋に本発明の他の実施例の
数例を示す．第３図（ａｌは半導体４を封止してある封
止剤１６の封止枠１５の周辺に複数の穴２１を設けたも
のであり、第３図（ｂｌはスリット１Ｂを封止枠１５の
辺に沿ってＬ字状に設けたものであり、第３図ｆｃｌは
スリソト１８を封止枠１５の辺に対して９０″ずらして
Ｌ字状に設けたものである．
以上述べたとおり、基板に積層する補強板にスリットを
設ける構造としているが、補強板に限るものではなく、
密封実装した半導体素子の搭！！領域の近傍であれば、
回路基板を構威する部材のいずれに設けられていてもよ
く、スリソトが設けられる構戒部材を特定するものでは
ない．又、表裏に関係なく、スリットを設ける事は可能
である．その実施例を第４図ｆａｌ〜ｆｃｌに示す。第
４図（ａｌは補強板がないものの例で、基板１２にワイ
ヤ１７と結線した半導体４がｉｉ３！置されている。半
導体４は封止剤１６にて封止されている。スリットｌ８
は、半導体４を封止している封止剤１７の周辺に設けて
ある。Figure 3 tag, (bltc+ shows several examples of other embodiments of the present invention. 21 is provided, and FIG. 3 (bl shows the slit 1B provided in an L-shape along the side of the sealing frame 15, and FIG. 3 fcl shows the slit 18 provided along the side of the sealing frame 15. The reinforcing plate laminated on the board is provided with slits in an L-shape.
A tower of sealed semiconductor elements! ! If it is near the area,
It may be provided on any of the members that make up the circuit board, and does not specify the member that makes up the circuit board. Also, it is possible to provide slits regardless of the front or back sides. Examples thereof are shown in FIG. 4 fal to fcl. FIG. 4 (Al is an example without a reinforcing plate, and a semiconductor 4 connected to a wire 17 is placed on a substrate 12 ii3! The semiconductor 4 is sealed with a sealant 16. A slit l8
are provided around the sealant 17 that seals the semiconductor 4.
第４図（ｂｌは半導体４は基板１２にバンプ３６にて結
線される。第４図（ｂｌの実施例は基板１２上の封止剤
１６の周囲に凹部２０を設け、スリットの代用をしてい
るものである。第４図（Ｃｌの実施例は基板１２の裏側
に凹部２０を設けたものである。In the embodiment shown in FIG. 4 (bl), the semiconductor 4 is connected to the substrate 12 by bumps 36. In the embodiment shown in FIG. In the embodiment shown in FIG. 4 (Cl), a recess 20 is provided on the back side of the substrate 12.
更に、本実施例では基板に補強板を積層した構造として
示しているが、半導体素子を密封実装した単層の回路基
板であってもよく、この場合は前記半導体素子の搭載領
域近傍の前記回路基板にスリットを設けるものである．
〔発明の効果〕
本発明により、回路基板に搭載された半導体素子が外圧
から保護されるため、ＩＣカードのような薄型の携帯型
電子機器の信頼性向上に大きな効果がある。Furthermore, although this embodiment shows a structure in which a reinforcing plate is laminated on a substrate, it may be a single-layer circuit board on which a semiconductor element is hermetically mounted, and in this case, the circuit board near the mounting area of the semiconductor element may be A slit is provided in the substrate. [Effects of the Invention] According to the present invention, the semiconductor elements mounted on the circuit board are protected from external pressure, so there is a great effect on improving the reliability of thin portable electronic devices such as IC cards.
第１図ｆａｌは本発明による一実施例を示す回路基板の
部分平面図、第ｌ図ｆｂ）は同図（ａｌのＢ−Ｂ断面図
、第１図（Ｃｌは同図（ｂｌの回路基板の湾曲状態図、
第２図（ａｌは従来の回路基板の部分平面図、第２図ｆ
ｂ）は同図ｆａｌのＡ−Ａ断面図、第２図ｔｅｌは同図
（ｂｌの回路基板の湾曲状態図、第３図ｆａｔ乃至（Ｃ
ｌは本発明によるスリ７｝形状の他の実施例を示す部分
平面図、第４図ｔａ＋乃至ｔｅｌは本発明による回路基
板の構造の他の実施例を示す断面図である．
４ ・ ・
８ ・ ・
１１・ ・
１２・ ・
１３・
１５・ ・
１６・
１７・ ・
１８・ ・
１９・ ・
２０・ ・
２１・ ・
３６・ ・
・半導体素子
・クラック
・回路基板
・基板
・補強板
・封止枠
・封止剤
・ワイヤー
・スリット
・導体パターン
・凹部
・穴
・パンブFIG. 1 fal is a partial plan view of a circuit board showing an embodiment of the present invention, FIG. The curvature state diagram of
Figure 2 (al is a partial plan view of a conventional circuit board, Figure 2 f
b) is a sectional view taken along line A-A in the same figure fal, Figure 2 tel is a diagram of the curved state of the circuit board in the same figure (bl), and Figures 3 fat to (C
1 is a partial plan view showing another embodiment of the slit 7} shape according to the present invention, and FIGS. 4 ・ ・ 8 ・ ・ 11 ・ ・ 12 ・ 13 ・ 15 ・ 16 ・ 17 ・ 18 ・ 19 ・ 20 ・ 21 ・ 36 ・ ・ Semiconductor elements, cracks, circuit boards, substrates, reinforcing plates・Sealing frame, sealant, wire, slit, conductor pattern, recess, hole, punch
Claims (6)
ち、前記半導体素子を密封してなる回路基板において、
前記半導体素子の搭載領域近傍の前記回路基板にスリッ
トを設けたことを特徴とする回路基板の構造。(1) In a circuit board formed by placing a semiconductor element on a substrate, electrically connecting the semiconductor element, and then sealing the semiconductor element,
A structure of a circuit board, characterized in that a slit is provided in the circuit board near the mounting area of the semiconductor element.
ち、前記基板に補強板を積層するとともに前記半導体素
子を密封してなる回路基板において、前記半導体素子の
搭載領域近傍の前記補強板にスリットを設けたことを特
徴とする回路基板の構造。(2) In a circuit board in which a semiconductor element is placed on a substrate and electrically connected, a reinforcing plate is laminated on the substrate and the semiconductor element is hermetically sealed, the reinforcement near the mounting area of the semiconductor element is provided. A circuit board structure characterized by having slits in the board.
ち、前記半導体素子を密封してなる回路基板において、
前記半導体素子の搭載領域近傍の前記回路基板に凹部を
設けたことを特徴とする回路基板の構造。(3) In a circuit board formed by mounting a semiconductor element on a substrate, electrically connecting the semiconductor element, and then sealing the semiconductor element,
A structure of a circuit board, characterized in that a recess is provided in the circuit board near the mounting area of the semiconductor element.
ち、前記基板に補強板を積層するとともに前記半導体素
子を密封してなる回路基板において、前記半導体素子の
搭載領域近傍の前記捕強板に凹部を設けたことを特徴と
する回路基板の構造。(4) In a circuit board in which a semiconductor element is placed on a substrate and electrically connected, a reinforcing plate is laminated on the substrate and the semiconductor element is hermetically sealed; A circuit board structure characterized by having a recessed portion in a strong plate.
ち、前記半導体素子を密封してなる回路基板において、
前記半導体素子の搭載領域近傍の前記回路基板に穴を設
けたことを特徴とする回路基板の構造。(5) In a circuit board formed by placing a semiconductor element on a substrate, electrically connecting the semiconductor element, and then sealing the semiconductor element,
A structure of a circuit board, characterized in that a hole is provided in the circuit board near the mounting area of the semiconductor element.
ち、前記基板に補強板を積層するとともに前記半導体素
子を密封してなる回路基板において、前記半導体素子の
搭載領域近傍の前記補強板に穴を設けたことを特徴とす
る回路基板の構造。(6) In a circuit board formed by mounting a semiconductor element on a substrate and electrically connecting it, laminating a reinforcing plate on the substrate and sealing the semiconductor element, the reinforcement near the mounting area of the semiconductor element A circuit board structure characterized by having holes in the board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807089A JP2844085B2 (en) | 1989-07-20 | 1989-07-20 | Circuit board and method of mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18807089A JP2844085B2 (en) | 1989-07-20 | 1989-07-20 | Circuit board and method of mounting semiconductor element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0352255A true JPH0352255A (en) | 1991-03-06 |
| JP2844085B2 JP2844085B2 (en) | 1999-01-06 |
Family
ID=16217184
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18807089A Expired - Fee Related JP2844085B2 (en) | 1989-07-20 | 1989-07-20 | Circuit board and method of mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2844085B2 (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0540993U (en) * | 1991-10-23 | 1993-06-01 | 能美防災株式会社 | Fire alarm printed circuit board |
| JP2001357375A (en) * | 2000-06-14 | 2001-12-26 | Dainippon Printing Co Ltd | Ic carrier with planar frame body |
| JP2003044816A (en) * | 2001-07-31 | 2003-02-14 | Toppan Forms Co Ltd | Ic card |
| JP2005346559A (en) * | 2004-06-04 | 2005-12-15 | Nittoku Eng Co Ltd | Ic module and manufacturing method thereof |
| JP2008010615A (en) * | 2006-06-29 | 2008-01-17 | Matsushita Electric Ind Co Ltd | Flexible printed board, and electronic apparatus equipped therewith |
| JP2009182228A (en) * | 2008-01-31 | 2009-08-13 | Nitto Denko Corp | Wiring circuit board and its manufacturing method |
| US7665925B2 (en) | 2002-04-30 | 2010-02-23 | Max Co., Ltd. | Binder and binding device |
| JP2010283043A (en) * | 2009-06-02 | 2010-12-16 | Ngk Spark Plug Co Ltd | Wiring board with reinforcing material, and method of manufacturing the same |
| JP2011152502A (en) * | 2010-01-26 | 2011-08-11 | Panasonic Electric Works Co Ltd | Electrostatic atomizer |
| JP2012078983A (en) * | 2010-09-30 | 2012-04-19 | Toppan Printing Co Ltd | High intensity ic card |
| JP2013105921A (en) * | 2011-11-15 | 2013-05-30 | Nippon Telegr & Teleph Corp <Ntt> | Multilayer wiring board for semiconductor device |
| KR101486591B1 (en) * | 2008-01-31 | 2015-01-26 | 닛토덴코 가부시키가이샤 | Printed circuit board and method of manufacturing the same |
| JP2016131164A (en) * | 2015-01-13 | 2016-07-21 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| JP2017063077A (en) * | 2015-09-24 | 2017-03-30 | 本田技研工業株式会社 | Circuit board on which multipolar connector is mounted |
| EP3252679A1 (en) | 2016-06-02 | 2017-12-06 | Fujitsu Limited | Rfid tag |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4888875A (en) * | 1972-02-21 | 1973-11-21 | ||
| JPS5794954U (en) * | 1980-12-01 | 1982-06-11 |
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1989
- 1989-07-20 JP JP18807089A patent/JP2844085B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4888875A (en) * | 1972-02-21 | 1973-11-21 | ||
| JPS5794954U (en) * | 1980-12-01 | 1982-06-11 |
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|---|---|---|---|---|
| JPH0540993U (en) * | 1991-10-23 | 1993-06-01 | 能美防災株式会社 | Fire alarm printed circuit board |
| JP2001357375A (en) * | 2000-06-14 | 2001-12-26 | Dainippon Printing Co Ltd | Ic carrier with planar frame body |
| JP4580509B2 (en) * | 2000-06-14 | 2010-11-17 | 大日本印刷株式会社 | IC carrier with plate-like frame fixed to card mounting board |
| JP2003044816A (en) * | 2001-07-31 | 2003-02-14 | Toppan Forms Co Ltd | Ic card |
| US7665925B2 (en) | 2002-04-30 | 2010-02-23 | Max Co., Ltd. | Binder and binding device |
| JP2005346559A (en) * | 2004-06-04 | 2005-12-15 | Nittoku Eng Co Ltd | Ic module and manufacturing method thereof |
| JP2008010615A (en) * | 2006-06-29 | 2008-01-17 | Matsushita Electric Ind Co Ltd | Flexible printed board, and electronic apparatus equipped therewith |
| JP2009182228A (en) * | 2008-01-31 | 2009-08-13 | Nitto Denko Corp | Wiring circuit board and its manufacturing method |
| KR101486591B1 (en) * | 2008-01-31 | 2015-01-26 | 닛토덴코 가부시키가이샤 | Printed circuit board and method of manufacturing the same |
| KR101536360B1 (en) * | 2008-01-31 | 2015-07-13 | 닛토덴코 가부시키가이샤 | Printed circuit board and method of manufacturing the same |
| US8581110B2 (en) | 2008-01-31 | 2013-11-12 | Nitto Denko Corporation | Printed circuit board and method of manufacturing the same |
| JP2010283043A (en) * | 2009-06-02 | 2010-12-16 | Ngk Spark Plug Co Ltd | Wiring board with reinforcing material, and method of manufacturing the same |
| JP2011152502A (en) * | 2010-01-26 | 2011-08-11 | Panasonic Electric Works Co Ltd | Electrostatic atomizer |
| JP2012078983A (en) * | 2010-09-30 | 2012-04-19 | Toppan Printing Co Ltd | High intensity ic card |
| JP2013105921A (en) * | 2011-11-15 | 2013-05-30 | Nippon Telegr & Teleph Corp <Ntt> | Multilayer wiring board for semiconductor device |
| JP2016131164A (en) * | 2015-01-13 | 2016-07-21 | 日立オートモティブシステムズ株式会社 | Electronic control device |
| JP2017063077A (en) * | 2015-09-24 | 2017-03-30 | 本田技研工業株式会社 | Circuit board on which multipolar connector is mounted |
| EP3252679A1 (en) | 2016-06-02 | 2017-12-06 | Fujitsu Limited | Rfid tag |
| US10032104B2 (en) | 2016-06-02 | 2018-07-24 | Fujitsu Limited | RFID tag |
| WO2020032220A1 (en) * | 2018-08-10 | 2020-02-13 | ニッタ株式会社 | Ic tag |
| CN112449702A (en) * | 2018-08-10 | 2021-03-05 | 霓达株式会社 | IC tag |
| JPWO2020032220A1 (en) * | 2018-08-10 | 2021-08-12 | ニッタ株式会社 | IC tag |
| US11436464B2 (en) | 2018-08-10 | 2022-09-06 | Nitta Corporation | IC tag |
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| Publication number | Publication date |
|---|---|
| JP2844085B2 (en) | 1999-01-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |