JPH0351979Y2 - - Google Patents
Info
- Publication number
- JPH0351979Y2 JPH0351979Y2 JP18016782U JP18016782U JPH0351979Y2 JP H0351979 Y2 JPH0351979 Y2 JP H0351979Y2 JP 18016782 U JP18016782 U JP 18016782U JP 18016782 U JP18016782 U JP 18016782U JP H0351979 Y2 JPH0351979 Y2 JP H0351979Y2
- Authority
- JP
- Japan
- Prior art keywords
- heat dissipation
- dissipation board
- resin
- thickness
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000017525 heat dissipation Effects 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 33
- 239000011347 resin Substances 0.000 claims description 31
- 229920005989 resin Polymers 0.000 claims description 31
- 239000008188 pellet Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 7
- 238000000465 moulding Methods 0.000 description 5
- 229920002545 silicone oil Polymers 0.000 description 2
- 229920002799 BoPET Polymers 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【考案の詳細な説明】
技術分野
本考案は半導体装置に関し、特に半導体ペレツ
トを載置した放熱基板の全面を樹脂材にて被覆し
た絶縁型の半導体装置に関する。[Detailed Description of the Invention] Technical Field The present invention relates to a semiconductor device, and more particularly to an insulated semiconductor device in which the entire surface of a heat dissipation substrate on which semiconductor pellets are placed is covered with a resin material.
背景技術
中電力用乃至大電力用の半導体装置は半導体ペ
レツトが発生する熱を良好に放熱するため放熱基
板上に載置され、さらには外部放熱器に固定され
る。このような半導体装置の一例を第１図及び第
２図から説明する。図において１は平板状の放熱
基板で、１ａは外部放熱器等への取付用の穴を示
す。２は放熱基板１に載置した半導体ペレツト、
３は図示例では３本１組のリードで、平行配列さ
れ、中央のリード３ａの一端は半導体ペレツト２
近傍の放熱基板１端部に固定され、他のリード３
ｂ，３ｃの一端はそれぞれ半導体ペレツト２の両
側近傍に配置されている。４，４は半導体ペレツ
ト２上の電極（図示せず）と各リード３ｂ，３ｃ
とを電気的に接続した金属細線、５は半導体ペレ
ツト２を含む主要部分を被覆した樹脂材を示す。BACKGROUND TECHNOLOGY Semiconductor devices for medium to high power use are placed on a heat radiating substrate and further fixed to an external heat radiator in order to effectively radiate heat generated by semiconductor pellets. An example of such a semiconductor device will be explained with reference to FIGS. 1 and 2. In the figure, numeral 1 indicates a flat heat dissipation board, and 1a indicates a hole for attachment to an external heat dissipator or the like. 2 is a semiconductor pellet placed on a heat dissipation substrate 1;
In the illustrated example, 3 is a set of three leads arranged in parallel, and one end of the central lead 3a is connected to the semiconductor pellet 2.
It is fixed to the end of the nearby heat dissipation board 1 and connected to the other lead 3.
One ends of b and 3c are placed near both sides of the semiconductor pellet 2, respectively. 4, 4 are electrodes (not shown) on the semiconductor pellet 2 and respective leads 3b, 3c.
5 is a thin metal wire electrically connected to the semiconductor pellet 2, and 5 is a resin material covering the main portion including the semiconductor pellet 2.
この半導体装置は外部放熱器等に固定する際に
放熱基板１と半導体ペレツト２とが電気的に接続
されているため、第３図に示すように、放熱基板
１と放熱器６の間にマイカ板やマイラ板等の絶縁
薄板７を介在させ、穴１ａには絶縁ブツシユ８を
挿入した上でネジ９で固定する必要があり、また
熱伝導性を良好にするためには絶縁薄板７の両面
にシリコーンオイル等を充填しなくてはならず作
業性が悪かつた。 When this semiconductor device is fixed to an external heatsink or the like, the heatsink substrate 1 and the semiconductor pellet 2 are electrically connected, so as shown in FIG. It is necessary to interpose an insulating thin plate 7 such as a board or mylar plate, and insert an insulating bushing 8 into the hole 1a and fix it with screws 9. In addition, in order to improve thermal conductivity, both sides of the insulating thin plate 7 must be inserted. This required filling with silicone oil, etc., resulting in poor workability.
そのため、第４図に示すように放熱基板１の露
呈部を樹脂材５で被覆した絶縁型半導体装置が実
用されている。 Therefore, as shown in FIG. 4, an insulated semiconductor device in which the exposed portion of a heat dissipation substrate 1 is covered with a resin material 5 has been put into practical use.
これにより絶縁薄板７や絶縁ブツシユ８が省
け、また放熱器６への密着性も良いためシリコー
ンオイル等の充填材も省くことが可能となり取付
け作業性が良好となる。 As a result, the thin insulating plate 7 and the insulating bush 8 can be omitted, and the adhesion to the radiator 6 is also good, so it is also possible to omit a filler such as silicone oil, and the installation workability is improved.
この半導体装置は第５図に示す樹脂モールド装
置を用いて樹脂モールドされる。図において、１
０は下型で、ワイヤボンデイングを完了した半導
体装置組立体が装着されるキヤビテイ１１が設け
られている。１２はキヤビテイ１１から突設され
放熱基板１の穴１ａに間〓をもつて貫通する突出
体、１３は上型で、突出体１２と嵌合する穴１４
を有し、放熱基板１と間〓をもつてキヤビテイ１
１を閉塞する。リード３の中間部は上下型１０，
１３で締付けられ、放熱基板１はキヤビテイ１１
内に位置規正される。また１５はキヤビテイ１１
角部の上下型１０，１３の接合部に設けたゲート
を示す。 This semiconductor device is resin molded using a resin molding apparatus shown in FIG. In the figure, 1
Reference numeral 0 denotes a lower mold, which is provided with a cavity 11 into which a semiconductor device assembly that has undergone wire bonding is mounted. 12 is a protrusion that protrudes from the cavity 11 and passes through the hole 1a of the heat dissipation board 1 with a gap; 13 is an upper mold, and a hole 14 that fits into the protrusion 12;
It has a cavity 1 with a space between it and the heat dissipation board 1.
Block 1. The middle part of the lead 3 is the upper and lower mold 10,
13, and the heat dissipation board 1 is tightened by the cavity 11.
The position is adjusted within. Also, 15 is cavity 11
A gate provided at the joint between the upper and lower dies 10 and 13 at the corner is shown.
この樹脂モールドの際に、放熱基板１と上型１
３の間〓t1と放熱基板１とキヤビテイ１１側壁の
間〓t2を比較すると、t1は熱伝導性を良好にする
ため薄くする必要があつてt1≦t2に設定されてい
る。また間〓t1，t2に対応する巾w1，w2を比較す
るとw1≫w2に設定されている。そのためキヤビ
テイ１１に注入された樹脂は放熱基板１の側壁側
を通り易く、下型１０側キヤビテイに速く充填さ
れ上型１３側キヤビテイには不完全充填状態とな
ることがあつて、ボイドを生じこのような半導体
装置を放熱器に取付けると放熱基板１と放熱器と
は離れた状態でも沿面距離が短かくなつて、表面
汚染等により耐電圧が低下するという問題があつ
た。 During this resin molding, heat dissipation board 1 and upper mold 1
Comparing t 1 between 3 and t 2 between heat dissipation board 1 and side wall of cavity 11, t 1 needs to be thin to improve thermal conductivity, so it is set to t 1 ≦ t 2. . Furthermore, when comparing the widths w 1 and w 2 corresponding to the distances t 1 and t 2 , it is found that w 1 ≫w 2 . Therefore, the resin injected into the cavity 11 easily passes through the side wall of the heat dissipation board 1, and the cavity on the lower mold 10 side is quickly filled, and the cavity on the upper mold 13 side may be incompletely filled, resulting in voids. When such a semiconductor device is attached to a heat sink, there is a problem that the creepage distance becomes short even when the heat sink substrate 1 and the heat sink are separated, and the withstand voltage decreases due to surface contamination or the like.
そのため、第６図に示すように放熱基板１の上
下面で樹脂材５の厚みを薄くして、樹脂を放熱基
板１の上下面に均等に注入することもできるが、
ネジ締めの際に樹脂が欠け易いという欠点もあつ
た。 Therefore, as shown in FIG. 6, it is possible to reduce the thickness of the resin material 5 on the upper and lower surfaces of the heat dissipation board 1 and inject the resin evenly onto the upper and lower surfaces of the heat dissipation board 1.
Another drawback was that the resin was easily chipped when tightening the screws.
考案の開示
本考案は上記問題点に鑑み提案されたもので、
上記欠点を除き、放熱基板裏面の樹脂層にボイド
を生じなくした半導体装置を提供する。Disclosure of the invention This invention was proposed in view of the above problems.
The present invention provides a semiconductor device that eliminates the above drawbacks and eliminates voids in the resin layer on the back surface of a heat dissipation substrate.
本考案は、放熱基板上に載置した半導体ペレツ
トと、一端を半導体ペレツトの近傍に配置したリ
ードとを電気的に接続し、半導体ペレツトを含み
かつ放熱基板の全周を樹脂材にて被覆したものに
おいて、上記放熱基板の半導体ペレツトから離隔
した端部をペレツト載置面側に折曲すると共に折
曲部の上下端部における樹脂材の厚みを略等しく
したこを特徴とする。 The present invention electrically connects a semiconductor pellet placed on a heat dissipation board with a lead whose one end is placed near the semiconductor pellet, and covers the entire circumference of the heat dissipation board, including the semiconductor pellet, with a resin material. The heat dissipating substrate is characterized in that the end portion remote from the semiconductor pellet is bent toward the pellet mounting surface, and the thickness of the resin material at the upper and lower ends of the bent portion is approximately equal.
本考案は上記構成により次のような効果を有す
る。 The present invention has the following effects due to the above configuration.
１ 放熱基板の裏面に形成される樹脂層にボイド
の発生がなく、耐電圧特性が安定する。1. There are no voids in the resin layer formed on the back surface of the heat dissipation board, and the withstand voltage characteristics are stable.
２ 放熱基板が補強されネジ締等によつても樹脂
の剥離がない。2. The heat dissipation board is reinforced and the resin will not peel off even when tightening screws, etc.
考案を実施するための最良の形態
以下に本考案の一実施例を第７図及び第８図か
ら説明する。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 7 and 8.
図において、第４図と同一符号は同一物を示し
説明を省略する。第４図装置と相違するのは放熱
基板１６のみで、放熱基板１６のリード３が接続
された端部とは反対の端部を、半導体ペレツト２
載置面側に略90度折り曲げて折曲部１６ａを形成
したもので、１６ｂは取り付け用の穴を示す。 In the figure, the same reference numerals as in FIG. 4 indicate the same parts, and the explanation will be omitted. The only difference from the device shown in FIG. 4 is the heat dissipation board 16. The end of the heat dissipation board 16 opposite to the end to which the leads 3 are connected is connected to the semiconductor pellet 2.
It is bent approximately 90 degrees toward the mounting surface to form a bent portion 16a, and 16b indicates a hole for attachment.
これによれば、放熱基板１の裏面の樹脂層の厚
み、巾をそれぞれt1，w1とし、折曲部１６ａの側
面の樹脂層の厚み、巾をそれぞれt2，w2、折曲部
１６ａの端面部分（放熱基板１６の主面と平行な
部分）の樹脂層の厚み、巾をそれぞれt3，w3とす
れば、第５図に示す樹脂モールド装置を用い樹脂
モールドする際にt2＜t1としても、w2が長くなつ
た上t3≒t1あるいはt3＜t1とすることによつて放
熱基板１６裏面への樹脂の廻り込みを良好にでき
ボイドの発生を防止できる。ここで放熱基板１６
の主面はペレツト載置面と、この面と反対の面
（裏面）の２つの面があるが、折曲部１６ａの端
面はいずれか一方の主面に対して平行にすればよ
い。 According to this, the thickness and width of the resin layer on the back surface of the heat dissipation board 1 are respectively t 1 and w 1 , and the thickness and width of the resin layer on the side surface of the bent portion 16a are respectively t 2 and w 2 , and the bent portion If the thickness and width of the resin layer at the end surface portion (parallel to the main surface of the heat dissipation board 16) of the heat dissipation board 16a are t 3 and w 3 , respectively, then when resin molding is performed using the resin molding apparatus shown in FIG. Even if 2 < t 1 , w 2 becomes longer and by setting t 3 ≒ t 1 or t 3 < t 1 , it is possible to improve the circulation of the resin to the back surface of the heat dissipation board 16 and prevent the generation of voids. can. Here, the heat dissipation board 16
Although there are two main surfaces, a pellet mounting surface and a surface opposite to this surface (back surface), the end surface of the bent portion 16a may be made parallel to either one of the main surfaces.
また放熱基板１６は折曲部１６ａによつて補強
されるため変形し難く、ネジ締め等によつて樹脂
が剥離する虞れもなくすことができる。 Further, since the heat dissipation board 16 is reinforced by the bent portions 16a, it is difficult to deform, and there is no possibility that the resin will peel off due to screw tightening or the like.
尚、本考案は上記実施例のみに限定されること
なく、例えば第９図に示すように折曲部１６ａの
長さw2はネジ締めによつて放熱基板１６上面の
樹脂が欠けない程度の厚みが確保できる範囲で短
かくすることもできる。 It should be noted that the present invention is not limited to the above-mentioned embodiment . For example, as shown in FIG. It can also be shortened as long as the thickness can be ensured.
第１図は半導体装置の一例を示す透視平面図、
第２図は第１図Ａ−Ａ断面図、第３図は第１図装
置の取付例を示す要部側断面図、第４図は絶縁型
半導体装置の側断面図、第５図は第４図装置の樹
脂モールド装置の側断面図、第６図は絶縁型半導
体装置の変形例を示す側断面図、第７図は本考案
による半導体装置の一部透視平面図、第８図は第
７図Ｂ−Ｂ断面図、第９図は本考案の他の実施例
を示す部分断面側面図である。
２……半導体ペレツト、３……リード、５……
樹脂材、１６……放熱基板、１６ａ……折曲部、
１６ｂ……取付用の穴。
FIG. 1 is a perspective plan view showing an example of a semiconductor device;
2 is a sectional view taken along the line A-A in FIG. FIG. 4 is a side sectional view of the resin molding device of the apparatus, FIG. 6 is a side sectional view showing a modification of the insulated semiconductor device, FIG. 7 is a partially transparent plan view of the semiconductor device according to the present invention, and FIG. FIG. 7 is a sectional view taken along line B-B, and FIG. 9 is a partially sectional side view showing another embodiment of the present invention. 2... Semiconductor pellet, 3... Lead, 5...
Resin material, 16... heat dissipation board, 16a... bending part,
16b...Hole for mounting.
Claims (1)
なくとも一本のリードが連結された放熱基板上の
取付穴とリード間に半導体ペレツトを載置しリー
ドと半導体ペレツトとを電気的に接続して、リー
ドの一部及び半導体ペレツト、放熱基板の全面を
樹脂にて被覆しかつ放熱基板のペレツト載置面の
樹脂厚を反対面（裏面）の樹脂厚より厚く形成し
た半導体装置において、上記放熱基板のリード側
端部に対して反対側端部をペレツト載置面側に折
曲すると共にこの折曲部の放熱基板主面と平行な
部分の樹脂厚を放熱基板裏面の樹脂厚と略等しく
するとともに折曲部の取付用の穴に対して反対の
面側の樹脂厚を放熱基板裏面の樹脂厚より厚く形
成したことを特徴とする半導体装置。 A semiconductor pellet is placed between the mounting hole and the lead on a heat dissipation board which has a mounting hole and at least one lead of a set of multiple leads is connected, and the lead and the semiconductor pellet are electrically connected. In a semiconductor device in which a part of the lead, the semiconductor pellet, and the entire surface of the heat dissipation board are covered with resin, and the thickness of the resin on the pellet mounting surface of the heat dissipation board is made thicker than the resin thickness on the opposite surface (back surface), The end of the heat dissipation board opposite to the lead side end is bent toward the pellet mounting surface, and the resin thickness at the bent portion parallel to the main surface of the heat dissipation board is referred to as the resin thickness on the back side of the heat dissipation board. A semiconductor device characterized in that the thickness of the resin on the side opposite to the mounting hole of the bent part is made equal to the thickness of the resin on the back side of the heat dissipation board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18016782U JPS5983052U (en) | 1982-11-29 | 1982-11-29 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18016782U JPS5983052U (en) | 1982-11-29 | 1982-11-29 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5983052U JPS5983052U (en) | 1984-06-05 |
| JPH0351979Y2 true JPH0351979Y2 (en) | 1991-11-08 |
Family
ID=30390716
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18016782U Granted JPS5983052U (en) | 1982-11-29 | 1982-11-29 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5983052U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02290032A (en) * | 1989-12-14 | 1990-11-29 | Hitachi Ltd | Manufacture of resin mold type semiconductor device |
-
1982
- 1982-11-29 JP JP18016782U patent/JPS5983052U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5983052U (en) | 1984-06-05 |
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