JPH0350418B2 - - Google Patents
Info
- Publication number
- JPH0350418B2 JPH0350418B2 JP56041324A JP4132481A JPH0350418B2 JP H0350418 B2 JPH0350418 B2 JP H0350418B2 JP 56041324 A JP56041324 A JP 56041324A JP 4132481 A JP4132481 A JP 4132481A JP H0350418 B2 JPH0350418 B2 JP H0350418B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxidation
- forming
- etching
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000003647 oxidation Effects 0.000 claims description 20
- 238000007254 oxidation reaction Methods 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000001681 protective effect Effects 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 239000012212 insulator Substances 0.000 claims 1
- 238000000034 method Methods 0.000 description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000002250 progressing effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XWROUVVQGRRRMF-UHFFFAOYSA-N F.O[N+]([O-])=O Chemical compound F.O[N+]([O-])=O XWROUVVQGRRRMF-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
- Local Oxidation Of Silicon (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は、半導体装置の製造方法、より詳しく
は、実質的に横方向に進むことなく縦方向にのみ
エツチングが進む異方性ドライエツチング
（RIPE型ドライエツチング）の技術を利用し、将
来形成されるべき素子用の不純物拡散領域に衝突
することのないように自己整合（セルフアライ
ン）でチヤネルカツト領域を形成する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to an anisotropic dry etching (RIPE dry etching) technique in which etching progresses only in the vertical direction without substantially progressing in the lateral direction. This invention relates to a method of forming a channel cut region in a self-aligned manner so as to prevent it from colliding with an impurity diffusion region for an element to be formed in the future.
MIS型半導体装置の一例として、第１図に示さ
れるn-チヤネルMISトランジスタ素子の断面図
を参照すると、はｐ形シリコン基板、２，２′は
二酸化シリコンから成る絶縁膜、３はゲート電
極、４は例えばりん・シリケート・ガラス
（PSG）から成る絶縁層、５はゲート・コンタク
ト、６と７はそれぞれソースとドレーン用のコン
タクト、n+はn+拡散層、８はフイールド酸化膜、
１５はp+拡散層である。 Referring to the cross-sectional view of an n - channel MIS transistor element shown in FIG. 1 as an example of a MIS type semiconductor device, numeral 2 is a p-type silicon substrate, 2 and 2' are insulating films made of silicon dioxide, 3 is a gate electrode, 4 is an insulating layer made of, for example, phosphorous silicate glass (PSG), 5 is a gate contact, 6 and 7 are contacts for source and drain, respectively, n + is an n + diffusion layer, 8 is a field oxide film,
15 is a p + diffusion layer.
かゝる半導体素子の高速化を実現するために
は、基板と素子との接合容量を減少させることが
要求され、またかゝる素子を高耐圧化するために
は、n+拡散層の耐圧を上げることが必要で、そ
のために当該n+拡散層に衝突しないようチヤネ
ルカツト領域を設けることが必要である。図示の
p+拡散層はかゝる要求を満たすものである。 In order to increase the speed of such semiconductor devices, it is necessary to reduce the junction capacitance between the substrate and the device, and to increase the breakdown voltage of such devices, it is necessary to reduce the breakdown voltage of the n + diffusion layer. Therefore, it is necessary to provide a channel cut region so as not to collide with the n + diffusion layer. illustrated
The p + diffusion layer satisfies these requirements.
従来技術においてかゝるチヤネルカツト領域を
形成するためには、マスクを１枚余分に必要と
し、そのための特別の工程が要求された。 In the prior art, in order to form such a channel cut region, an extra mask was required and a special process was required.
本発明の目的は、上記の如きそのためのマスク
を必要とすることなくチヤネルカツト領域を形成
し、接合容量を減少し、拡散層の耐圧を上げるこ
とにより、高速かつ高耐圧の半導体装置を提供す
ることにある。その目的を実現するために、半導
体基板上に耐酸化マスク膜パターンを形成する工
程、該耐酸化マスク膜パターンを覆う保護膜を形
成する工程、該保護膜上に該保護膜とは異なる半
導体又は絶縁物若しくは金属から成る膜を被着形
成する工程、該膜を異方性ドライエツチングによ
つて該保護膜が露出するまで全面エツチングして
前記耐酸化マスク膜パターンの側縁部分にほぼ該
膜の成長膜に等しい幅に残存させる側壁膜を形成
する工程、該耐酸化マスク膜パターンとその側縁
部分に残存させた側壁膜とをマスクとしてチヤネ
ルカツト領域に対応する不純物導入領域を画定し
形成する工程、前記側壁膜を選択的に除去した後
に耐酸化マスク膜をマスクとする選択酸化により
酸化膜を形成する工程、を含むことを特徴とする
半導体装置の製造方法を提供するもので、実質的
に横方向に進むことなく縦方向にのみエツチング
が進む異方性エツチング（RIPE型エツチング）
の技術を利用し、将来形成されるべき例えばn+
領域に衝突することのないよう十分離して、セル
フアラインでチヤネルカツト領域を形成するもの
である。 An object of the present invention is to provide a high-speed and high-voltage semiconductor device by forming a channel cut region without requiring a mask as described above, reducing the junction capacitance, and increasing the breakdown voltage of the diffusion layer. It is in. In order to achieve this purpose, a process of forming an oxidation-resistant mask film pattern on a semiconductor substrate, a process of forming a protective film covering the oxidation-resistant mask film pattern, and a process of forming a semiconductor or A step of depositing and forming a film made of an insulating material or a metal, etching the entire surface of the film by anisotropic dry etching until the protective film is exposed, and etching the film almost on the side edge portions of the oxidation-resistant mask film pattern. a step of forming a sidewall film remaining with a width equal to the grown film; using the oxidation-resistant mask film pattern and the sidewall film left on the side edge portions as a mask to define and form an impurity introduction region corresponding to the channel cut region; The present invention provides a method for manufacturing a semiconductor device, comprising: a step of selectively removing the sidewall film and then forming an oxide film by selective oxidation using an oxidation-resistant mask film as a mask; Anisotropic etching in which etching progresses only in the vertical direction without progressing in the horizontal direction (RIPE type etching)
For example, n + should be formed in the future using the technology of
A channel cut region is formed by self-alignment at a sufficient distance so as not to collide with the region.
以下、本発明の方法の実施例を、添付図面を参
照して説明する。 Embodiments of the method of the present invention will be described below with reference to the accompanying drawings.
第２図は本発明の方法を実施する工程の断面図
である。先ずそのａに示されるように、ｐ形シリ
コン基板１上に通常の熱酸化法を用いて下地とな
るSiO2の絶縁膜１１を例えば500〔Å〕の膜厚に
形成し、全面にシリコンナイトライド（Si3N4）
膜を成長し、マスクを使用してSi3N4膜のみをパ
ターニングし、このために用いたレジストを除去
してSi3N4膜１２を図示の如くに形成する。 FIG. 2 is a cross-sectional view of the process of carrying out the method of the invention. First, as shown in part a, an insulating film 11 of SiO 2 as a base is formed to a thickness of, for example, 500 [Å] on a p-type silicon substrate 1 using a normal thermal oxidation method, and then silicon night is coated on the entire surface. Ride (Si 3 N 4 )
A film is grown, only the Si 3 N 4 film is patterned using a mask, and the resist used for this is removed to form the Si 3 N 4 film 12 as shown.
次に、そのｂに示されるように、化学気相成長
法（CVD）でSiO2を被着してブロツク酸化膜１
３を数百〜数千〔Å〕の膜厚に形成する。ブロツ
ク酸化膜１３は後に説明するRIPE型エツチング
及びポリシリコンの全面除去の際にブロツクの役
目を果たす。 Next, as shown in part b, SiO 2 is deposited by chemical vapor deposition (CVD) to form a block oxide film 1.
3 is formed to a thickness of several hundred to several thousand [Å]. The block oxide film 13 serves as a block during RIPE etching and complete removal of polysilicon, which will be described later.
続いて、そのｃに示されるように、例えば多結
晶シリコン（ポリシリコン）膜を１〔μm〕の膜厚
に成長させてポリシリコン膜１４を形成する。ポ
リシリコン以外にも、ブロツク酸化膜１３として
はRIPE型のエツチングにおけるエツチング速度
とエツチング液（エツチヤント）とが異なるその
他の材料をも使用しうる。 Subsequently, as shown in c, for example, a polysilicon film 14 is formed by growing a polycrystalline silicon (polysilicon) film to a thickness of 1 [μm]. In addition to polysilicon, other materials may be used as the block oxide film 13, which differ in the etching rate and etching solution (etchant) used in RIPE etching.
こゝで、RIPE型ドライエツチングを適用して
ポリシリコン膜厚１〔μm〕分だけ除去すると、
Si3N4膜１２の上方部分のポリシリコンは除去さ
れるが、SI2N4膜１２段部に成長したポリシリコ
ンは縦（垂直）方向には数〔μm〕の厚みを有す
るので、１〔μm〕の膜厚分だけの幅で段部に沿つ
てポリシリコンは残存するようになる。この結果
同図ｄに示される構造が得られる。ポリシリコン
よりもSiO2の方がエツチング速度が大であるか
ら、図で矢印で示すブロツク酸化膜１３は若干エ
ツチングされる。このことは、次になされるチヤ
ネルカツト領域拡散のための例えば高濃度ほう素
（B+）のイオン注入に関しても意義がある。ブロ
ツク酸化膜１３の本来の機能は、RIPEエツチン
グの際に基板シリコンが露出してしまわないよう
にすることにあり、それにより後のポリシリコン
全面除去時に基板シリコンのエツチングを防ぐも
のである。 Now, if we apply RIPE dry etching to remove 1 [μm] of polysilicon film thickness,
The polysilicon in the upper part of the Si 3 N 4 film 12 is removed, but since the polysilicon grown in the step part of the SI 2 N 4 film 12 has a thickness of several [μm] in the vertical (vertical) direction, The polysilicon remains along the stepped portion with a width corresponding to the film thickness of [μm]. As a result, the structure shown in Figure d is obtained. Since the etching rate of SiO 2 is higher than that of polysilicon, the block oxide film 13 shown by the arrow in the figure is slightly etched. This is also significant for the subsequent ion implantation of, for example, high concentration boron (B + ) for channel cut region diffusion. The original function of the block oxide film 13 is to prevent the substrate silicon from being exposed during RIPE etching, thereby preventing etching of the substrate silicon when the entire surface of polysilicon is removed later.
次に、同図ｅに示されるように、矢印の方向
に、例えば30KeVのエネルギーでB+のイオン注
入をなすと、そのｆに示されるようなP+領域１
５（チヤネルカツト領域）が形成される。この場
合、B+イオン注入箇所ではブロツク酸化膜１３
は薄くなつているので、注入エネルギーを大きく
する等の特別の配慮は不要となる。 Next, as shown in e of the figure, B + ions are implanted in the direction of the arrow at an energy of, for example, 30 KeV, resulting in a P + region 1 as shown in f.
5 (channel cut area) is formed. In this case, a block oxide film 13 is formed at the B + ion implantation location.
Since it is thinner, there is no need for special considerations such as increasing the implantation energy.
引続き、ポリシリコン膜１４をエツチング除去
して、Si3N4膜１２を残す。ポリシリコンは例え
ば硝酸−弗化水素系（HNO3−HF）のエツチヤ
ントを用いるウエツト・エツチングで除去する。
この際ブロツク酸化膜１３が基板シリコンのエツ
チングを防止する。更に選択酸化法で厚いフイー
ルド酸化膜８を形成し、Si3N4膜１２を除くと、
同図ｇに示される構造が得られる。 Subsequently, the polysilicon film 14 is removed by etching, leaving the Si 3 N 4 film 12. The polysilicon is removed by wet etching using, for example, a nitric acid-hydrogen fluoride (HNO 3 -HF) etchant.
At this time, the block oxide film 13 prevents the substrate silicon from being etched. Furthermore, a thick field oxide film 8 is formed using a selective oxidation method and the Si 3 N 4 film 12 is removed.
The structure shown in figure g is obtained.
それ以後通常の技法で第１図に示される如き半
導体装置を形成する。つまり、前記した第２図ｆ
とｇに示される工程において、Si3N4膜１２の下
には、半導体装置のn+拡散領域が形成されるべ
き部分が熱酸化工程に影響されることなく残さ
れ、その部分から十分離れたところにあるp+領
域１５の上に十分に厚いフイールド酸化膜８が形
成され、しかもかゝる位置関係は、特別のマスク
を用いることなく、セルフアラインによつて実現
されるのである。 Thereafter, a semiconductor device as shown in FIG. 1 is formed using conventional techniques. In other words, the above-mentioned figure 2 f
In the steps shown in and g, the part where the n + diffusion region of the semiconductor device is to be formed is left unaffected by the thermal oxidation process under the Si 3 N 4 film 12, and is kept sufficiently far away from that part. A sufficiently thick field oxide film 8 is formed on the p + region 15 located at a certain location, and such positional relationship is realized by self-alignment without using a special mask.
以上の説明と図面の参照から理解される如く、
フイールド酸化膜の下にはp+領域が形成されて
いるため、ｐ形シリコン基板に対する関係におい
て、第１図に示される本発明の方法を用いた半導
体装置では、ソース・ドレーン領域の如き素子用
のｎ形拡散領域に寄生する接合容量が減少されそ
のことは当該半導体装置の高速化に寄与する。 As understood from the above description and reference to the drawings,
Since a p + region is formed under the field oxide film, in relation to a p-type silicon substrate, in a semiconductor device using the method of the present invention shown in FIG. The parasitic junction capacitance in the n-type diffusion region of the semiconductor device is reduced, which contributes to speeding up the semiconductor device.
また、p+領域１５はn+領域との関係において
チヤネルカツト領域として働き、上記したよう
に、p+領域１５はセルフアラインによつてn+領
域から十分に分離して正確に形成されるので、第
１図の半導体素子においてはn+領域の耐圧を上
げることができ、そのことは高耐圧素子が容易に
形成されるという効果がある。 In addition, the p + region 15 acts as a channel cut region in relation to the n + region, and as described above, the p + region 15 is accurately formed sufficiently separated from the n + region by self-alignment. In the semiconductor device shown in FIG. 1, the breakdown voltage of the n + region can be increased, which has the effect that a high breakdown voltage device can be easily formed.
上記実施例では、RIPEエツチングによつて耐
酸化マスク膜（Si3N4膜）縁部分の段差部に残留
させてチヤネルカツト領域を画定するための膜材
料として、ポリシリコンを例示したが、これは他
の絶縁膜や金属膜で置換え得る。またチヤネルカ
ツト領域はイオン注入法によらずに、上記耐酸化
マスク膜の縁部分に残留させた膜をマスクとして
下地酸化膜に選択拡散窓開きを行ない、通常の不
純物拡散法を適用して実施してもよい。更に前記
ブロツク酸化膜はRIPEエツチング等のエツチン
グ工程中に下地への影響を防ぐためのものであつ
て必須のものではなく、エツチング性を配慮すれ
ば他種の絶縁膜を用いることもできる。要する
に、本発明では耐酸化マスク膜パターンの縁にあ
る段差を利用し、この上に被着形成した膜に対し
異方性ドライエツチングを適用することによつ
て、上記縁部分のみにこの膜を残留させ、かくし
て残存された膜と上記耐酸化マスク膜パターンを
マスクとしてチヤネルカツト領域を画定すること
にある。素子用のn+形拡散領域は耐酸化マスク
膜を利用して埋設形成されるフイールド酸化膜下
には形成されないため、チヤネルカツト領域とは
ほゞ上記縁部分に残存させた膜の幅（即ち被着膜
厚にほゞ等しい）だけ離間されることになる点が
重要である。これにより上述の如く低寄生接合容
量、高耐圧の素子を作成でき、しかもそのための
特別なフオトプロセスは必要ないという効果が得
られるものである。 In the above embodiment, polysilicon was used as an example of the film material to be left on the step part at the edge of the oxidation-resistant mask film (Si 3 N 4 film) to define the channel cut region by RIPE etching. It can be replaced with other insulating films or metal films. In addition, the channel cut region is formed by selectively opening a diffusion window in the base oxide film using the film left at the edge of the oxidation-resistant mask film as a mask, and applying the usual impurity diffusion method. It's okay. Further, the block oxide film is used to prevent the influence on the underlying layer during an etching process such as RIPE etching, and is not essential, and other types of insulating films may be used if etching properties are taken into consideration. In short, in the present invention, by utilizing the step at the edge of the oxidation-resistant mask film pattern and applying anisotropic dry etching to the film deposited thereon, the film is etched only at the edge. The remaining film and the oxidation-resistant mask film pattern are used as a mask to define a channel cut region. Since the n + -type diffusion region for the device is not formed under the field oxide film that is buried using the oxidation-resistant mask film, the channel cut region is defined as the width of the film left at the edge (i.e., the width of the film covered). Importantly, they will be spaced apart by a distance (approximately equal to the deposition thickness). As a result, an element with low parasitic junction capacitance and high breakdown voltage can be produced as described above, and a special photo process is not required for this purpose.
第１図は本発明の方法を用いて完成された半導
体装置の断面図、第２図は本発明の方法を実施す
る工程の断面図である。
図中、１はｐ形シリコン基板、２，２′はSiO2
絶縁膜、３はゲート電極、４は絶縁層、５はゲー
ト・コンタクト、６，７はソース・ドレーン・コ
ンタクト、８はフイールド酸化膜、１１はSiO2
絶縁膜、１２はSi3N4膜、１３はブロツク酸化
膜、１４はポリシリコン膜、１５はp+拡散層
（チヤネルカツト領域）を示す。
FIG. 1 is a cross-sectional view of a semiconductor device completed using the method of the present invention, and FIG. 2 is a cross-sectional view of a step of implementing the method of the present invention. In the figure, 1 is a p-type silicon substrate, 2 and 2' are SiO 2
Insulating film, 3 is a gate electrode, 4 is an insulating layer, 5 is a gate contact, 6 and 7 are source/drain contacts, 8 is a field oxide film, 11 is SiO 2
12 is a Si 3 N 4 film, 13 is a block oxide film, 14 is a polysilicon film, and 15 is a p + diffusion layer (channel cut region).
Claims (1)
成する工程、該耐酸化マスク膜パターンを覆う保
護膜を形成する工程、該保護膜上に該保護膜とは
異なる半導体又は絶縁物若しくは金属から成る膜
を被着形成する工程、該膜を異方性ドライエツチ
ングによつて該保護膜が露出するまで全面エツチ
ングして前記耐酸化マスク膜パターンの側縁部分
にほぼ該膜の成長膜厚に等しい幅に残存させる側
壁膜を形成する工程、該耐酸化マスク膜パターン
とその側縁部分に残存させた側壁膜とをマスクと
してチヤネルカツト領域に対応する不純物導入領
域を画定し形成する工程、 前記側壁膜を選択的に除去した後に耐酸化マス
ク膜をマスクとする選択酸化により酸化膜を形成
する工程、を含むことを特徴とする半導体装置の
製造方法。[Scope of Claims] 1. A step of forming an oxidation-resistant mask film pattern on a semiconductor substrate, a step of forming a protective film covering the oxidation-resistant mask film pattern, and a step of forming a semiconductor or an insulator different from the protective film on the protective film. A step of depositing and forming a film made of material or metal, etching the entire surface of the film by anisotropic dry etching until the protective film is exposed, so that almost all of the film is formed on the side edge portions of the oxidation-resistant mask film pattern. A step of forming a sidewall film to remain with a width equal to the thickness of the grown film, using the oxidation-resistant mask film pattern and the sidewall film left at the side edges as a mask to define and form an impurity introduction region corresponding to the channel cut region. A method of manufacturing a semiconductor device, comprising: forming an oxide film by selective oxidation using an oxidation-resistant mask film as a mask after selectively removing the sidewall film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4132481A JPS57155747A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4132481A JPS57155747A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57155747A JPS57155747A (en) | 1982-09-25 |
| JPH0350418B2 true JPH0350418B2 (en) | 1991-08-01 |
Family
ID=12605337
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4132481A Granted JPS57155747A (en) | 1981-03-20 | 1981-03-20 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57155747A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5347782A (en) * | 1976-10-13 | 1978-04-28 | Hitachi Ltd | Production of semiconductor device |
-
1981
- 1981-03-20 JP JP4132481A patent/JPS57155747A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5347782A (en) * | 1976-10-13 | 1978-04-28 | Hitachi Ltd | Production of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57155747A (en) | 1982-09-25 |
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