KR0186186B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR0186186B1 KR0186186B1 KR1019950046367A KR19950046367A KR0186186B1 KR 0186186 B1 KR0186186 B1 KR 0186186B1 KR 1019950046367 A KR1019950046367 A KR 1019950046367A KR 19950046367 A KR19950046367 A KR 19950046367A KR 0186186 B1 KR0186186 B1 KR 0186186B1
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- insulating film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000000151 deposition Methods 0.000 claims abstract description 7
- 150000002500 ions Chemical class 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 5
- 239000002184 metal Substances 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
본 발명은 반도체소자의 제조방법에 관한 것으로, 그레이디드(graded)한 측벽을 이용하여 채널영역부근에 얕은 소오스/드레인 접합을 형성하므로써 단채널효과를 감소시키고, 공정을 단순화하여 고집적소자에 적합하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for fabricating a semiconductor device, wherein a shallow source / drain junction is formed near a channel region using graded sidewalls to reduce short channel effects and simplify the process so as to be suitable for highly integrated devices. It is.
본 발명에 따른 반도체소자의 제조방법은 반도체기판을 준비하는 단계; 상기 반도체 간판상에 제1절연막과 상기 제1절연막 위에 도전층 및 상기 도전층 위에 제2절연막을 차례로 증착하는 단계; 상기 제2절연막과 도전층 및 제1절연막을 선택적으로 제거하여 캡게이트 절연막과 게이트전극 및 게이트 절연막을 형성하는 단계; 상기 캡게이트 절연막의 상부 및 측면과, 게이트 전극 및 게이트 절연막의 측면을 포함한 반도체기판의 노출된 표면에 제3절연막과 상기 제3절연막 위에 제4절연막을 차례로 증착하는 단계; 상기 제4절연막을 상기 제3절연막 측벽에만 남도록 선택적으로 제거하여 상기 캡게이트 절연막과 게이트 전극 및 게이트 절연막 측면에 측벽을 형성하는 단계; 상기 측벽을 포함한 캡게이트 절연막을 마스크로 하여 상기 반도체기판에 불순물이온을 주입하여 제1 및 제2불순물영역을 형성하는 단계를 포함하여 이루어진다.Method of manufacturing a semiconductor device according to the present invention comprises the steps of preparing a semiconductor substrate; Sequentially depositing a first insulating film on the semiconductor signboard, a conductive layer on the first insulating film, and a second insulating film on the conductive layer; Selectively removing the second insulating layer, the conductive layer, and the first insulating layer to form a capgate insulating layer, a gate electrode, and a gate insulating layer; Depositing a third insulating film and a fourth insulating film over the third insulating film on the exposed surface of the semiconductor substrate including the top and side surfaces of the capgate insulating film and the side surface of the gate electrode and the gate insulating film; Selectively removing the fourth insulating layer so that only the sidewalls of the third insulating layer remain to form sidewalls on the cap gate insulating layer, the gate electrode, and sidewalls of the gate insulating layer; And implanting impurity ions into the semiconductor substrate using the capgate insulating layer including the sidewalls as a mask to form first and second impurity regions.
Description
제1도(a) ~ (e)는 종래 반도체소자의 공정단면도.1 (a) to (e) are process cross-sectional views of a conventional semiconductor device.
제2도(a) ~ (f)는 본 발명에 따른 반도체소자의 공정단면도.2 (a) to (f) are process cross-sectional views of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
11 : 반도체 기판 12 : 제1절연막11 semiconductor substrate 12 first insulating film
12a : 게이트 절연막 13 : 금속층12a: gate insulating film 13: metal layer
13a : 게이트전극 14 : 제2절연막13a: gate electrode 14: second insulating film
14a : 캡게이트 절연막 15 : 제3절연막14a: capgate insulating film 15: third insulating film
15a : 측벽 16 : 제4절연막15a: side wall 16: fourth insulating film
16a : 임시 측벽 17, 18 : 불순물영역16a: temporary sidewalls 17, 18: impurity regions
17a, 18a : LDD영역17a, 18a: LDD area
본 발명은 반도체소자에 관한 것올, 특히 단채널효과를 감소시키고, 공정을 단순화 시킬 수 있는 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of reducing short channel effects and simplifying a process.
종래의 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a conventional method for manufacturing a semiconductor device is as follows.
제1도(a) ~ (e)는 본 발명에 따른 반도체소자의 제조공정 단면도이다.1 (a) to (e) are cross-sectional views of a manufacturing process of a semiconductor device according to the present invention.
종래 반도체소자의 제조방법은, 먼저 제1도(a)에 도시된 바와 같이, 반도체기판(1)을 준비하고, 상기 반도체기판(1)상세 게이트 절연막(2)과 상기 게이트 절연막(2)상에 금속층(3)을 차례로 증착한다.In the conventional method of manufacturing a semiconductor device, first, as shown in FIG. 1A, a semiconductor substrate 1 is prepared, and the semiconductor substrate 1 is formed on the detailed gate insulating film 2 and the gate insulating film 2. The metal layer 3 is deposited in this order.
이어서, 제1도(b)에 도시된 바와 같이, 사진석판술(photolithography) 및 사진식각 공정에 의해 상기 금속층(3)을 선택적으로 제거하여 게이트전극(3a)을 형성한다.Subsequently, as shown in FIG. 1B, the metal layer 3 is selectively removed by photolithography and photolithography to form the gate electrode 3a.
그 다음 제1c도에 도시된 바와 같이, 상기 게이트전극(3a)을 포한한 상기 게이트 절연막(2)의 노출된 표면에 도우프드 실리게이트 글라스(Doped Silicated Glass)를 증착하여 절연막(4)을 형성한다.Then, as shown in FIG. 1C, an insulating film 4 is formed by depositing doped Silicated Glass on the exposed surface of the gate insulating film 2 including the gate electrode 3a. do.
이어서 제1도(d)에 도시된 바와 같이, 상기 절연막(4)을 약 1000 ~ 1050℃ 온도에서 일정시간동안 열처리공정을 통해 리플로우(Reflow)하여 상기 게이트전극(3a)측면에 그레이디드(Graded)한 측벽(4a)을 형성한다.Subsequently, as illustrated in FIG. 1D, the insulating film 4 is reflowed through a heat treatment process at a temperature of about 1000 to 1050 ° C. for a predetermined time, and thus graded on the side of the gate electrode 3a is formed. Graded sidewalls 4a are formed.
이때, 상기 측벽(4a) 형성시에 상기 게이트전극(3a)의 상측 모서리부분이 제거된다.At this time, the upper edge portion of the gate electrode 3a is removed when the sidewall 4a is formed.
그 다음 제1도(e)에 도시된 바와 같이, 상기 측벽(4a)을 포함한 게이트전극(3a)을 마스크로 하여 상기 반도체기판(1)에 불순물이온을 주입하여 제1 및 제2불순물영역(5)(6)들을 형성한다.Next, as shown in FIG. 1E, impurity ions are implanted into the semiconductor substrate 1 using the gate electrode 3a including the sidewalls 4a as a mask so that the first and second impurity regions ( 5) (6).
이때 상기 제1 및 제2불순물영역(5)(6)들은 채널부근까지 그레이디스(graded)하게 분포한다.In this case, the first and second impurity regions 5 and 6 are distributed in a gradual manner to the vicinity of the channel.
상기와 같이 종래 반도체소자의 제조방법에 있어서는 다음과 같은 문제점이 있다.As described above, the conventional method of manufacturing a semiconductor device has the following problems.
첫째, 종래 반도체소자의 제조방법에 있어서는 약 1000 ~ 1050℃의 고온에서 리플로우(Reflow) 공정을 수행하기 때문에 채널도핑 프로파일(Channel Doping Profile)의 조정이 어려우므로 제작수율이 떨어진다.First, in the manufacturing method of the conventional semiconductor device, since the reflow process is performed at a high temperature of about 1000 to 1050 ° C., the channel doping profile is difficult to adjust, and thus the manufacturing yield is low.
둘째, 종래 반도체소자의 제조방법에 있어서는 측벽제거시에 게이트전극의 상측 모서리부분이 식각되기 쉽다.Second, in the conventional method of manufacturing a semiconductor device, the upper edge portion of the gate electrode is easily etched when the sidewall is removed.
셋째, 종래 반도체소자의 제조방법에 있어서는 채널부근의 소오스 및 드레인영역이 그레이디드(graded)한 접합을 이루고 있기 때문에 단채널효과가 발생하기 쉬우므로 소자의 동작특성이 나빠진다.Third, in the conventional method of manufacturing a semiconductor device, since the source and drain regions in the vicinity of the channel form a graded junction, short channel effects are likely to occur, thereby deteriorating operation characteristics of the device.
본 발명은 상기 종래 문제점을 해결하기 위해 안출된 것으로, 채널영역부근에 얕은소오스/드레인 접합을 형성하여 단채널효과를 감소시킬 수 있는 반도체소자의 제조방법을 제공함에 그 목적이 있다.Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a method of manufacturing a semiconductor device capable of reducing short channel effects by forming a shallow source / drain junction near a channel region.
또한, 본 발명의 목적은 한 번의 이온공정에 의해 LDD영역과 소오스 및 드레인영역을 동시에 형성하여 공정을 단순화하므로써 고집적소자 제조에 적합하도록 한 반도체소자의 제조방법을 제공함에 있다.It is also an object of the present invention to provide a method for manufacturing a semiconductor device, which is suitable for manufacturing a highly integrated device by simplifying the process by simultaneously forming an LDD region, a source and a drain region by one ion process.
상기 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은 반도체기판을 준비하는 단계.Method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of preparing a semiconductor substrate.
상기 반도체기판상에 제1절연막과 상기 제1절연막 위에 도전층 및 상기 도전층 위에 제2절연막을 차례로 증착하는 단계; 동일 마스크를 이용하여 상기 제2절연막과 도전층 및 제1절연막을 선택적으로 제거하여 캡게이트 절연막과 게이트전극 및 게이트 절연막을 형성하는 단계; 상기 캡게이트 절연막의 상부 및 측벽과, 게이트전극 및 게이트 절연막의 측면을 포함한 반도체기판의 노출된 표면에 제3절연막과 상기 제3절연막 위에 제4절연막을 차례로 증착하는 단계; 상기 제4절연막은 상기 제3절연막 측면에만 남도록 상기 제4절연막을 선택적으로 제거하여 임시측벽을 형성하는 단계; 상기 임시측벽을 포함한 상기 제3절연막을 선택적으로 제거하여 상기 캡게이트 절연막과 게이트전극 및 게이트 절연막 측면에 측별을 형성하는 단계; 상기 측벽을 포함한 캡게이트 절연막을 마스크로하여 상기 반도체기판에 불순물이온을 주입하여 제1 및 제2불순물영역을 형성하는 단계를 포함하여 이루어짐에 그 특징이 있다.Sequentially depositing a first insulating film on the semiconductor substrate, a conductive layer on the first insulating film, and a second insulating film on the conductive layer; Selectively removing the second insulating layer, the conductive layer, and the first insulating layer using the same mask to form a capgate insulating film, a gate electrode, and a gate insulating film; Depositing a third insulating film and a fourth insulating film over the third insulating film on an exposed surface of the semiconductor substrate including upper and sidewalls of the capgate insulating film, and a side surface of the gate electrode and the gate insulating film; Forming a temporary sidewall by selectively removing the fourth insulating layer so that the fourth insulating layer remains only on the side surface of the third insulating layer; Selectively removing the third insulating film including the temporary side wall to form sides on the capgate insulating film, the gate electrode, and side surfaces of the gate insulating film; And implanting impurity ions into the semiconductor substrate using the capgate insulating layer including the sidewalls as a mask, thereby forming first and second impurity regions.
본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명한다.A method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제2도(a) ~ (f)는 본 발명에 따른 반도체소자의 제조공정 단면도이다.2 (a) to (f) are cross-sectional views of the manufacturing process of the semiconductor device according to the present invention.
본 발명에 따른 반도체소자의 제조방법은, 먼제 제2도(a)에 도시된 바와 같이, 반도체기판(11)을 준비하고, 상기 반도체기판(11)상에 제1절연막(12)과 상기 제1절연막(12)상에 금속층(13) 및 상기 금속층(13)상에 제2절연막(14)을 차례로 증착한다.In the method for manufacturing a semiconductor device according to the present invention, as shown in FIG. 2 (a), a semiconductor substrate 11 is prepared, and the first insulating film 12 and the first insulating film 12 are formed on the semiconductor substrate 11. The metal layer 13 is deposited on the first insulating layer 12, and the second insulating layer 14 is sequentially deposited on the metal layer 13.
이때 상기 제1 및 제2절연막(12)(14)은 SiO2를 사용하여 화학기상증착법(CVD)에 의해 증착된다.In this case, the first and second insulating layers 12 and 14 are deposited by chemical vapor deposition (CVD) using SiO 2 .
이어서, 제2도(b)에 도시된 바와 같이, 사진석판술(photolithography) 및 사진식각 공정에 의해 상기 제2절연막(14)과 금속층(13) 및 제1절연막(12)을 선택적으로 제거하여 게이트 절연막(12a)과 게이트전극(13a) 및 캡 게이트 절연막(14a)을 형성한다.Subsequently, as shown in FIG. 2B, the second insulating layer 14, the metal layer 13, and the first insulating layer 12 are selectively removed by photolithography and photolithography. The gate insulating film 12a, the gate electrode 13a, and the cap gate insulating film 14a are formed.
그 다음 제2도(c)에 도시된 바와 같이, 상기 캡 게이트 절연막(14a)의 상부 및 측면과, 게이트전극(13a) 및 게이트 절연막(12a)의 측면을 포함한 상기 반도체기판(11)의 노출된 표면에 제3절연막(15)과 상기 제3절연막(15)위에 제4절연막(16)을 증착한다.Next, as shown in FIG. 2C, the semiconductor substrate 11 is exposed, including the top and side surfaces of the cap gate insulating layer 14a and the side surfaces of the gate electrode 13a and the gate insulating layer 12a. A third insulating film 15 and a fourth insulating film 16 are deposited on the third insulating film 15 on the surface.
이때, 상기 제3절연막(15)과 제4절연막(16)은 식각선택비가 큰 서로 다른 물질을 사용한다.In this case, the third insulating layer 15 and the fourth insulating layer 16 use different materials having high etching selectivity.
또한, 상기 제3 및 제4절연막(15)(16)은 산화막(SiO2)과 질화막(Si3N4)중 어느하나를 선택적으로 사용하며, 상기 제4절연막(16) 대신에 다결정 실리콘(poly-Si)으로 형성할 수 있다.In addition, the third and fourth insulating layers 15 and 16 may selectively use any one of an oxide film SiO 2 and a nitride film Si 3 N 4 , and instead of the fourth insulating layer 16, polycrystalline silicon ( poly-Si).
이어서, 제2도(d)에 도시된 바와 같이, 건식식각동정에 의해 상기 제4절연막(16)을 상기 제3절연막(15)의 측면에만 남도록 상기 제4절연막(16)을 선택적으로 제거하여 임시측벽(16a)을 형성한다.Subsequently, as illustrated in FIG. 2D, the fourth insulating layer 16 is selectively removed so that the fourth insulating layer 16 remains only on the side surface of the third insulating layer 15 by dry etching. The temporary side wall 16a is formed.
그 다음, 제2도(e)에 도시된 바와 같이, 상기 임시측벽(16a)을 포함한 상기 제3절연막(15)을 선택적으로 제거하여 상기 캡 게이트 절연막(14a)과 게이트전극(13a) 및 게이트 절연막(12a)의측면에 측벽(15a)을 형성한다.Next, as shown in FIG. 2E, the cap insulation layer 14a, the gate electrode 13a, and the gate are selectively removed by selectively removing the third insulation layer 15 including the temporary side wall 16a. The side wall 15a is formed on the side surface of the insulating film 12a.
즉, 상기 임시측벽(16a)과 제3절연막(15)의 식각공정은 상기 임시측벽(16a)이 오나전 제거되는 시간동안 상기 제3절연막(15)이 그 두께만큼만 제거되도록 식각선택비를 적절히 조절하여 진행한다.That is, in the etching process of the temporary side wall 16a and the third insulating layer 15, the etching selectivity is appropriately adjusted so that the third insulating layer 15 is removed only by the thickness during the time when the temporary side wall 16a is removed. Proceed by
이때, 상기 측벽(15a)이 하부부분은 반도체기판쪽으로 갈수록 두꺼워지면서 그레이딩(grading) 되도록 한다.At this time, the lower portion of the side wall 15a is gradually thickened toward the semiconductor substrate, thereby grading.
이어서 제2도(f)에 도시된 바와 같이, 상기 측벽(15a)과 캡 게이트 절연막(14a)을 마스크로 하여 반도체기판(11)의 노출된 표면에 불순물이온을 주입한다.Subsequently, as illustrated in FIG. 2F, impurity ions are implanted into the exposed surface of the semiconductor substrate 11 using the sidewalls 15a and the cap gate insulating layer 14a as a mask.
이때 채널부근의 반도체기판(11)부분에는 그 위쪽에 형성된 측벽(15a)두께가 두껍기 때문에 이온주입이 얕게 되고, 채널로부터 떨어진 반도체기판(11)부분에는 이온주입이 깊게 된다.At this time, since the sidewall 15a formed on the upper portion of the semiconductor substrate 11 near the channel is thick, ion implantation is shallow, and ion implantation is deep in the semiconductor substrate 11 portion away from the channel.
이렇게 하여 반도체기판(11)에 제1 및 제2불순물영역(17)(18)과 LDD영역(17a)(18a)이 동시에 형성한다.In this way, the first and second impurity regions 17 and 18 and the LDD regions 17a and 18a are simultaneously formed in the semiconductor substrate 11.
상기와 같이 본 발명에 따른 반도체소자의 제조방법에 있어서는 다음과 같은 특징들이 있다.As described above, the method of manufacturing a semiconductor device according to the present invention has the following characteristics.
첫째, 본 발명에 따른 반도체소자의 제조방법에 있어서는 그레이디드(graded)측벽을 이용하여 채널부근이 반도체기판에 얕은(shallow) 소오스/드레인 접합을 형성할 수 있으므로 단채널효과(short-channel effect)를 감소시킬 수 있다.First, in the method of manufacturing a semiconductor device according to the present invention, since a shallow source / drain junction can be formed in a semiconductor substrate near the channel using a graded side wall, a short-channel effect is obtained. Can be reduced.
둘째, 본 발명에 따른 반도체소자의 제조방법에 잇어서는 한 번의 이온주입공정에 의해 소오스/드레인영역으로 사용하는 불순물영역과 LDD영역을 동시에 형성할 수 있어, 공정을 단순화시킬 수 있으므로 고집적소자 제조시에 적합하다.Second, in the method of manufacturing a semiconductor device according to the present invention, an impurity region and an LDD region used as a source / drain region can be formed at the same time by a single ion implantation process, so that the process can be simplified. Suitable for
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