JPH0348544B2 - - Google Patents

Info

Publication number
JPH0348544B2
JPH0348544B2 JP56010017A JP1001781A JPH0348544B2 JP H0348544 B2 JPH0348544 B2 JP H0348544B2 JP 56010017 A JP56010017 A JP 56010017A JP 1001781 A JP1001781 A JP 1001781A JP H0348544 B2 JPH0348544 B2 JP H0348544B2
Authority
JP
Japan
Prior art keywords
access
memory access
control device
memory
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56010017A
Other languages
English (en)
Japanese (ja)
Other versions
JPS57123463A (en
Inventor
Masanori Takahashi
Minoru Etsuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56010017A priority Critical patent/JPS57123463A/ja
Publication of JPS57123463A publication Critical patent/JPS57123463A/ja
Publication of JPH0348544B2 publication Critical patent/JPH0348544B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Storage Device Security (AREA)
JP56010017A 1981-01-26 1981-01-26 Memory access control system Granted JPS57123463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56010017A JPS57123463A (en) 1981-01-26 1981-01-26 Memory access control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56010017A JPS57123463A (en) 1981-01-26 1981-01-26 Memory access control system

Publications (2)

Publication Number Publication Date
JPS57123463A JPS57123463A (en) 1982-07-31
JPH0348544B2 true JPH0348544B2 (enrdf_load_stackoverflow) 1991-07-24

Family

ID=11738620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56010017A Granted JPS57123463A (en) 1981-01-26 1981-01-26 Memory access control system

Country Status (1)

Country Link
JP (1) JPS57123463A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003030167A (ja) * 2001-04-27 2003-01-31 Internatl Business Mach Corp <Ibm> クラスタ化コンピュータ・システムでの入出力ブリッジ・デバイスのアトミック所有権変更動作

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5940365A (ja) * 1982-08-31 1984-03-06 Toshiba Corp デイスクレコ−ド再生装置
JPS603774A (ja) * 1983-06-22 1985-01-10 Nec Corp システム制御装置
JPH0750457B2 (ja) * 1984-09-10 1995-05-31 富士通株式会社 メモリデバイスのキ−ロツク制御方式
JPS6365553A (ja) * 1986-09-05 1988-03-24 Fujitsu Ltd 入出力装置構成制御デ−タの信頼性保証方式

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003030167A (ja) * 2001-04-27 2003-01-31 Internatl Business Mach Corp <Ibm> クラスタ化コンピュータ・システムでの入出力ブリッジ・デバイスのアトミック所有権変更動作

Also Published As

Publication number Publication date
JPS57123463A (en) 1982-07-31

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