JPH0347776B2 - - Google Patents

Info

Publication number
JPH0347776B2
JPH0347776B2 JP58037499A JP3749983A JPH0347776B2 JP H0347776 B2 JPH0347776 B2 JP H0347776B2 JP 58037499 A JP58037499 A JP 58037499A JP 3749983 A JP3749983 A JP 3749983A JP H0347776 B2 JPH0347776 B2 JP H0347776B2
Authority
JP
Japan
Prior art keywords
gaasfet
gate
dfet
circuit
efet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58037499A
Other languages
English (en)
Japanese (ja)
Other versions
JPS59165524A (ja
Inventor
Yasuo Igawa
Akimichi Hojo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP58037499A priority Critical patent/JPS59165524A/ja
Publication of JPS59165524A publication Critical patent/JPS59165524A/ja
Publication of JPH0347776B2 publication Critical patent/JPH0347776B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0952—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using Schottky type FET MESFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
JP58037499A 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路 Granted JPS59165524A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58037499A JPS59165524A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58037499A JPS59165524A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Publications (2)

Publication Number Publication Date
JPS59165524A JPS59165524A (ja) 1984-09-18
JPH0347776B2 true JPH0347776B2 (enExample) 1991-07-22

Family

ID=12499212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58037499A Granted JPS59165524A (ja) 1983-03-09 1983-03-09 ＧａＡｓ論理集積回路

Country Status (1)

Country Link
JP (1) JPS59165524A (enExample)

Also Published As

Publication number Publication date
JPS59165524A (ja) 1984-09-18

Similar Documents

Publication Publication Date Title
US4853561A (en) Family of noise-immune logic gates and memory cells
US4958089A (en) High output drive FET buffer for providing high initial current to a subsequent stage
US5034629A (en) Output control circuit for reducing through current in CMOS output buffer
JP2549141B2 (ja) Ｂｉｆｅｔ論理回路
US4491747A (en) Logic circuit using depletion mode field effect switching transistors
US4810969A (en) High speed logic circuit having feedback to prevent current in the output stage
JPS6113817A (ja) 金属半導体電界効果トランジスタを用いた電気回路
US4490632A (en) Noninverting amplifier circuit for one propagation delay complex logic gates
US4798972A (en) Apparatus and method for capacitor coupled complementary buffering
US4092548A (en) Substrate bias modulation to improve mosfet circuit performance
GB2327544A (en) Monolithic MOS analogue switch with increased signal voltage range
US4417162A (en) Tri-state logic buffer circuit
US4798979A (en) Schottky diode logic for E-mode FET/D-mode FET VLSI circuits
US4883985A (en) Mesfet latch circuit
US4931670A (en) TTL and CMOS logic compatible GAAS logic family
US4931669A (en) High speed logic circuit having output feedback
US4418292A (en) Logic gate having a noise immunity circuit
US4885480A (en) Source follower field-effect logic gate (SFFL) suitable for III-V technologies
JP2631986B2 (ja) 温度補償した電気回路
US4418291A (en) Logic gate having an isolation FET and noise immunity circuit
US4954730A (en) Complementary FET circuit having merged enhancement/depletion FET output
US5537076A (en) Negative resistance circuit and inverter circuit including the same
JPH0347776B2 (enExample)
JPH09261038A (ja) 論理回路
EP0354241A1 (en) Feedback source coupled fet logic