JPH0346916B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of Application of the Invention] The present invention relates to a sample-and-hold circuit, and particularly to a sample-and-hold circuit in which the capacitance of a hold capacitor is small and
This article relates to a sample and hold circuit suitable for IC implementation. [Background of the Invention] Generally, a sample and hold circuit (hereinafter referred to as an S&H circuit) has a configuration as shown in FIG. In FIG. 1, a signal 10 inputted from an input terminal 1 is transmitted to a sampling pulse generation circuit 7.
The signal is transmitted to the output terminal 2 via the switch S1, which turns on and off according to the sampling pulse 12 generated by the sampling pulse 12 generated by the sampling pulse 12. During the period when switch S1 is on (sampling period), the potential of input terminal 1 is transmitted as is to output terminal 2;
During the period when is off (hold period), switch S
1 is charged to the hold capacitor C1 and output to the output terminal 2.
is maintained at the potential immediately before switch S1 is turned off. Now, as an example, the input signal 10 is the sine wave 10 shown in FIG.
is the pulse 12 shown in the figure, the signal transmitted to the output terminal 2 is the hold signal 14 (shown in Figure 5) that holds the input sine wave 10 at the falling edge of the pulse 12. (shows waveform)
become that way. Here, the operating principle of a specific S&H circuit particularly suitable for IC implementation will be explained with reference to FIGS. 2 and 5. FIG. 2 is a circuit diagram showing an example of a specific S&H circuit. In Fig. 2, the input terminal 1 has an input signal 10
(The sampled and held signal is a sine wave 10 shown in FIG. 5), but terminals 4 and 5 have a sampling pulse 12 that turns on and off switching transistors Q5, Q8 and Q6, Q7, respectively, and a DC voltage corresponding to the sampling pulse 12. 13 has been input. Now, when the sampling pulse 12 is at a high level (hereinafter referred to as the sampling period), the transistors Q5 and Q
8 is turned on, and transistors Q6 and Q7 are turned off. In this state, the circuit shown in Figure 2 consists of differential pair transistors Q1 and Q2 and a load resistor.
This is a negative full feedback amplifier consisting of a differential amplifier of R1 and constant current source I1, and an emitter follower negative feedback circuit of transistors Q4 and Q8. A negative feedback amplifier generally has the configuration shown in Figure 4, and its input/output characteristics are as follows: υ ₀ = A(υ _i −βυ ₀ ) −(1) where υ _i : input signal 100 υ ₀ : output Signal 101 A: Gain of differential amplifier β: Feedback factor of feedback circuit 103. If the above equation (1) is transformed, υ ₀ =A/1+βAυ _i −(2), and now if β=1 and A≫1, υ ₀ ≒υ _i −(3). Therefore, in the sample period in FIG. 2, the input signal becomes the output signal as it is. Note that the value of the load resistor R1 in the circuit shown in FIG. It is determined based on the current value of I1. In this state, the base potential of the transistors Q3 and Q4 is equal to the potential E2 which is the sum of the potential E1 of the output terminal 2 and the base-emitter voltage of the transistors. Next, in FIG. 2, sampling pulse 1
2 is at low level (hereinafter referred to as the hold period).
I will explain about it. In this case, transistor Q
6, Q7 is on, transistors Q5, Q8
is turned off. For this reason, transistor Q3
And the base potential of Q4 is resistor R1 and constant current source I1
Due to the voltage drop caused by I2 and I2, the potential E3 becomes sufficiently lower than the base potential of the transistor Q2 (potential of the output terminal 2) E1. As a result, transistors Q3 and Q4 are turned off, preventing charges from flowing into the hold capacitor C1 from the power supply line. Also, since the collector current of transistor Q5 is not flowing, the transistor Q
1 and Q2 are now in a disconnected state, preventing the charge stored in the hold capacitor C1 from flowing out. Therefore, during the hold period, the potential E1 of the output terminal 2 is held at the potential immediately before the sampling pulse 12 becomes low level, as explained with reference to FIG. The above is the operating principle of the S&H circuit shown in FIG. However, the above S&H circuit has problems in actual operation as described below. The problems will be explained below. Generally, a transistor has junction capacitances C2 and C3 between its base and collector and between its base and emitter, as shown in FIG. In the S&H circuit of FIG. 2 described above, it was necessary to drop the base potential of transistors Q3 and Q4 from E2 to E3 in the process of switching from the sample period to the hold period. For these reasons, the baseline of the transistor Q2 in the S&H circuit shown in FIG. 2 can be equivalently regarded as the equivalent circuit shown in FIG. 6. In FIG. 6, capacitor C4 has the capacitance obtained when the base-collector capacitance of transistor Q2 and the base-emitter capacitance of transistor Q3 are connected in series, and the base-emitter capacitance of transistor Q4 is connected in parallel. This is the capacity when That is, C4=1/1/C2+1/C3+C3 =C2C3/C2+C3+C3 -(4) where C2: capacitance between the base and collector of the transistor C3: capacitance between the base and emitter of the transistor. Potential E1 is the base potential of transistor Q2 immediately before the hold period, potential E2 is the base potential of transistors Q3 and Q4 during the sample period, and potential E3 is the base potential of transistors Q3 and Q4 during the hold period. Note that terminal A of switch S2 corresponds to the baseline of transistors Q3 and Q4 in the S&H circuit of FIG. Therefore, in the above S&H circuit, during the process of switching from the sample period to the hold period due to the capacitor C4, the charge charged in the hold capacitor C1 fluctuates, and as a result, the hold potential appearing at the output terminal 2 is It will change by ΔV. The amount of change ΔV in this hold potential is
In the equivalent circuit of FIG. 6, one end of the capacitor C4 (the one not connected to the hold capacitor C1) is set to a potential E2 during the sampling period by the switch S2 which is switched in accordance with the sampling pulse 12.
Since the potential is E3 during the hold period, ΔV=C4(E3-E2)/C1+C4=ΔQ/C1+C4-(5) where C1: Capacity of the hold capacitor. C4: Capacity expressed by the above formula (4). E2: Transistor Q3, Q4 during sample period
base potential of E3: Hold period transistor Q3, Q4
base potential of ΔQ: Amount of change in the electric charge charged in the hold capacitor C1. It is expressed as Now, since E2>E3, the amount of change ΔV in the hold potential has a negative value. Therefore, the hold potential actually appearing at the output terminal 2 has a waveform shown in FIG. 15, as opposed to 14 in FIG. 5, making it difficult to hold the potential accurately. In addition, especially when sampling and holding high frequency signals or when installing the hold capacitor C1 inside the IC, the capacitance of the hold capacitor C1 must be made small, so the denominator of equation (5) becomes small. As is clear from the above, |ΔV| becomes larger and larger. [Object of the Invention] An object of the present invention is to solve the above-mentioned problems and provide a sample-and-hold circuit suitable for IC implementation that allows accurate sample-and-hold even when the value of the hold capacitor is small. be. [Summary of the Invention] The present invention provides a new capacitor and a switch in order to suppress fluctuations in the charge charged in the hold capacitor during the process of switching from the sample period to the hold period in the sample/hold circuit. This is to keep the hold potential at an accurate value. [Embodiments of the Invention] The principle of the sample-and-hold circuit of the present invention will be explained below with reference to FIG. FIG. 7 is an equivalent circuit diagram when the present invention is applied to the above-mentioned FIG. 6 (equivalent circuit diagram in the process of switching from the sample period to the hold period of the S&H circuit). Hold capacitor C1, capacitor C4, switch S2, etc. have the same configuration as in FIG. 6, and capacitor C5, switch S3, and voltage sources E4 and E5 are newly provided circuits. In FIG. 7, the switch S2 operates at a potential E2 during the sampling period according to the sampling pulse 12 generated by the sampling pulse generation circuit 7.
On the side, the hold period is closed to the potential E3 side.
On the other hand, the switch S3 is similarly closed to the potential E4 side during the sample period and to the potential E5 side during the hold period. As a result, the amount of variation ΔQ in the charge charged in the hold capacitor C1 is expressed as ΔQ=C4(E3-E2)+C5(E5-E4)-(6) where C5 is the capacitance of the capacitor. Therefore, the amount of change ΔV in the hold potential appearing at the output terminal 2 is as follows: ΔV=ΔQ/C1+C4+C5 −(7). Now, if we select capacitor C5 and potentials E4 and E5 so that ΔV = 0, that is, C4 (E3 - E2) = C5 (E4 - E5) - (8), then from equations (6) and (7) above, ΔV=0, and accurate potential can be maintained. The present invention eliminates fluctuations in the hold potential by the means described above. Note that it is clear that the capacitor C5 is not an actual capacitor, but may be a junction capacitance of a transistor or the like like the capacitor C4 described above. FIG. 8 shows an embodiment of an S&H circuit to which the present invention is applied. In FIG. 8, the circuit excluding the resistor R2, the transistor Q9, and the portion surrounded by the broken line is the same circuit as that in FIG. 2 described above, and detailed explanation thereof will be omitted here. In addition, the transistor Q14,
Q15, Q16 and resistors R3, R4, R5 are connected to terminal 6.
A constant current source is constituted by the bias potential 15 given to . In FIG. 8, during the sample period, transistors Q5 and Q8 are on, and transistor Q
6 and Q7 are in the off state. Therefore, the base potentials of transistors Q1 and Q2 are almost equal, and the base potential of transistors Q3 and Q4 is equal to the potential E2, which is the sum of the base potential E1 of transistor Q2 and V _BE (base-emitter voltage of the transistor). ing. Also, transistor Q1
Since the transistor Q5 is in the on state, the collector potential of the transistor Q9 (emitter potential of the transistor Q9) is equal to the collector current of the transistor Q1 and the resistor.
The potential E4 is lower than the power supply voltage +V _CC by the voltage drop caused by R2. The S&H portion in FIG. 8 in this state is equivalent to the equivalent circuit shown in FIG. However, capacitor C4 is expressed as
This is the combined capacitance due to the junction capacitance of transistors Q2, Q3, and Q4 shown in (4), and the capacitor C5
is the base-emitter junction capacitance of transistor Q9. On the other hand, during the hold period, transistors Q6 and Q
7 is in the on state, and the transistors Q5 and Q8 are in the off state, so that the transistors Q1 to Q4 are in the off state. Therefore, the collector potential of transistor Q1 is the power supply voltage +V _CC
(=E5), and the base potential of transistors Q3 and Q4 is increased by the voltage drop due to the collector current of transistors Q6 and Q7 and resistor R1, which is equal to the power supply voltage +
The potential E3 is lower than V _CC . The equivalent circuit in this state is the case in which the switch S2 is closed to the switch terminal D side and the switch S3 is closed to the switch terminal F side in FIG. In the process of switching from the sample period to the hold period, capacitor C4 and transistor Q3
The amount of change ΔQ _a in the charge of hold capacitor C1 due to the change in the base potential of Q4 (E3 − E2) is ΔQ _a = C4 (E3 − E2) − (9). The amount of change ΔQ _b in the charge of the hold capacitor C1 due to the change in emitter potential (E5−E4) is ΔQ _b =C5(E5−E4)−(10). In the S&H circuit of this embodiment, the amount of change in the charge of the hold capacitor C1 is ΔQ _a =-
The potential E4 is determined by selecting the resistor R2 so that ΔQ _b . This resistance R2 and potential E4
From equation (8), E4 = C4 / C5 (E3 - E2) + E5 - (11) R2 = E5 - E4 / IQ ₁ - (12) where, IQ ₁ : collector current of transistor Q1 flowing during the sample period . It is. This allows the present S&H circuit to perform accurate sample and hold. Note that the circuit surrounded by the broken line part 100 is the
The signal held in the H part is output by the emitter follower, and the transistors Q10 and Q
Reference numeral 11 and Q12 denote a base current compensation circuit that prevents the charge charged in the hold capacitor C1 from flowing out due to the base current of the transistor Q13. The operating principle of the base current compensation will be explained below using FIG. 9. Collector current I _C that generally flows through a transistor,
The relationship between base current I _B and emitter current I _E is as follows: I _C = αI _E = I _e −I _B − (13) I _C = α/1 − αI _B − (14) Where, α: common base transistor Current transmission ratio. It is expressed as In FIG. 9, the base current I _B0 flowing into the transistor Q12 is determined by the emitter current I3, and this base current I _B0 flows into the transistor Q1
0 base current I _B0 . or,
The collector current of transistor Q10 is determined by the base current I _B0 , and the relationship between these currents is given by equations (13) and (14): I ₃ =1/1−α _N I _BO −( 15) I ₄ =α _p /1−α _p I _BO − (16) Here, α _N : Current transmission ratio of the common base NPN transistor α _p : Current transmission ratio of the base common PNP transistor. Also, the emitter current of transistor Q12
Since I3 is the collector current I3 of the transistor Q13, and the collector current I4 of the transistor Q10 is the emitter current I4 of the transistor Q11, the base current I _B1 of the transistor Q13 and the base current I _B2 of the transistor Q11 are calculated by formula (13). From equation (16), it is expressed as I _B1 = 1/αNI _B0 −(17) I _B2 = α _p I _B0 −(18). Therefore, transistor Q13
The relationship between the base current I _B1 of the transistor Q11 and the base current I _B2 of the transistor Q11 is as follows from equations (17) and (18): I _B1 /I _B2 = 1/α _N · α _p − (19). In general, α _N ≒1, α _p ≒1, so
From equation (19), it can be considered that I _B1 ≒ I _B2 . As a result, the base current of the transistor Q13 in FIG. 8 is supplied by the base current of the transistor Q11, and it is possible to prevent the charge stored in the hold capacitor C1 from flowing out. Next, another embodiment to which the present invention is applied will be described using FIG. 10. In Figure 10, transistors Q26 and Q27 perform switching operations, and transistor Q is used as a capacitor using junction capacitance.
A constant current source constituted by 9, a transistor 32, and a resistor 13 is a circuit for suppressing fluctuations in the charge charged in the hold capacitor C1 during the process of switching from the sample period to the hold period, and is indicated by the dotted line 100. The part surrounded by is a base current compensation type emitter follower that outputs a hold signal as in FIG. 8 described above. Terminal 1 has an input signal (sampled/held signal) 10
is input, and terminal 4 receives sampling pulse 12
However, terminal 5 has a reference DC voltage for the sampling pulse 12, and terminal 6 has transistors Q16, Q32, Q3 constituting a constant current source.
A bias voltage giving a base potential of 3 is input. A detailed explanation of the operation will be given below. First, the sample period (sampling pulse 12
is at high level), transistor Q2
4, G27 turns on, transistor Q2
5, Q26 is turned off. Therefore, a constant current source consisting of a differential pair of transistors Q21 and Q22, a resistor R11, and a transistor Q33 and a resistor R14 via a transistor Q24 constitutes a differential amplifier. Since the base and collector of the transistor Q22 are connected, the differential amplifier is a negative full feedback amplifier. For this reason,
The signal 10 input from the input terminal 1 is transmitted as is to the base line (terminal 2) of the transistor Q22. Also, in this state,
Since no collector current flows through the transistor Q25, the base of the transistor Q23 is at a potential E2 approximately equal to the current voltage +V _CC , and the transistor Q23 can be regarded as a diode. On the other hand, the collector potential of transistor Q27 is
Since transistor Q27 is in the on state, the potential is lower than the power supply voltage +V _CC by the voltage drop due to the collector current of transistor Q27 and resistor R2.
It's becoming E4. The equivalent circuit of the S&H portion shown in FIG. 10 in this state becomes the equivalent circuit shown in FIG. However, in this case, capacitor C4 in FIG. 7 is the base-emitter junction capacitance of transistor Q23, and capacitor C5 is the base-emitter junction capacitance of transistor Q9. Next, hold period (sampling pulse 12
is low level), transistor Q2
5, Q26 is on, transistor Q24,
Q27 is turned off, and transistors Q21,
Q22 is in a state of discontinuation. Also, transistor Q
Since the transistor Q25 is on, the base potential of the transistor Q23 becomes a potential E3 lower than the power supply voltage +V _CC by the voltage drop caused by the collector current of the transistor Q25 and the resistor R12. However, the potential E3 at this time is set to be lower than the emitter potential of the transistor Q23 in order to prevent charge from flowing from the power supply line to the hold capacitor C1 by turning off the transistor Q23. are doing. On the other hand, since transistor Q27 is in the off state, no collector current flows, and the collector potential (emitter potential of transistor Q9) is the power supply voltage + V _CC
(=E5). The equivalent circuit in this state is shown in FIG. 7, with switch S2 connected to switch terminal D and switch S3 connected to switch terminal D.
It becomes equal when the switch terminal F is closed. From the above, the amount of variation ΔQ _C in the charge charged in the hold capacitor C1 during the process of switching from the sample period to the hold period of the S&H circuit shown in FIG _. −E2)+C5(E5−E4)−(20). In the example shown in Fig. 10, in order to set ΔQ _C = 0 in the above equation (20), C5 = 2 x C4, and the resistance is set so that (E3 - E2) = 2 x (E5 - E4).
The current value of the current source consisting of R2, transistor Q32, and resistor R13 is selected. As explained above, by reducing the variation ΔQ of the charge charged in the hold capacitor C1 to zero, it is possible to suppress the variation ΔV of the hold potential and hold an accurate potential. In the two S&H circuits described above, the amount of change in charge ΔQ in the hold capacitor C1 is suppressed to zero by selecting the value of the resistor R2 in the S&H circuit shown in FIG. In the S&H circuit, resistor R2 and transistor Q
This has been done by selecting the base-emitter junction capacitance of 9. In this way, under the condition that the transistor Q9 is always kept in the inactive state, the means for reducing the charge change amount ΔQ to zero can be arbitrarily selected as long as the condition of equation (8) is satisfied. . Also, especially when integrated into an IC, by using the capacitor C5 as the base-emitter junction capacitance of the transistor and taking the ratio with the capacitor C4,
Even with variations in the absolute values of the capacitors C4 and C5, the amount of change in charge ΔQ can be easily suppressed to zero. [Effects of the Invention] As explained above, by using the present invention, it is possible to accurately sample and hold signals regardless of the capacity of the hold capacitor, and in particular, it is possible to sample and hold high frequency signals and to store signals inside an IC. This is particularly effective when a small capacitance is used as a hold capacitor in a sample/hold circuit where a hold capacitor is provided.

[Brief explanation of drawings]

Figure 1 is the principle diagram of the S&H circuit, Figure 2 is the S&H circuit.
A circuit diagram specifically showing an example of the circuit, FIG. 3 is a circuit diagram for explaining the junction capacitance of a transistor,
Figure 4 is an equivalent circuit diagram of a negative feedback amplifier, Figure 5 is a waveform diagram showing a specific example of approximate signal waveforms at each terminal to explain the S&H circuit diagram, and Figure 6 is a waveform diagram showing a specific example of approximate signal waveforms at each terminal. Fig. 7 is an equivalent circuit diagram of the S&H circuit of the present invention, Fig. 8 is a circuit diagram showing an example of the S&H circuit of the present invention, and Fig. 9 is a circuit diagram of the S&H circuit of the present invention. A circuit diagram for explaining the output circuit of the emitsuta follower, FIG. 10 is the S &
FIG. 2 is a circuit diagram showing an example of an H circuit. Explanation of symbols, C1...Hold capacitor, S
1... Sample switch, Q9... Compensation transistor.

Claims (1)

[Claims] 1: an input terminal; a first transistor having a base connected to the input terminal; an output terminal; a second transistor having a base connected to the output terminal; A constant current source that supplies current to the emitter of the second transistor and stops the current supply during the hold period, a hold capacitor connected to the output terminal, and a constant current source that supplies current to the emitter of the second transistor during the sample period. Negative feedback of the signal to its base,
It consists of a negative feedback transistor that stops its negative feedback operation during the hold period, and a semiconductor element that is connected to the output terminal and operates as a capacitor. The capacitance of this semiconductor element and the voltage applied to it are:
A sample-and-hold circuit, characterized in that the capacitor formed by the second transistor and the negative feedback transistor is configured to cancel fluctuations in the charge of the holding capacitor at the time of period switching. 2 an input terminal, a first transistor whose base is connected to the input terminal, an output terminal, a second transistor whose base is connected to the output terminal, and an emitter of the first and second transistors during the sample period. a constant current source that supplies current to the transistor and stops the current supply during the hold period, a hold capacitor connected to the output terminal, and a negative feedback connection that connects the base and collector of the second transistor; a third transistor provided in the collector current path of the second transistor, conductive during the sample period and depleted during the hold period;
It consists of a semiconductor element that is connected to the output terminal and operates as a capacitor, and the capacitance of this semiconductor element and the voltage applied to it are:
A sample-and-hold circuit, characterized in that the capacitance formed by the second and third transistors is designed to cancel out fluctuations in the charge of the holding capacitor at the time of period switching.